From: Jon Lin <jon....@rock-chips.com> rk3588 pcie3 phy has a pcie3_phymode to decide how to use the four lanes, add support in dts so that we can customize in dts.
The phy has two port and each port has two lane: pcie30_phy_mode[2:0] 2: aggregation 1: bifurcation for port 1 0: bifurcation for port 0 Signed-off-by: Kever Yang <kever.y...@rock-chips.com> Signed-off-by: Jon Lin <jon....@rock-chips.com> --- include/dt-bindings/phy/phy-snps-pcie3.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 include/dt-bindings/phy/phy-snps-pcie3.h diff --git a/include/dt-bindings/phy/phy-snps-pcie3.h b/include/dt-bindings/phy/phy-snps-pcie3.h new file mode 100644 index 0000000000..5006947f22 --- /dev/null +++ b/include/dt-bindings/phy/phy-snps-pcie3.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2021 Rockchip Electronics Co., Ltd. + */ + +#ifndef _DT_BINDINGS_PHY_SNPS_PCIE3 +#define _DT_BINDINGS_PHY_SNPS_PCIE3 + +/* + * pcie30_phy_mode[2:0] + * bit2: aggregation + * bit1: bifurcation for port 1 + * bit0: bifurcation for port 0 + */ +#define PHY_MODE_PCIE_AGGREGATION 4 /* PCIe3x4 */ +#define PHY_MODE_PCIE_NANBNB 0 /* P1:PCIe3x2 + P0:PCIe3x2 */ +#define PHY_MODE_PCIE_NANBBI 1 /* P1:PCIe3x2 + P0:PCIe3x1*2 */ +#define PHY_MODE_PCIE_NABINB 2 /* P1:PCIe3x1*2 + P0:PCIe3x2 */ +#define PHY_MODE_PCIE_NABIBI 3 /* P1:PCIe3x1*2 + P0:PCIe3x1*2 */ + +#endif /* _DT_BINDINGS_PHY_SNPS_PCIE3 */ -- 2.39.1
