Re: [PATCH 7/9] net: dwc_eth_qos: Add board_interface_eth_init() for i.MX8M Plus
On Thu, Jan 19, 2023 at 11:45 PM Marek Vasut wrote:
>
> Implement common board_interface_eth_init() and call it from the DWMAC
> driver to configure IOMUXC GPR[1] register according to the PHY mode
> obtained from DT. This supports all three interface modes supported by
> the i.MX8M Plus DWMAC and supersedes current board-side configuration
> of the same IOMUX GPR[1] duplicated in the board files.
>
> Signed-off-by: Marek Vasut
> ---
> Cc: "Ariel D'Alessandro"
> Cc: "NXP i.MX U-Boot Team"
> Cc: Andrey Zhizhikin
> Cc: Fabio Estevam
> Cc: Joe Hershberger
> Cc: Lukasz Majewski
> Cc: Marcel Ziswiler
> Cc: Marek Vasut
> Cc: Michael Trimarchi
> Cc: Peng Fan
> Cc: Ramon Fried
> Cc: Sean Anderson
> Cc: Stefano Babic
> Cc: Tim Harvey
> Cc: Tommaso Merciai
> Cc: u-boot@lists.denx.de
> ---
> arch/arm/include/asm/arch-imx8m/imx-regs.h | 8 -
> arch/arm/mach-imx/imx8m/clock_imx8mm.c | 37 ++
> drivers/net/dwc_eth_qos_imx.c | 4 +++
> 3 files changed, 48 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h
> b/arch/arm/include/asm/arch-imx8m/imx-regs.h
> index 20f4699a12b..88e7f7dc557 100644
> --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
> +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
> @@ -85,7 +85,13 @@
> #define DDRC_IPS_BASE_ADDR(X) (0x3d40 + ((X) * 0x200))
> #define DDR_CSD1_BASE_ADDR 0x4000
>
> -#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x7
> +#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN BIT(21)
> +#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SELBIT(20)
> +#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_ENBIT(19)
> +#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK GENMASK(18, 16)
> +#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MII (0 << 16)
> +#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RGMII(1 << 16)
> +#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RMII (4 << 16)
> #define FEC_QUIRK_ENET_MAC
>
> #define CAAM_ARB_BASE_ADDR (0x0010)
> diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> index 494bfbedc8c..069087c2cfd 100644
> --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
> @@ -15,6 +15,7 @@
> #include
> #include
> #include
> +#include
>
> DECLARE_GLOBAL_DATA_PTR;
>
> @@ -872,6 +873,42 @@ int set_clk_eqos(enum enet_freq type)
>
> return 0;
> }
> +
> +int board_interface_eth_init(struct udevice *dev, phy_interface_t
> interface_type)
> +{
> + struct iomuxc_gpr_base_regs *gpr =
> + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
> +
> + clrbits_le32(>gpr[1],
> +IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK |
> +IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN |
> +IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL |
> +IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN);
> +
> + switch (interface_type) {
> + case PHY_INTERFACE_MODE_MII:
> + setbits_le32(>gpr[1],
> +IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN |
> +IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MII);
> + break;
> + case PHY_INTERFACE_MODE_RMII:
> + setbits_le32(>gpr[1],
> +IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL |
> +IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN |
> +IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RMII);
> + break;
> + case PHY_INTERFACE_MODE_RGMII:
> + setbits_le32(>gpr[1],
> +IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN |
> +IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN |
> +IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RGMII);
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> #endif
>
> #ifdef CONFIG_FEC_MXC
> diff --git a/drivers/net/dwc_eth_qos_imx.c b/drivers/net/dwc_eth_qos_imx.c
> index 55080257623..f8f4cbc0257 100644
> --- a/drivers/net/dwc_eth_qos_imx.c
> +++ b/drivers/net/dwc_eth_qos_imx.c
> @@ -54,6 +54,10 @@ static int eqos_probe_resources_imx(struct udevice *dev)
> return -EINVAL;
> }
>
> + ret = board_interface_eth_init(dev, interface);
> + if (ret)
> + return -EINVAL;
> +
> eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0);
>
> ret = clk_get_by_name(dev, "stmmaceth", >clk_master_bus);
> --
> 2.39.0
>
Reviewed-by: Ramon Fried
[PATCH 7/9] net: dwc_eth_qos: Add board_interface_eth_init() for i.MX8M Plus
Implement common board_interface_eth_init() and call it from the DWMAC
driver to configure IOMUXC GPR[1] register according to the PHY mode
obtained from DT. This supports all three interface modes supported by
the i.MX8M Plus DWMAC and supersedes current board-side configuration
of the same IOMUX GPR[1] duplicated in the board files.
Signed-off-by: Marek Vasut
---
Cc: "Ariel D'Alessandro"
Cc: "NXP i.MX U-Boot Team"
Cc: Andrey Zhizhikin
Cc: Fabio Estevam
Cc: Joe Hershberger
Cc: Lukasz Majewski
Cc: Marcel Ziswiler
Cc: Marek Vasut
Cc: Michael Trimarchi
Cc: Peng Fan
Cc: Ramon Fried
Cc: Sean Anderson
Cc: Stefano Babic
Cc: Tim Harvey
Cc: Tommaso Merciai
Cc: u-boot@lists.denx.de
---
arch/arm/include/asm/arch-imx8m/imx-regs.h | 8 -
arch/arm/mach-imx/imx8m/clock_imx8mm.c | 37 ++
drivers/net/dwc_eth_qos_imx.c | 4 +++
3 files changed, 48 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h
b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 20f4699a12b..88e7f7dc557 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -85,7 +85,13 @@
#define DDRC_IPS_BASE_ADDR(X) (0x3d40 + ((X) * 0x200))
#define DDR_CSD1_BASE_ADDR 0x4000
-#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK 0x7
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN BIT(21)
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SELBIT(20)
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_ENBIT(19)
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK GENMASK(18, 16)
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MII (0 << 16)
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RGMII(1 << 16)
+#define IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RMII (4 << 16)
#define FEC_QUIRK_ENET_MAC
#define CAAM_ARB_BASE_ADDR (0x0010)
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
index 494bfbedc8c..069087c2cfd 100644
--- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c
+++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c
@@ -15,6 +15,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -872,6 +873,42 @@ int set_clk_eqos(enum enet_freq type)
return 0;
}
+
+int board_interface_eth_init(struct udevice *dev, phy_interface_t
interface_type)
+{
+ struct iomuxc_gpr_base_regs *gpr =
+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
+
+ clrbits_le32(>gpr[1],
+IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK |
+IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN |
+IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL |
+IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN);
+
+ switch (interface_type) {
+ case PHY_INTERFACE_MODE_MII:
+ setbits_le32(>gpr[1],
+IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN |
+IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MII);
+ break;
+ case PHY_INTERFACE_MODE_RMII:
+ setbits_le32(>gpr[1],
+IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_TX_CLK_SEL |
+IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN |
+IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RMII);
+ break;
+ case PHY_INTERFACE_MODE_RGMII:
+ setbits_le32(>gpr[1],
+IOMUXC_GPR_GPR1_GPR_ENET_QOS_RGMII_EN |
+IOMUXC_GPR_GPR1_GPR_ENET_QOS_CLK_GEN_EN |
+IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_RGMII);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
#endif
#ifdef CONFIG_FEC_MXC
diff --git a/drivers/net/dwc_eth_qos_imx.c b/drivers/net/dwc_eth_qos_imx.c
index 55080257623..f8f4cbc0257 100644
--- a/drivers/net/dwc_eth_qos_imx.c
+++ b/drivers/net/dwc_eth_qos_imx.c
@@ -54,6 +54,10 @@ static int eqos_probe_resources_imx(struct udevice *dev)
return -EINVAL;
}
+ ret = board_interface_eth_init(dev, interface);
+ if (ret)
+ return -EINVAL;
+
eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0);
ret = clk_get_by_name(dev, "stmmaceth", >clk_master_bus);
--
2.39.0
