Re: [PATCH 8/8] net: gmac_rockchip: Add dwc_eth_qos support

2020-05-09 Thread David Wu 

Hi Stephen,

在 2020/5/1 上午6:52, Stephen Warren 写道:

I'm really confused; with a filename like gmac_rockchip.c that sounds
like it's driver for a MAC device. DWC EQoS is also a MAC device. The
two shouldn't be related or coupled in any way.

I think what you need is to completely drop this patch (and the patch
which creates dwc_eth_qos.h), and instead make the DWC EQoS driver
itself directly support the Rockchip SoC by adding RK's compatible value
to the list of compatible values that the EQoS driver supports, along
with new probe functions etc.

Maybe this requires splitting some PHY code out of gmac_rockchip into a
common/separate PHY driver? I haven't looked at the code to know if
that's required.


I think this relationship is like the current designware.c and 
gmac_rockchip.c, except that the designware driver becomes DWC EQoS. In 
fact, most of the code is the same, because it is the same controller, 
and there are a few differences related to Soc implemented in 
gmac_rockchip.c, this is the purpose of my series of patches, and the 
code must be compatible with the previous Rockchip Socs.

Re: [PATCH 8/8] net: gmac_rockchip: Add dwc_eth_qos support

2020-04-30 Thread Stephen Warren 
On 4/30/20 4:45 AM, David Wu wrote:
> Change the original data structure so that Rockchip's Soc
> gmac controller can support the designware.c and dwc_eth_qos.c
> drivers, a Soc can only support one.

I'm really confused; with a filename like gmac_rockchip.c that sounds
like it's driver for a MAC device. DWC EQoS is also a MAC device. The
two shouldn't be related or coupled in any way.

I think what you need is to completely drop this patch (and the patch
which creates dwc_eth_qos.h), and instead make the DWC EQoS driver
itself directly support the Rockchip SoC by adding RK's compatible value
to the list of compatible values that the EQoS driver supports, along
with new probe functions etc.

Maybe this requires splitting some PHY code out of gmac_rockchip into a
common/separate PHY driver? I haven't looked at the code to know if
that's required.

[PATCH 8/8] net: gmac_rockchip: Add dwc_eth_qos support

2020-04-30 Thread David Wu 
Change the original data structure so that Rockchip's Soc
gmac controller can support the designware.c and dwc_eth_qos.c
drivers, a Soc can only support one.

Signed-off-by: David Wu 
---

 drivers/net/Kconfig |   2 +-
 drivers/net/gmac_rockchip.c | 160 ++--
 2 files changed, 135 insertions(+), 27 deletions(-)

diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 4d1013c984..07d2b0787c 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -482,7 +482,7 @@ config PIC32_ETH
 
 config GMAC_ROCKCHIP
bool "Rockchip Synopsys Designware Ethernet MAC"
-   depends on DM_ETH && ETH_DESIGNWARE
+   depends on DM_ETH && (ETH_DESIGNWARE || DWC_ETH_QOS)
help
  This driver provides Rockchip SoCs network support based on the
  Synopsys Designware driver.
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index e152faf083..aa2bab4203 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -25,26 +25,39 @@
 #include 
 #include 
 #include "designware.h"
+#include "dwc_eth_qos.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 #define DELAY_ENABLE(soc, tx, rx) \
(((tx) ? soc##_TXCLK_DLY_ENA_GMAC_ENABLE : 
soc##_TXCLK_DLY_ENA_GMAC_DISABLE) | \
((rx) ? soc##_RXCLK_DLY_ENA_GMAC_ENABLE : 
soc##_RXCLK_DLY_ENA_GMAC_DISABLE))
 
+struct rockchip_eth_dev {
+   union {
+   struct eqos_priv eqos;
+   struct dw_eth_dev dw;
+   };
+};
+
 /*
  * Platform data for the gmac
  *
  * dw_eth_pdata: Required platform data for designware driver (must be first)
  */
 struct gmac_rockchip_platdata {
-   struct dw_eth_pdata dw_eth_pdata;
+   union {
+   struct dw_eth_pdata dw_eth_pdata;
+   struct eth_pdata eth_pdata;
+   };
+   bool has_gmac4;
bool clock_input;
int tx_delay;
int rx_delay;
 };
 
 struct rk_gmac_ops {
-   int (*fix_mac_speed)(struct dw_eth_dev *priv);
+   const struct eqos_config config;
+   int (*fix_mac_speed)(struct rockchip_eth_dev *dev);
void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata);
void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata);
 };
@@ -55,6 +68,9 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice 
*dev)
struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev);
const char *string;
 
+   if (device_is_compatible(dev, "snps,dwmac-4.20a"))
+   pdata->has_gmac4 = true;
+
string = dev_read_string(dev, "clock_in_out");
if (!strcmp(string, "input"))
pdata->clock_input = true;
@@ -71,11 +87,15 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice 
*dev)
if (pdata->rx_delay == -ENOENT)
pdata->rx_delay = dev_read_u32_default(dev, "rx-delay", 0x10);
 
-   return designware_eth_ofdata_to_platdata(dev);
+   if (!pdata->has_gmac4)
+   return designware_eth_ofdata_to_platdata(dev);
+
+   return 0;
 }
 
-static int px30_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int px30_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
 {
+   struct dw_eth_dev *priv = >dw;
struct px30_grf *grf;
struct clk clk_speed;
int speed, ret;
@@ -115,8 +135,9 @@ static int px30_gmac_fix_mac_speed(struct dw_eth_dev *priv)
return 0;
 }
 
-static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3228_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
 {
+   struct dw_eth_dev *priv = >dw;
struct rk322x_grf *grf;
int clk;
enum {
@@ -148,8 +169,9 @@ static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev 
*priv)
return 0;
 }
 
-static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3288_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
 {
+   struct dw_eth_dev *priv = >dw;
struct rk3288_grf *grf;
int clk;
 
@@ -174,8 +196,9 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev 
*priv)
return 0;
 }
 
-static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3308_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
 {
+   struct dw_eth_dev *priv = >dw;
struct rk3308_grf *grf;
struct clk clk_speed;
int speed, ret;
@@ -215,8 +238,9 @@ static int rk3308_gmac_fix_mac_speed(struct dw_eth_dev 
*priv)
return 0;
 }
 
-static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3328_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
 {
+   struct dw_eth_dev *priv = >dw;
struct rk3328_grf_regs *grf;
int clk;
enum {
@@ -248,8 +272,9 @@ static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev 
*priv)
return 0;
 }
 
-static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+static int rk3368_gmac_fix_mac_speed(struct rockchip_eth_dev *dev)
 {
+   struct dw_eth_dev *priv = >dw;
struct rk3368_grf *grf;
int clk;