A38x BootROM MMC_CMD_SEND_STATUS timeouts (Was: Re: [PATCH RFC u-boot-mvebu 0/2] arm: mvebu: Fix eMMC boot)
CCing MMC maintainers (Peng Fan & Jaehoon Chung). Could you help us with this issue? Expected usage is following: BootROM reads and execute SPL from eMMC (BootROM has its own code for reading eMMC), SPL initialize mmc driver and after SPL finish its work it returns control back to BootROM and BootROM reads and execute proper U-Boot from eMMC. And issue is that after SPL returns control back to BootROM it looks like that BootROM is sending MMC_CMD_SEND_STATUS command to eMMC but it timeouts (timeout takes 5 minutes!) and after it correctly reads proper U-Boot from eMMC and continues booting proper U-Boot. I guess that there is an issue that SPL's mmc driver changes eMMC state into something which BootROM does not expect. On Friday 24 March 2023 02:55:55 Martin Rowe wrote: > On Thu, 23 Mar 2023 at 19:01, Pali Rohár wrote: > > There is issue with that 5 minutes delay. But I think it should be fixed > > by the patch which I sent earlier, which restore partition config based > > on mmc->part_config in board_return_to_bootrom(). Could you test it? > > https://lore.kernel.org/u-boot/20230305160416.xc7wlzmkaociwcf7@pali/ > > Now when mmc->part_config is correctly initialized it should restore > > configuration and BootROM does not have to get that "Timeout waiting > > card ready" error. > > Still takes about 5 minutes. The output is below with MMC tracing. I > confirmed the value of mmc->part_config used for > restore_emmc_boot_part_config is the same as what is initially > detected early in SPL (both are 10 with mmc partconf 0 0 1 1 and > zeroed boot0). > > ERROR: Invalid kwbimage v1 > mmc_load_image_raw_sector: mmc block read error > spl: mmc: wrong boot mode > Trying to boot from BOOTROM > CMD_SEND:6 > ARG 0x03b30a00 > MMC_RSP_R1b 0x0900 > CMD_SEND:13 > ARG 0x0001 > MMC_RSP_R1,5,6,7 0x0900 > CURR STATE:4 > Returning to BootROM (return address 0x05c4)... I looked at the BootROM disassembled code and error message "Timeout waiting card ready" is printed when following mmc command cmdidx=0xd, resptype=0x15, cmdarg=(something)<<0x10 timeouts. 0xd is in U-Boot MMC_CMD_SEND_STATUS 0x15 is in U-Boot MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC|MMC_RSP_BUSY which looks like U-Boot's MMC_RSP_R2 with BUSY bit set It looks like U-Boot function mmc_send_status() where that "something" in cmdarg is mmc->rca. If command does not timeout then BootROM next checks if response has BIT(8) set and if response mask 0x1e00 matches value 0xe00. If both are truth then BootROM mark call as successful. If response ANDed with mask 0xfdf94080 is non-zero then BootROM prints "Status Error: " with hex response value and mark call as unsuccessful. I'm looking at the U-Boot code and this BootROM logic looks very similar to U-Boot function mmc_poll_for_busy(), just without first call mmc_wait_dat0(). BIT(8) is MMC_STATUS_RDY_FOR_DATA 0x1e00 is MMC_STATUS_CURR_STATE 0xe00 is MMC_STATE_PRG 0xfdf94080 is MMC_STATUS_MASK I'm not mmc expert, but this looks like MMC_CMD_SEND_STATUS is failing in BootROM after U-Boot returns control back to the BootROM.
Re: [PATCH RFC u-boot-mvebu 0/2] arm: mvebu: Fix eMMC boot
On Thu, 23 Mar 2023 at 19:01, Pali Rohár wrote: > > On Thursday 23 March 2023 12:24:13 Martin Rowe wrote: > > On Wed, 22 Mar 2023 at 19:09, Pali Rohár wrote: > > > > > > On Wednesday 22 March 2023 18:59:45 Pali Rohár wrote: > > > > On Wednesday 22 March 2023 13:45:56 Martin Rowe wrote: > > > > > On Wed, 22 Mar 2023 at 12:38, Martin Rowe > > > > > wrote: > > > > > > > > > > > > On Tue, 21 Mar 2023 at 08:08, Pali Rohár wrote: > > > > > >> > > > > > >> On Tuesday 21 March 2023 08:01:16 Martin Rowe wrote: > > > > > >> > On Mon, 20 Mar 2023 at 17:33, Pali Rohár wrote: > > > > > >> > > > > > > >> > > On Monday 20 March 2023 11:48:59 Martin Rowe wrote: > > > > > >> > > > On Sun, 19 Mar 2023 at 16:22, Pali Rohár > > > > > >> > > > wrote: > > > > > >> > > > > > > > > >> > > > > On Sunday 19 March 2023 00:32:01 Martin Rowe wrote: > > > > > >> > > > > > On Mon, 6 Mar 2023 at 11:53, Pali Rohár > > > > > >> > > > > > wrote: > > > > > >> > > > > > > > > > > >> > > > > > > Could you try to print mmc->part_config (ideally as > > > > > >> > > > > > > early as > > > > > >> > > possible)? > > > > > >> > > > > > > > > > > > >> > > > > > > > > > > >> > > > > > In SPL mmc->part_config is 255 > > > > > >> > > > > > In main u-boot at the start of clearfog.c board_init() > > > > > >> > > mmc->part_config > > > > > >> > > > > is > > > > > >> > > > > > 255 > > > > > >> > > > > > In main u-boot at the start of clearfog.c checkboard() > > > > > >> > > mmc->part_config > > > > > >> > > > > is > > > > > >> > > > > > 8 (ack: 0, partition_enable: 1, access: 0) > > > > > >> > > > > > > > > > >> > > > > 255 is uninitialized value. > > > > > >> > > > > > > > > > >> > > > > > If I set partition_enable to 2, I get the same result > > > > > >> > > > > > except the > > > > > >> > > value is > > > > > >> > > > > > 16 (ack: 0, partition_enable: 2, access: 0) instead of > > > > > >> > > > > > 8 for the > > > > > >> > > last > > > > > >> > > > > value > > > > > >> > > > > > > > > > >> > > > > Try to change "access" bits. > > > > > >> > > > > > > > > > >> > > > > > > > > > > >> > > > > > BootROM - 1.73 > > > > > >> > > > > > > > > > > >> > > > > > Booting from MMC > > > > > >> > > > > > > > > > > >> > > > > > U-Boot SPL 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 > > > > > >> > > > > > 2023 - > > > > > >> > > 10:05:32 > > > > > >> > > > > > +1000) > > > > > >> > > > > > High speed PHY - Version: 2.0 > > > > > >> > > > > > EEPROM TLV detection failed: Using static config for > > > > > >> > > > > > Clearfog Pro. > > > > > >> > > > > > Detected Device ID 6828 > > > > > >> > > > > > board SerDes lanes topology details: > > > > > >> > > > > > | Lane # | Speed | Type | > > > > > >> > > > > > > > > > > >> > > > > > | 0| 3 | SATA0 | > > > > > >> > > > > > | 1| 0 | SGMII1 | > > > > > >> > > > > > | 2| 5 | PCIe1 | > > > > > >> > > > > > | 3| 5 | USB3 HOST1 | > > > > > >> > > > > > | 4| 5 | PCIe2 | > > > > > >> > > > > > | 5| 0 | SGMII2 | > > > > > >> > > > > > > > > > > >> > > > > > High speed PHY - Ended Successfully > > > > > >> > > > > > mv_ddr: 14.0.0 > > > > > >> > > > > > DDR3 Training Sequence - Switching XBAR Window to > > > > > >> > > > > > FastPath Window > > > > > >> > > > > > mv_ddr: completed successfully > > > > > >> > > > > > spl.c spl_boot_device part_config = 255 > > > > > >> > > > > > Trying to boot from MMC1 > > > > > >> > > > > > > > > > > >> > > > > > > > > > > >> > > > > > U-Boot 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 > > > > > >> > > > > > - 10:05:32 > > > > > >> > > +1000) > > > > > >> > > > > > > > > > > >> > > > > > SoC: MV88F6828-A0 at 1600 MHz > > > > > >> > > > > > DRAM: 1 GiB (800 MHz, 32-bit, ECC not enabled) > > > > > >> > > > > > clearfog.c board_init part_config = 255 > > > > > >> > > > > > Core: 38 devices, 22 uclasses, devicetree: separate > > > > > >> > > > > > MMC: mv_sdh: 0 > > > > > >> > > > > > Loading Environment from MMC... *** Warning - bad CRC, > > > > > >> > > > > > using default > > > > > >> > > > > > environment > > > > > >> > > > > > > > > > > >> > > > > > Model: SolidRun Clearfog A1 > > > > > >> > > > > > clearfog.c checkboard part_config = 8 > > > > > >> > > > > > Board: SolidRun Clearfog Pro > > > > > >> > > > > > Net: > > > > > >> > > > > > Warning: ethernet@7 (eth1) using random MAC address - > > > > > >> > > > > 32:16:0e:b4:d1:d8 > > > > > >> > > > > > eth1: ethernet@7 > > > > > >> > > > > > Warning: ethernet@3 (eth2) using random MAC address - > > > > > >> > > > > 72:30:3f:79:07:12 > > > > > >> > > > > > , eth2: ethernet@3 > > > > > >> > > > > > Warning: ethernet@34000 (eth3) using random MAC address - > > > > > >> > > > > 82:fb:71:23:46:4f > > > > > >> > > > > > , eth3: ethernet@34000 > > > > > >> > > > > > Hit any key to stop autoboot: 0 > > > > > >> > > > > > => mmc partconf 0 > >
Re: [PATCH RFC u-boot-mvebu 0/2] arm: mvebu: Fix eMMC boot
On Thursday 23 March 2023 12:24:13 Martin Rowe wrote: > On Wed, 22 Mar 2023 at 19:09, Pali Rohár wrote: > > > > On Wednesday 22 March 2023 18:59:45 Pali Rohár wrote: > > > On Wednesday 22 March 2023 13:45:56 Martin Rowe wrote: > > > > On Wed, 22 Mar 2023 at 12:38, Martin Rowe > > > > wrote: > > > > > > > > > > On Tue, 21 Mar 2023 at 08:08, Pali Rohár wrote: > > > > >> > > > > >> On Tuesday 21 March 2023 08:01:16 Martin Rowe wrote: > > > > >> > On Mon, 20 Mar 2023 at 17:33, Pali Rohár wrote: > > > > >> > > > > > >> > > On Monday 20 March 2023 11:48:59 Martin Rowe wrote: > > > > >> > > > On Sun, 19 Mar 2023 at 16:22, Pali Rohár > > > > >> > > > wrote: > > > > >> > > > > > > > >> > > > > On Sunday 19 March 2023 00:32:01 Martin Rowe wrote: > > > > >> > > > > > On Mon, 6 Mar 2023 at 11:53, Pali Rohár > > > > >> > > > > > wrote: > > > > >> > > > > > > > > > >> > > > > > > Could you try to print mmc->part_config (ideally as > > > > >> > > > > > > early as > > > > >> > > possible)? > > > > >> > > > > > > > > > > >> > > > > > > > > > >> > > > > > In SPL mmc->part_config is 255 > > > > >> > > > > > In main u-boot at the start of clearfog.c board_init() > > > > >> > > mmc->part_config > > > > >> > > > > is > > > > >> > > > > > 255 > > > > >> > > > > > In main u-boot at the start of clearfog.c checkboard() > > > > >> > > mmc->part_config > > > > >> > > > > is > > > > >> > > > > > 8 (ack: 0, partition_enable: 1, access: 0) > > > > >> > > > > > > > > >> > > > > 255 is uninitialized value. > > > > >> > > > > > > > > >> > > > > > If I set partition_enable to 2, I get the same result > > > > >> > > > > > except the > > > > >> > > value is > > > > >> > > > > > 16 (ack: 0, partition_enable: 2, access: 0) instead of 8 > > > > >> > > > > > for the > > > > >> > > last > > > > >> > > > > value > > > > >> > > > > > > > > >> > > > > Try to change "access" bits. > > > > >> > > > > > > > > >> > > > > > > > > > >> > > > > > BootROM - 1.73 > > > > >> > > > > > > > > > >> > > > > > Booting from MMC > > > > >> > > > > > > > > > >> > > > > > U-Boot SPL 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 > > > > >> > > > > > 2023 - > > > > >> > > 10:05:32 > > > > >> > > > > > +1000) > > > > >> > > > > > High speed PHY - Version: 2.0 > > > > >> > > > > > EEPROM TLV detection failed: Using static config for > > > > >> > > > > > Clearfog Pro. > > > > >> > > > > > Detected Device ID 6828 > > > > >> > > > > > board SerDes lanes topology details: > > > > >> > > > > > | Lane # | Speed | Type | > > > > >> > > > > > > > > > >> > > > > > | 0| 3 | SATA0 | > > > > >> > > > > > | 1| 0 | SGMII1 | > > > > >> > > > > > | 2| 5 | PCIe1 | > > > > >> > > > > > | 3| 5 | USB3 HOST1 | > > > > >> > > > > > | 4| 5 | PCIe2 | > > > > >> > > > > > | 5| 0 | SGMII2 | > > > > >> > > > > > > > > > >> > > > > > High speed PHY - Ended Successfully > > > > >> > > > > > mv_ddr: 14.0.0 > > > > >> > > > > > DDR3 Training Sequence - Switching XBAR Window to FastPath > > > > >> > > > > > Window > > > > >> > > > > > mv_ddr: completed successfully > > > > >> > > > > > spl.c spl_boot_device part_config = 255 > > > > >> > > > > > Trying to boot from MMC1 > > > > >> > > > > > > > > > >> > > > > > > > > > >> > > > > > U-Boot 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - > > > > >> > > > > > 10:05:32 > > > > >> > > +1000) > > > > >> > > > > > > > > > >> > > > > > SoC: MV88F6828-A0 at 1600 MHz > > > > >> > > > > > DRAM: 1 GiB (800 MHz, 32-bit, ECC not enabled) > > > > >> > > > > > clearfog.c board_init part_config = 255 > > > > >> > > > > > Core: 38 devices, 22 uclasses, devicetree: separate > > > > >> > > > > > MMC: mv_sdh: 0 > > > > >> > > > > > Loading Environment from MMC... *** Warning - bad CRC, > > > > >> > > > > > using default > > > > >> > > > > > environment > > > > >> > > > > > > > > > >> > > > > > Model: SolidRun Clearfog A1 > > > > >> > > > > > clearfog.c checkboard part_config = 8 > > > > >> > > > > > Board: SolidRun Clearfog Pro > > > > >> > > > > > Net: > > > > >> > > > > > Warning: ethernet@7 (eth1) using random MAC address - > > > > >> > > > > 32:16:0e:b4:d1:d8 > > > > >> > > > > > eth1: ethernet@7 > > > > >> > > > > > Warning: ethernet@3 (eth2) using random MAC address - > > > > >> > > > > 72:30:3f:79:07:12 > > > > >> > > > > > , eth2: ethernet@3 > > > > >> > > > > > Warning: ethernet@34000 (eth3) using random MAC address - > > > > >> > > > > 82:fb:71:23:46:4f > > > > >> > > > > > , eth3: ethernet@34000 > > > > >> > > > > > Hit any key to stop autoboot: 0 > > > > >> > > > > > => mmc partconf 0 > > > > >> > > > > > EXT_CSD[179], PARTITION_CONFIG: > > > > >> > > > > > BOOT_ACK: 0x0 > > > > >> > > > > > BOOT_PARTITION_ENABLE: 0x1 > > > > >> > > > > > PARTITION_ACCESS: 0x0 > > > > >> > > > > > > > > > >> > > > > > > > > > >> > > > > > > > > > >> > > > > >
Re: [PATCH RFC u-boot-mvebu 0/2] arm: mvebu: Fix eMMC boot
On Wed, 22 Mar 2023 at 19:09, Pali Rohár wrote: > > On Wednesday 22 March 2023 18:59:45 Pali Rohár wrote: > > On Wednesday 22 March 2023 13:45:56 Martin Rowe wrote: > > > On Wed, 22 Mar 2023 at 12:38, Martin Rowe wrote: > > > > > > > > On Tue, 21 Mar 2023 at 08:08, Pali Rohár wrote: > > > >> > > > >> On Tuesday 21 March 2023 08:01:16 Martin Rowe wrote: > > > >> > On Mon, 20 Mar 2023 at 17:33, Pali Rohár wrote: > > > >> > > > > >> > > On Monday 20 March 2023 11:48:59 Martin Rowe wrote: > > > >> > > > On Sun, 19 Mar 2023 at 16:22, Pali Rohár wrote: > > > >> > > > > > > >> > > > > On Sunday 19 March 2023 00:32:01 Martin Rowe wrote: > > > >> > > > > > On Mon, 6 Mar 2023 at 11:53, Pali Rohár > > > >> > > > > > wrote: > > > >> > > > > > > > > >> > > > > > > Could you try to print mmc->part_config (ideally as early > > > >> > > > > > > as > > > >> > > possible)? > > > >> > > > > > > > > > >> > > > > > > > > >> > > > > > In SPL mmc->part_config is 255 > > > >> > > > > > In main u-boot at the start of clearfog.c board_init() > > > >> > > mmc->part_config > > > >> > > > > is > > > >> > > > > > 255 > > > >> > > > > > In main u-boot at the start of clearfog.c checkboard() > > > >> > > mmc->part_config > > > >> > > > > is > > > >> > > > > > 8 (ack: 0, partition_enable: 1, access: 0) > > > >> > > > > > > > >> > > > > 255 is uninitialized value. > > > >> > > > > > > > >> > > > > > If I set partition_enable to 2, I get the same result except > > > >> > > > > > the > > > >> > > value is > > > >> > > > > > 16 (ack: 0, partition_enable: 2, access: 0) instead of 8 > > > >> > > > > > for the > > > >> > > last > > > >> > > > > value > > > >> > > > > > > > >> > > > > Try to change "access" bits. > > > >> > > > > > > > >> > > > > > > > > >> > > > > > BootROM - 1.73 > > > >> > > > > > > > > >> > > > > > Booting from MMC > > > >> > > > > > > > > >> > > > > > U-Boot SPL 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - > > > >> > > 10:05:32 > > > >> > > > > > +1000) > > > >> > > > > > High speed PHY - Version: 2.0 > > > >> > > > > > EEPROM TLV detection failed: Using static config for > > > >> > > > > > Clearfog Pro. > > > >> > > > > > Detected Device ID 6828 > > > >> > > > > > board SerDes lanes topology details: > > > >> > > > > > | Lane # | Speed | Type | > > > >> > > > > > > > > >> > > > > > | 0| 3 | SATA0 | > > > >> > > > > > | 1| 0 | SGMII1 | > > > >> > > > > > | 2| 5 | PCIe1 | > > > >> > > > > > | 3| 5 | USB3 HOST1 | > > > >> > > > > > | 4| 5 | PCIe2 | > > > >> > > > > > | 5| 0 | SGMII2 | > > > >> > > > > > > > > >> > > > > > High speed PHY - Ended Successfully > > > >> > > > > > mv_ddr: 14.0.0 > > > >> > > > > > DDR3 Training Sequence - Switching XBAR Window to FastPath > > > >> > > > > > Window > > > >> > > > > > mv_ddr: completed successfully > > > >> > > > > > spl.c spl_boot_device part_config = 255 > > > >> > > > > > Trying to boot from MMC1 > > > >> > > > > > > > > >> > > > > > > > > >> > > > > > U-Boot 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - > > > >> > > > > > 10:05:32 > > > >> > > +1000) > > > >> > > > > > > > > >> > > > > > SoC: MV88F6828-A0 at 1600 MHz > > > >> > > > > > DRAM: 1 GiB (800 MHz, 32-bit, ECC not enabled) > > > >> > > > > > clearfog.c board_init part_config = 255 > > > >> > > > > > Core: 38 devices, 22 uclasses, devicetree: separate > > > >> > > > > > MMC: mv_sdh: 0 > > > >> > > > > > Loading Environment from MMC... *** Warning - bad CRC, using > > > >> > > > > > default > > > >> > > > > > environment > > > >> > > > > > > > > >> > > > > > Model: SolidRun Clearfog A1 > > > >> > > > > > clearfog.c checkboard part_config = 8 > > > >> > > > > > Board: SolidRun Clearfog Pro > > > >> > > > > > Net: > > > >> > > > > > Warning: ethernet@7 (eth1) using random MAC address - > > > >> > > > > 32:16:0e:b4:d1:d8 > > > >> > > > > > eth1: ethernet@7 > > > >> > > > > > Warning: ethernet@3 (eth2) using random MAC address - > > > >> > > > > 72:30:3f:79:07:12 > > > >> > > > > > , eth2: ethernet@3 > > > >> > > > > > Warning: ethernet@34000 (eth3) using random MAC address - > > > >> > > > > 82:fb:71:23:46:4f > > > >> > > > > > , eth3: ethernet@34000 > > > >> > > > > > Hit any key to stop autoboot: 0 > > > >> > > > > > => mmc partconf 0 > > > >> > > > > > EXT_CSD[179], PARTITION_CONFIG: > > > >> > > > > > BOOT_ACK: 0x0 > > > >> > > > > > BOOT_PARTITION_ENABLE: 0x1 > > > >> > > > > > PARTITION_ACCESS: 0x0 > > > >> > > > > > > > > >> > > > > > > > > >> > > > > > > > > >> > > > > > BootROM - 1.73 > > > >> > > > > > > > > >> > > > > > Booting from MMC > > > >> > > > > > > > > >> > > > > > U-Boot SPL 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - > > > >> > > 10:05:32 > > > >> > > > > > +1000) > > > >> > > > > > High speed PHY - Version: 2.0 > > > >> > > > > > EEPROM TLV detection failed: Using static
Re: [PATCH RFC u-boot-mvebu 0/2] arm: mvebu: Fix eMMC boot
On Wednesday 22 March 2023 18:59:45 Pali Rohár wrote: > On Wednesday 22 March 2023 13:45:56 Martin Rowe wrote: > > On Wed, 22 Mar 2023 at 12:38, Martin Rowe wrote: > > > > > > On Tue, 21 Mar 2023 at 08:08, Pali Rohár wrote: > > >> > > >> On Tuesday 21 March 2023 08:01:16 Martin Rowe wrote: > > >> > On Mon, 20 Mar 2023 at 17:33, Pali Rohár wrote: > > >> > > > >> > > On Monday 20 March 2023 11:48:59 Martin Rowe wrote: > > >> > > > On Sun, 19 Mar 2023 at 16:22, Pali Rohár wrote: > > >> > > > > > >> > > > > On Sunday 19 March 2023 00:32:01 Martin Rowe wrote: > > >> > > > > > On Mon, 6 Mar 2023 at 11:53, Pali Rohár > > >> > > > > > wrote: > > >> > > > > > > > >> > > > > > > Could you try to print mmc->part_config (ideally as early as > > >> > > possible)? > > >> > > > > > > > > >> > > > > > > > >> > > > > > In SPL mmc->part_config is 255 > > >> > > > > > In main u-boot at the start of clearfog.c board_init() > > >> > > mmc->part_config > > >> > > > > is > > >> > > > > > 255 > > >> > > > > > In main u-boot at the start of clearfog.c checkboard() > > >> > > mmc->part_config > > >> > > > > is > > >> > > > > > 8 (ack: 0, partition_enable: 1, access: 0) > > >> > > > > > > >> > > > > 255 is uninitialized value. > > >> > > > > > > >> > > > > > If I set partition_enable to 2, I get the same result except > > >> > > > > > the > > >> > > value is > > >> > > > > > 16 (ack: 0, partition_enable: 2, access: 0) instead of 8 for > > >> > > > > > the > > >> > > last > > >> > > > > value > > >> > > > > > > >> > > > > Try to change "access" bits. > > >> > > > > > > >> > > > > > > > >> > > > > > BootROM - 1.73 > > >> > > > > > > > >> > > > > > Booting from MMC > > >> > > > > > > > >> > > > > > U-Boot SPL 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - > > >> > > 10:05:32 > > >> > > > > > +1000) > > >> > > > > > High speed PHY - Version: 2.0 > > >> > > > > > EEPROM TLV detection failed: Using static config for Clearfog > > >> > > > > > Pro. > > >> > > > > > Detected Device ID 6828 > > >> > > > > > board SerDes lanes topology details: > > >> > > > > > | Lane # | Speed | Type | > > >> > > > > > > > >> > > > > > | 0| 3 | SATA0 | > > >> > > > > > | 1| 0 | SGMII1 | > > >> > > > > > | 2| 5 | PCIe1 | > > >> > > > > > | 3| 5 | USB3 HOST1 | > > >> > > > > > | 4| 5 | PCIe2 | > > >> > > > > > | 5| 0 | SGMII2 | > > >> > > > > > > > >> > > > > > High speed PHY - Ended Successfully > > >> > > > > > mv_ddr: 14.0.0 > > >> > > > > > DDR3 Training Sequence - Switching XBAR Window to FastPath > > >> > > > > > Window > > >> > > > > > mv_ddr: completed successfully > > >> > > > > > spl.c spl_boot_device part_config = 255 > > >> > > > > > Trying to boot from MMC1 > > >> > > > > > > > >> > > > > > > > >> > > > > > U-Boot 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - > > >> > > > > > 10:05:32 > > >> > > +1000) > > >> > > > > > > > >> > > > > > SoC: MV88F6828-A0 at 1600 MHz > > >> > > > > > DRAM: 1 GiB (800 MHz, 32-bit, ECC not enabled) > > >> > > > > > clearfog.c board_init part_config = 255 > > >> > > > > > Core: 38 devices, 22 uclasses, devicetree: separate > > >> > > > > > MMC: mv_sdh: 0 > > >> > > > > > Loading Environment from MMC... *** Warning - bad CRC, using > > >> > > > > > default > > >> > > > > > environment > > >> > > > > > > > >> > > > > > Model: SolidRun Clearfog A1 > > >> > > > > > clearfog.c checkboard part_config = 8 > > >> > > > > > Board: SolidRun Clearfog Pro > > >> > > > > > Net: > > >> > > > > > Warning: ethernet@7 (eth1) using random MAC address - > > >> > > > > 32:16:0e:b4:d1:d8 > > >> > > > > > eth1: ethernet@7 > > >> > > > > > Warning: ethernet@3 (eth2) using random MAC address - > > >> > > > > 72:30:3f:79:07:12 > > >> > > > > > , eth2: ethernet@3 > > >> > > > > > Warning: ethernet@34000 (eth3) using random MAC address - > > >> > > > > 82:fb:71:23:46:4f > > >> > > > > > , eth3: ethernet@34000 > > >> > > > > > Hit any key to stop autoboot: 0 > > >> > > > > > => mmc partconf 0 > > >> > > > > > EXT_CSD[179], PARTITION_CONFIG: > > >> > > > > > BOOT_ACK: 0x0 > > >> > > > > > BOOT_PARTITION_ENABLE: 0x1 > > >> > > > > > PARTITION_ACCESS: 0x0 > > >> > > > > > > > >> > > > > > > > >> > > > > > > > >> > > > > > BootROM - 1.73 > > >> > > > > > > > >> > > > > > Booting from MMC > > >> > > > > > > > >> > > > > > U-Boot SPL 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - > > >> > > 10:05:32 > > >> > > > > > +1000) > > >> > > > > > High speed PHY - Version: 2.0 > > >> > > > > > EEPROM TLV detection failed: Using static config for Clearfog > > >> > > > > > Pro. > > >> > > > > > Detected Device ID 6828 > > >> > > > > > board SerDes lanes topology details: > > >> > > > > > | Lane # | Speed | Type | > > >> > > > > > > > >> > > > > > | 0| 3 | SATA0 | > > >> > > > > > |
Re: [PATCH RFC u-boot-mvebu 0/2] arm: mvebu: Fix eMMC boot
On Wednesday 22 March 2023 13:45:56 Martin Rowe wrote: > On Wed, 22 Mar 2023 at 12:38, Martin Rowe wrote: > > > > On Tue, 21 Mar 2023 at 08:08, Pali Rohár wrote: > >> > >> On Tuesday 21 March 2023 08:01:16 Martin Rowe wrote: > >> > On Mon, 20 Mar 2023 at 17:33, Pali Rohár wrote: > >> > > >> > > On Monday 20 March 2023 11:48:59 Martin Rowe wrote: > >> > > > On Sun, 19 Mar 2023 at 16:22, Pali Rohár wrote: > >> > > > > >> > > > > On Sunday 19 March 2023 00:32:01 Martin Rowe wrote: > >> > > > > > On Mon, 6 Mar 2023 at 11:53, Pali Rohár wrote: > >> > > > > > > >> > > > > > > Could you try to print mmc->part_config (ideally as early as > >> > > possible)? > >> > > > > > > > >> > > > > > > >> > > > > > In SPL mmc->part_config is 255 > >> > > > > > In main u-boot at the start of clearfog.c board_init() > >> > > mmc->part_config > >> > > > > is > >> > > > > > 255 > >> > > > > > In main u-boot at the start of clearfog.c checkboard() > >> > > mmc->part_config > >> > > > > is > >> > > > > > 8 (ack: 0, partition_enable: 1, access: 0) > >> > > > > > >> > > > > 255 is uninitialized value. > >> > > > > > >> > > > > > If I set partition_enable to 2, I get the same result except the > >> > > value is > >> > > > > > 16 (ack: 0, partition_enable: 2, access: 0) instead of 8 for the > >> > > last > >> > > > > value > >> > > > > > >> > > > > Try to change "access" bits. > >> > > > > > >> > > > > > > >> > > > > > BootROM - 1.73 > >> > > > > > > >> > > > > > Booting from MMC > >> > > > > > > >> > > > > > U-Boot SPL 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - > >> > > 10:05:32 > >> > > > > > +1000) > >> > > > > > High speed PHY - Version: 2.0 > >> > > > > > EEPROM TLV detection failed: Using static config for Clearfog > >> > > > > > Pro. > >> > > > > > Detected Device ID 6828 > >> > > > > > board SerDes lanes topology details: > >> > > > > > | Lane # | Speed | Type | > >> > > > > > > >> > > > > > | 0| 3 | SATA0 | > >> > > > > > | 1| 0 | SGMII1 | > >> > > > > > | 2| 5 | PCIe1 | > >> > > > > > | 3| 5 | USB3 HOST1 | > >> > > > > > | 4| 5 | PCIe2 | > >> > > > > > | 5| 0 | SGMII2 | > >> > > > > > > >> > > > > > High speed PHY - Ended Successfully > >> > > > > > mv_ddr: 14.0.0 > >> > > > > > DDR3 Training Sequence - Switching XBAR Window to FastPath Window > >> > > > > > mv_ddr: completed successfully > >> > > > > > spl.c spl_boot_device part_config = 255 > >> > > > > > Trying to boot from MMC1 > >> > > > > > > >> > > > > > > >> > > > > > U-Boot 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - > >> > > > > > 10:05:32 > >> > > +1000) > >> > > > > > > >> > > > > > SoC: MV88F6828-A0 at 1600 MHz > >> > > > > > DRAM: 1 GiB (800 MHz, 32-bit, ECC not enabled) > >> > > > > > clearfog.c board_init part_config = 255 > >> > > > > > Core: 38 devices, 22 uclasses, devicetree: separate > >> > > > > > MMC: mv_sdh: 0 > >> > > > > > Loading Environment from MMC... *** Warning - bad CRC, using > >> > > > > > default > >> > > > > > environment > >> > > > > > > >> > > > > > Model: SolidRun Clearfog A1 > >> > > > > > clearfog.c checkboard part_config = 8 > >> > > > > > Board: SolidRun Clearfog Pro > >> > > > > > Net: > >> > > > > > Warning: ethernet@7 (eth1) using random MAC address - > >> > > > > 32:16:0e:b4:d1:d8 > >> > > > > > eth1: ethernet@7 > >> > > > > > Warning: ethernet@3 (eth2) using random MAC address - > >> > > > > 72:30:3f:79:07:12 > >> > > > > > , eth2: ethernet@3 > >> > > > > > Warning: ethernet@34000 (eth3) using random MAC address - > >> > > > > 82:fb:71:23:46:4f > >> > > > > > , eth3: ethernet@34000 > >> > > > > > Hit any key to stop autoboot: 0 > >> > > > > > => mmc partconf 0 > >> > > > > > EXT_CSD[179], PARTITION_CONFIG: > >> > > > > > BOOT_ACK: 0x0 > >> > > > > > BOOT_PARTITION_ENABLE: 0x1 > >> > > > > > PARTITION_ACCESS: 0x0 > >> > > > > > > >> > > > > > > >> > > > > > > >> > > > > > BootROM - 1.73 > >> > > > > > > >> > > > > > Booting from MMC > >> > > > > > > >> > > > > > U-Boot SPL 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - > >> > > 10:05:32 > >> > > > > > +1000) > >> > > > > > High speed PHY - Version: 2.0 > >> > > > > > EEPROM TLV detection failed: Using static config for Clearfog > >> > > > > > Pro. > >> > > > > > Detected Device ID 6828 > >> > > > > > board SerDes lanes topology details: > >> > > > > > | Lane # | Speed | Type | > >> > > > > > > >> > > > > > | 0| 3 | SATA0 | > >> > > > > > | 1| 0 | SGMII1 | > >> > > > > > | 2| 5 | PCIe1 | > >> > > > > > | 3| 5 | USB3 HOST1 | > >> > > > > > | 4| 5 | PCIe2 | > >> > > > > > | 5| 0 | SGMII2 | > >> > > > > > > >> > > > > > High speed PHY - Ended Successfully > >> > > > > > mv_ddr: 14.0.0 > >> > >
Re: [PATCH RFC u-boot-mvebu 0/2] arm: mvebu: Fix eMMC boot
On Wed, 22 Mar 2023 at 12:38, Martin Rowe wrote: > > On Tue, 21 Mar 2023 at 08:08, Pali Rohár wrote: >> >> On Tuesday 21 March 2023 08:01:16 Martin Rowe wrote: >> > On Mon, 20 Mar 2023 at 17:33, Pali Rohár wrote: >> > >> > > On Monday 20 March 2023 11:48:59 Martin Rowe wrote: >> > > > On Sun, 19 Mar 2023 at 16:22, Pali Rohár wrote: >> > > > >> > > > > On Sunday 19 March 2023 00:32:01 Martin Rowe wrote: >> > > > > > On Mon, 6 Mar 2023 at 11:53, Pali Rohár wrote: >> > > > > > >> > > > > > > Could you try to print mmc->part_config (ideally as early as >> > > possible)? >> > > > > > > >> > > > > > >> > > > > > In SPL mmc->part_config is 255 >> > > > > > In main u-boot at the start of clearfog.c board_init() >> > > mmc->part_config >> > > > > is >> > > > > > 255 >> > > > > > In main u-boot at the start of clearfog.c checkboard() >> > > mmc->part_config >> > > > > is >> > > > > > 8 (ack: 0, partition_enable: 1, access: 0) >> > > > > >> > > > > 255 is uninitialized value. >> > > > > >> > > > > > If I set partition_enable to 2, I get the same result except the >> > > value is >> > > > > > 16 (ack: 0, partition_enable: 2, access: 0) instead of 8 for the >> > > last >> > > > > value >> > > > > >> > > > > Try to change "access" bits. >> > > > > >> > > > > > >> > > > > > BootROM - 1.73 >> > > > > > >> > > > > > Booting from MMC >> > > > > > >> > > > > > U-Boot SPL 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - >> > > 10:05:32 >> > > > > > +1000) >> > > > > > High speed PHY - Version: 2.0 >> > > > > > EEPROM TLV detection failed: Using static config for Clearfog Pro. >> > > > > > Detected Device ID 6828 >> > > > > > board SerDes lanes topology details: >> > > > > > | Lane # | Speed | Type | >> > > > > > >> > > > > > | 0| 3 | SATA0 | >> > > > > > | 1| 0 | SGMII1 | >> > > > > > | 2| 5 | PCIe1 | >> > > > > > | 3| 5 | USB3 HOST1 | >> > > > > > | 4| 5 | PCIe2 | >> > > > > > | 5| 0 | SGMII2 | >> > > > > > >> > > > > > High speed PHY - Ended Successfully >> > > > > > mv_ddr: 14.0.0 >> > > > > > DDR3 Training Sequence - Switching XBAR Window to FastPath Window >> > > > > > mv_ddr: completed successfully >> > > > > > spl.c spl_boot_device part_config = 255 >> > > > > > Trying to boot from MMC1 >> > > > > > >> > > > > > >> > > > > > U-Boot 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - 10:05:32 >> > > +1000) >> > > > > > >> > > > > > SoC: MV88F6828-A0 at 1600 MHz >> > > > > > DRAM: 1 GiB (800 MHz, 32-bit, ECC not enabled) >> > > > > > clearfog.c board_init part_config = 255 >> > > > > > Core: 38 devices, 22 uclasses, devicetree: separate >> > > > > > MMC: mv_sdh: 0 >> > > > > > Loading Environment from MMC... *** Warning - bad CRC, using >> > > > > > default >> > > > > > environment >> > > > > > >> > > > > > Model: SolidRun Clearfog A1 >> > > > > > clearfog.c checkboard part_config = 8 >> > > > > > Board: SolidRun Clearfog Pro >> > > > > > Net: >> > > > > > Warning: ethernet@7 (eth1) using random MAC address - >> > > > > 32:16:0e:b4:d1:d8 >> > > > > > eth1: ethernet@7 >> > > > > > Warning: ethernet@3 (eth2) using random MAC address - >> > > > > 72:30:3f:79:07:12 >> > > > > > , eth2: ethernet@3 >> > > > > > Warning: ethernet@34000 (eth3) using random MAC address - >> > > > > 82:fb:71:23:46:4f >> > > > > > , eth3: ethernet@34000 >> > > > > > Hit any key to stop autoboot: 0 >> > > > > > => mmc partconf 0 >> > > > > > EXT_CSD[179], PARTITION_CONFIG: >> > > > > > BOOT_ACK: 0x0 >> > > > > > BOOT_PARTITION_ENABLE: 0x1 >> > > > > > PARTITION_ACCESS: 0x0 >> > > > > > >> > > > > > >> > > > > > >> > > > > > BootROM - 1.73 >> > > > > > >> > > > > > Booting from MMC >> > > > > > >> > > > > > U-Boot SPL 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - >> > > 10:05:32 >> > > > > > +1000) >> > > > > > High speed PHY - Version: 2.0 >> > > > > > EEPROM TLV detection failed: Using static config for Clearfog Pro. >> > > > > > Detected Device ID 6828 >> > > > > > board SerDes lanes topology details: >> > > > > > | Lane # | Speed | Type | >> > > > > > >> > > > > > | 0| 3 | SATA0 | >> > > > > > | 1| 0 | SGMII1 | >> > > > > > | 2| 5 | PCIe1 | >> > > > > > | 3| 5 | USB3 HOST1 | >> > > > > > | 4| 5 | PCIe2 | >> > > > > > | 5| 0 | SGMII2 | >> > > > > > >> > > > > > High speed PHY - Ended Successfully >> > > > > > mv_ddr: 14.0.0 >> > > > > > DDR3 Training Sequence - Switching XBAR Window to FastPath Window >> > > > > > mv_ddr: completed successfully >> > > > > > spl.c spl_boot_device part_config = 255 >> > > > > > Trying to boot from MMC1 >> > > > > > >> > > > > > >> > > > > > U-Boot 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - 10:05:32 >> > > +1000) >> > > > > > >> > > >
Re: [PATCH RFC u-boot-mvebu 0/2] arm: mvebu: Fix eMMC boot
On Tue, 21 Mar 2023 at 08:08, Pali Rohár wrote: > On Tuesday 21 March 2023 08:01:16 Martin Rowe wrote: > > On Mon, 20 Mar 2023 at 17:33, Pali Rohár wrote: > > > > > On Monday 20 March 2023 11:48:59 Martin Rowe wrote: > > > > On Sun, 19 Mar 2023 at 16:22, Pali Rohár wrote: > > > > > > > > > On Sunday 19 March 2023 00:32:01 Martin Rowe wrote: > > > > > > On Mon, 6 Mar 2023 at 11:53, Pali Rohár wrote: > > > > > > > > > > > > > Could you try to print mmc->part_config (ideally as early as > > > possible)? > > > > > > > > > > > > > > > > > > > In SPL mmc->part_config is 255 > > > > > > In main u-boot at the start of clearfog.c board_init() > > > mmc->part_config > > > > > is > > > > > > 255 > > > > > > In main u-boot at the start of clearfog.c checkboard() > > > mmc->part_config > > > > > is > > > > > > 8 (ack: 0, partition_enable: 1, access: 0) > > > > > > > > > > 255 is uninitialized value. > > > > > > > > > > > If I set partition_enable to 2, I get the same result except the > > > value is > > > > > > 16 (ack: 0, partition_enable: 2, access: 0) instead of 8 for the > > > last > > > > > value > > > > > > > > > > Try to change "access" bits. > > > > > > > > > > > > > > > > > BootROM - 1.73 > > > > > > > > > > > > Booting from MMC > > > > > > > > > > > > U-Boot SPL 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - > > > 10:05:32 > > > > > > +1000) > > > > > > High speed PHY - Version: 2.0 > > > > > > EEPROM TLV detection failed: Using static config for Clearfog > Pro. > > > > > > Detected Device ID 6828 > > > > > > board SerDes lanes topology details: > > > > > > | Lane # | Speed | Type | > > > > > > > > > > > > | 0| 3 | SATA0 | > > > > > > | 1| 0 | SGMII1 | > > > > > > | 2| 5 | PCIe1 | > > > > > > | 3| 5 | USB3 HOST1 | > > > > > > | 4| 5 | PCIe2 | > > > > > > | 5| 0 | SGMII2 | > > > > > > > > > > > > High speed PHY - Ended Successfully > > > > > > mv_ddr: 14.0.0 > > > > > > DDR3 Training Sequence - Switching XBAR Window to FastPath Window > > > > > > mv_ddr: completed successfully > > > > > > spl.c spl_boot_device part_config = 255 > > > > > > Trying to boot from MMC1 > > > > > > > > > > > > > > > > > > U-Boot 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - > 10:05:32 > > > +1000) > > > > > > > > > > > > SoC: MV88F6828-A0 at 1600 MHz > > > > > > DRAM: 1 GiB (800 MHz, 32-bit, ECC not enabled) > > > > > > clearfog.c board_init part_config = 255 > > > > > > Core: 38 devices, 22 uclasses, devicetree: separate > > > > > > MMC: mv_sdh: 0 > > > > > > Loading Environment from MMC... *** Warning - bad CRC, using > default > > > > > > environment > > > > > > > > > > > > Model: SolidRun Clearfog A1 > > > > > > clearfog.c checkboard part_config = 8 > > > > > > Board: SolidRun Clearfog Pro > > > > > > Net: > > > > > > Warning: ethernet@7 (eth1) using random MAC address - > > > > > 32:16:0e:b4:d1:d8 > > > > > > eth1: ethernet@7 > > > > > > Warning: ethernet@3 (eth2) using random MAC address - > > > > > 72:30:3f:79:07:12 > > > > > > , eth2: ethernet@3 > > > > > > Warning: ethernet@34000 (eth3) using random MAC address - > > > > > 82:fb:71:23:46:4f > > > > > > , eth3: ethernet@34000 > > > > > > Hit any key to stop autoboot: 0 > > > > > > => mmc partconf 0 > > > > > > EXT_CSD[179], PARTITION_CONFIG: > > > > > > BOOT_ACK: 0x0 > > > > > > BOOT_PARTITION_ENABLE: 0x1 > > > > > > PARTITION_ACCESS: 0x0 > > > > > > > > > > > > > > > > > > > > > > > > BootROM - 1.73 > > > > > > > > > > > > Booting from MMC > > > > > > > > > > > > U-Boot SPL 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - > > > 10:05:32 > > > > > > +1000) > > > > > > High speed PHY - Version: 2.0 > > > > > > EEPROM TLV detection failed: Using static config for Clearfog > Pro. > > > > > > Detected Device ID 6828 > > > > > > board SerDes lanes topology details: > > > > > > | Lane # | Speed | Type | > > > > > > > > > > > > | 0| 3 | SATA0 | > > > > > > | 1| 0 | SGMII1 | > > > > > > | 2| 5 | PCIe1 | > > > > > > | 3| 5 | USB3 HOST1 | > > > > > > | 4| 5 | PCIe2 | > > > > > > | 5| 0 | SGMII2 | > > > > > > > > > > > > High speed PHY - Ended Successfully > > > > > > mv_ddr: 14.0.0 > > > > > > DDR3 Training Sequence - Switching XBAR Window to FastPath Window > > > > > > mv_ddr: completed successfully > > > > > > spl.c spl_boot_device part_config = 255 > > > > > > Trying to boot from MMC1 > > > > > > > > > > > > > > > > > > U-Boot 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - > 10:05:32 > > > +1000) > > > > > > > > > > > > SoC: MV88F6828-A0 at 1600 MHz > > > > > > DRAM: 1 GiB (800 MHz, 32-bit, ECC not enabled) > > > > > > clearfog.c board_init part_config = 255 > > > > > > Core: 38 devices, 22
Re: [PATCH RFC u-boot-mvebu 0/2] arm: mvebu: Fix eMMC boot
On Tuesday 21 March 2023 08:01:16 Martin Rowe wrote: > On Mon, 20 Mar 2023 at 17:33, Pali Rohár wrote: > > > On Monday 20 March 2023 11:48:59 Martin Rowe wrote: > > > On Sun, 19 Mar 2023 at 16:22, Pali Rohár wrote: > > > > > > > On Sunday 19 March 2023 00:32:01 Martin Rowe wrote: > > > > > On Mon, 6 Mar 2023 at 11:53, Pali Rohár wrote: > > > > > > > > > > > Could you try to print mmc->part_config (ideally as early as > > possible)? > > > > > > > > > > > > > > > > In SPL mmc->part_config is 255 > > > > > In main u-boot at the start of clearfog.c board_init() > > mmc->part_config > > > > is > > > > > 255 > > > > > In main u-boot at the start of clearfog.c checkboard() > > mmc->part_config > > > > is > > > > > 8 (ack: 0, partition_enable: 1, access: 0) > > > > > > > > 255 is uninitialized value. > > > > > > > > > If I set partition_enable to 2, I get the same result except the > > value is > > > > > 16 (ack: 0, partition_enable: 2, access: 0) instead of 8 for the > > last > > > > value > > > > > > > > Try to change "access" bits. > > > > > > > > > > > > > > BootROM - 1.73 > > > > > > > > > > Booting from MMC > > > > > > > > > > U-Boot SPL 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - > > 10:05:32 > > > > > +1000) > > > > > High speed PHY - Version: 2.0 > > > > > EEPROM TLV detection failed: Using static config for Clearfog Pro. > > > > > Detected Device ID 6828 > > > > > board SerDes lanes topology details: > > > > > | Lane # | Speed | Type | > > > > > > > > > > | 0| 3 | SATA0 | > > > > > | 1| 0 | SGMII1 | > > > > > | 2| 5 | PCIe1 | > > > > > | 3| 5 | USB3 HOST1 | > > > > > | 4| 5 | PCIe2 | > > > > > | 5| 0 | SGMII2 | > > > > > > > > > > High speed PHY - Ended Successfully > > > > > mv_ddr: 14.0.0 > > > > > DDR3 Training Sequence - Switching XBAR Window to FastPath Window > > > > > mv_ddr: completed successfully > > > > > spl.c spl_boot_device part_config = 255 > > > > > Trying to boot from MMC1 > > > > > > > > > > > > > > > U-Boot 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - 10:05:32 > > +1000) > > > > > > > > > > SoC: MV88F6828-A0 at 1600 MHz > > > > > DRAM: 1 GiB (800 MHz, 32-bit, ECC not enabled) > > > > > clearfog.c board_init part_config = 255 > > > > > Core: 38 devices, 22 uclasses, devicetree: separate > > > > > MMC: mv_sdh: 0 > > > > > Loading Environment from MMC... *** Warning - bad CRC, using default > > > > > environment > > > > > > > > > > Model: SolidRun Clearfog A1 > > > > > clearfog.c checkboard part_config = 8 > > > > > Board: SolidRun Clearfog Pro > > > > > Net: > > > > > Warning: ethernet@7 (eth1) using random MAC address - > > > > 32:16:0e:b4:d1:d8 > > > > > eth1: ethernet@7 > > > > > Warning: ethernet@3 (eth2) using random MAC address - > > > > 72:30:3f:79:07:12 > > > > > , eth2: ethernet@3 > > > > > Warning: ethernet@34000 (eth3) using random MAC address - > > > > 82:fb:71:23:46:4f > > > > > , eth3: ethernet@34000 > > > > > Hit any key to stop autoboot: 0 > > > > > => mmc partconf 0 > > > > > EXT_CSD[179], PARTITION_CONFIG: > > > > > BOOT_ACK: 0x0 > > > > > BOOT_PARTITION_ENABLE: 0x1 > > > > > PARTITION_ACCESS: 0x0 > > > > > > > > > > > > > > > > > > > > BootROM - 1.73 > > > > > > > > > > Booting from MMC > > > > > > > > > > U-Boot SPL 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - > > 10:05:32 > > > > > +1000) > > > > > High speed PHY - Version: 2.0 > > > > > EEPROM TLV detection failed: Using static config for Clearfog Pro. > > > > > Detected Device ID 6828 > > > > > board SerDes lanes topology details: > > > > > | Lane # | Speed | Type | > > > > > > > > > > | 0| 3 | SATA0 | > > > > > | 1| 0 | SGMII1 | > > > > > | 2| 5 | PCIe1 | > > > > > | 3| 5 | USB3 HOST1 | > > > > > | 4| 5 | PCIe2 | > > > > > | 5| 0 | SGMII2 | > > > > > > > > > > High speed PHY - Ended Successfully > > > > > mv_ddr: 14.0.0 > > > > > DDR3 Training Sequence - Switching XBAR Window to FastPath Window > > > > > mv_ddr: completed successfully > > > > > spl.c spl_boot_device part_config = 255 > > > > > Trying to boot from MMC1 > > > > > > > > > > > > > > > U-Boot 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - 10:05:32 > > +1000) > > > > > > > > > > SoC: MV88F6828-A0 at 1600 MHz > > > > > DRAM: 1 GiB (800 MHz, 32-bit, ECC not enabled) > > > > > clearfog.c board_init part_config = 255 > > > > > Core: 38 devices, 22 uclasses, devicetree: separate > > > > > MMC: mv_sdh: 0 > > > > > Loading Environment from MMC... *** Warning - bad CRC, using default > > > > > environment > > > > > > > > > > Model: SolidRun Clearfog A1 > > > > > clearfog.c checkboard part_config = 16 > > > > > Board: SolidRun Clearfog Pro > > > > > Net: > > > > >
Re: [PATCH RFC u-boot-mvebu 0/2] arm: mvebu: Fix eMMC boot
On Mon, 20 Mar 2023 at 17:33, Pali Rohár wrote: > On Monday 20 March 2023 11:48:59 Martin Rowe wrote: > > On Sun, 19 Mar 2023 at 16:22, Pali Rohár wrote: > > > > > On Sunday 19 March 2023 00:32:01 Martin Rowe wrote: > > > > On Mon, 6 Mar 2023 at 11:53, Pali Rohár wrote: > > > > > > > > > Could you try to print mmc->part_config (ideally as early as > possible)? > > > > > > > > > > > > > In SPL mmc->part_config is 255 > > > > In main u-boot at the start of clearfog.c board_init() > mmc->part_config > > > is > > > > 255 > > > > In main u-boot at the start of clearfog.c checkboard() > mmc->part_config > > > is > > > > 8 (ack: 0, partition_enable: 1, access: 0) > > > > > > 255 is uninitialized value. > > > > > > > If I set partition_enable to 2, I get the same result except the > value is > > > > 16 (ack: 0, partition_enable: 2, access: 0) instead of 8 for the > last > > > value > > > > > > Try to change "access" bits. > > > > > > > > > > > BootROM - 1.73 > > > > > > > > Booting from MMC > > > > > > > > U-Boot SPL 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - > 10:05:32 > > > > +1000) > > > > High speed PHY - Version: 2.0 > > > > EEPROM TLV detection failed: Using static config for Clearfog Pro. > > > > Detected Device ID 6828 > > > > board SerDes lanes topology details: > > > > | Lane # | Speed | Type | > > > > > > > > | 0| 3 | SATA0 | > > > > | 1| 0 | SGMII1 | > > > > | 2| 5 | PCIe1 | > > > > | 3| 5 | USB3 HOST1 | > > > > | 4| 5 | PCIe2 | > > > > | 5| 0 | SGMII2 | > > > > > > > > High speed PHY - Ended Successfully > > > > mv_ddr: 14.0.0 > > > > DDR3 Training Sequence - Switching XBAR Window to FastPath Window > > > > mv_ddr: completed successfully > > > > spl.c spl_boot_device part_config = 255 > > > > Trying to boot from MMC1 > > > > > > > > > > > > U-Boot 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - 10:05:32 > +1000) > > > > > > > > SoC: MV88F6828-A0 at 1600 MHz > > > > DRAM: 1 GiB (800 MHz, 32-bit, ECC not enabled) > > > > clearfog.c board_init part_config = 255 > > > > Core: 38 devices, 22 uclasses, devicetree: separate > > > > MMC: mv_sdh: 0 > > > > Loading Environment from MMC... *** Warning - bad CRC, using default > > > > environment > > > > > > > > Model: SolidRun Clearfog A1 > > > > clearfog.c checkboard part_config = 8 > > > > Board: SolidRun Clearfog Pro > > > > Net: > > > > Warning: ethernet@7 (eth1) using random MAC address - > > > 32:16:0e:b4:d1:d8 > > > > eth1: ethernet@7 > > > > Warning: ethernet@3 (eth2) using random MAC address - > > > 72:30:3f:79:07:12 > > > > , eth2: ethernet@3 > > > > Warning: ethernet@34000 (eth3) using random MAC address - > > > 82:fb:71:23:46:4f > > > > , eth3: ethernet@34000 > > > > Hit any key to stop autoboot: 0 > > > > => mmc partconf 0 > > > > EXT_CSD[179], PARTITION_CONFIG: > > > > BOOT_ACK: 0x0 > > > > BOOT_PARTITION_ENABLE: 0x1 > > > > PARTITION_ACCESS: 0x0 > > > > > > > > > > > > > > > > BootROM - 1.73 > > > > > > > > Booting from MMC > > > > > > > > U-Boot SPL 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - > 10:05:32 > > > > +1000) > > > > High speed PHY - Version: 2.0 > > > > EEPROM TLV detection failed: Using static config for Clearfog Pro. > > > > Detected Device ID 6828 > > > > board SerDes lanes topology details: > > > > | Lane # | Speed | Type | > > > > > > > > | 0| 3 | SATA0 | > > > > | 1| 0 | SGMII1 | > > > > | 2| 5 | PCIe1 | > > > > | 3| 5 | USB3 HOST1 | > > > > | 4| 5 | PCIe2 | > > > > | 5| 0 | SGMII2 | > > > > > > > > High speed PHY - Ended Successfully > > > > mv_ddr: 14.0.0 > > > > DDR3 Training Sequence - Switching XBAR Window to FastPath Window > > > > mv_ddr: completed successfully > > > > spl.c spl_boot_device part_config = 255 > > > > Trying to boot from MMC1 > > > > > > > > > > > > U-Boot 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - 10:05:32 > +1000) > > > > > > > > SoC: MV88F6828-A0 at 1600 MHz > > > > DRAM: 1 GiB (800 MHz, 32-bit, ECC not enabled) > > > > clearfog.c board_init part_config = 255 > > > > Core: 38 devices, 22 uclasses, devicetree: separate > > > > MMC: mv_sdh: 0 > > > > Loading Environment from MMC... *** Warning - bad CRC, using default > > > > environment > > > > > > > > Model: SolidRun Clearfog A1 > > > > clearfog.c checkboard part_config = 16 > > > > Board: SolidRun Clearfog Pro > > > > Net: > > > > Warning: ethernet@7 (eth1) using random MAC address - > > > 92:5a:fc:14:e8:f6 > > > > eth1: ethernet@7 > > > > Warning: ethernet@3 (eth2) using random MAC address - > > > 42:9c:d8:3a:cb:b2 > > > > , eth2: ethernet@3 > > > > Warning: ethernet@34000 (eth3) using random MAC address - > > > c6:99:20:f4:02:a0 > > > > ,
Re: [PATCH RFC u-boot-mvebu 0/2] arm: mvebu: Fix eMMC boot
On Monday 20 March 2023 11:48:59 Martin Rowe wrote: > On Sun, 19 Mar 2023 at 16:22, Pali Rohár wrote: > > > On Sunday 19 March 2023 00:32:01 Martin Rowe wrote: > > > On Mon, 6 Mar 2023 at 11:53, Pali Rohár wrote: > > > > > > > Could you try to print mmc->part_config (ideally as early as possible)? > > > > > > > > > > In SPL mmc->part_config is 255 > > > In main u-boot at the start of clearfog.c board_init() mmc->part_config > > is > > > 255 > > > In main u-boot at the start of clearfog.c checkboard() mmc->part_config > > is > > > 8 (ack: 0, partition_enable: 1, access: 0) > > > > 255 is uninitialized value. > > > > > If I set partition_enable to 2, I get the same result except the value is > > > 16 (ack: 0, partition_enable: 2, access: 0) instead of 8 for the last > > value > > > > Try to change "access" bits. > > > > > > > > BootROM - 1.73 > > > > > > Booting from MMC > > > > > > U-Boot SPL 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - 10:05:32 > > > +1000) > > > High speed PHY - Version: 2.0 > > > EEPROM TLV detection failed: Using static config for Clearfog Pro. > > > Detected Device ID 6828 > > > board SerDes lanes topology details: > > > | Lane # | Speed | Type | > > > > > > | 0| 3 | SATA0 | > > > | 1| 0 | SGMII1 | > > > | 2| 5 | PCIe1 | > > > | 3| 5 | USB3 HOST1 | > > > | 4| 5 | PCIe2 | > > > | 5| 0 | SGMII2 | > > > > > > High speed PHY - Ended Successfully > > > mv_ddr: 14.0.0 > > > DDR3 Training Sequence - Switching XBAR Window to FastPath Window > > > mv_ddr: completed successfully > > > spl.c spl_boot_device part_config = 255 > > > Trying to boot from MMC1 > > > > > > > > > U-Boot 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - 10:05:32 +1000) > > > > > > SoC: MV88F6828-A0 at 1600 MHz > > > DRAM: 1 GiB (800 MHz, 32-bit, ECC not enabled) > > > clearfog.c board_init part_config = 255 > > > Core: 38 devices, 22 uclasses, devicetree: separate > > > MMC: mv_sdh: 0 > > > Loading Environment from MMC... *** Warning - bad CRC, using default > > > environment > > > > > > Model: SolidRun Clearfog A1 > > > clearfog.c checkboard part_config = 8 > > > Board: SolidRun Clearfog Pro > > > Net: > > > Warning: ethernet@7 (eth1) using random MAC address - > > 32:16:0e:b4:d1:d8 > > > eth1: ethernet@7 > > > Warning: ethernet@3 (eth2) using random MAC address - > > 72:30:3f:79:07:12 > > > , eth2: ethernet@3 > > > Warning: ethernet@34000 (eth3) using random MAC address - > > 82:fb:71:23:46:4f > > > , eth3: ethernet@34000 > > > Hit any key to stop autoboot: 0 > > > => mmc partconf 0 > > > EXT_CSD[179], PARTITION_CONFIG: > > > BOOT_ACK: 0x0 > > > BOOT_PARTITION_ENABLE: 0x1 > > > PARTITION_ACCESS: 0x0 > > > > > > > > > > > > BootROM - 1.73 > > > > > > Booting from MMC > > > > > > U-Boot SPL 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - 10:05:32 > > > +1000) > > > High speed PHY - Version: 2.0 > > > EEPROM TLV detection failed: Using static config for Clearfog Pro. > > > Detected Device ID 6828 > > > board SerDes lanes topology details: > > > | Lane # | Speed | Type | > > > > > > | 0| 3 | SATA0 | > > > | 1| 0 | SGMII1 | > > > | 2| 5 | PCIe1 | > > > | 3| 5 | USB3 HOST1 | > > > | 4| 5 | PCIe2 | > > > | 5| 0 | SGMII2 | > > > > > > High speed PHY - Ended Successfully > > > mv_ddr: 14.0.0 > > > DDR3 Training Sequence - Switching XBAR Window to FastPath Window > > > mv_ddr: completed successfully > > > spl.c spl_boot_device part_config = 255 > > > Trying to boot from MMC1 > > > > > > > > > U-Boot 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - 10:05:32 +1000) > > > > > > SoC: MV88F6828-A0 at 1600 MHz > > > DRAM: 1 GiB (800 MHz, 32-bit, ECC not enabled) > > > clearfog.c board_init part_config = 255 > > > Core: 38 devices, 22 uclasses, devicetree: separate > > > MMC: mv_sdh: 0 > > > Loading Environment from MMC... *** Warning - bad CRC, using default > > > environment > > > > > > Model: SolidRun Clearfog A1 > > > clearfog.c checkboard part_config = 16 > > > Board: SolidRun Clearfog Pro > > > Net: > > > Warning: ethernet@7 (eth1) using random MAC address - > > 92:5a:fc:14:e8:f6 > > > eth1: ethernet@7 > > > Warning: ethernet@3 (eth2) using random MAC address - > > 42:9c:d8:3a:cb:b2 > > > , eth2: ethernet@3 > > > Warning: ethernet@34000 (eth3) using random MAC address - > > c6:99:20:f4:02:a0 > > > , eth3: ethernet@34000 > > > Hit any key to stop autoboot: 0 > > > => mmc partconf 0 > > > EXT_CSD[179], PARTITION_CONFIG: > > > BOOT_ACK: 0x0 > > > BOOT_PARTITION_ENABLE: 0x2 > > > PARTITION_ACCESS: 0x0 > > > > > > > Are both logs from the configuration when SPL+u-boot is stored on Boot0? > > Could you try to erase Boot0 and store
Re: [PATCH RFC u-boot-mvebu 0/2] arm: mvebu: Fix eMMC boot
On Sun, 19 Mar 2023 at 16:22, Pali Rohár wrote: > On Sunday 19 March 2023 00:32:01 Martin Rowe wrote: > > On Mon, 6 Mar 2023 at 11:53, Pali Rohár wrote: > > > > > Could you try to print mmc->part_config (ideally as early as possible)? > > > > > > > In SPL mmc->part_config is 255 > > In main u-boot at the start of clearfog.c board_init() mmc->part_config > is > > 255 > > In main u-boot at the start of clearfog.c checkboard() mmc->part_config > is > > 8 (ack: 0, partition_enable: 1, access: 0) > > 255 is uninitialized value. > > > If I set partition_enable to 2, I get the same result except the value is > > 16 (ack: 0, partition_enable: 2, access: 0) instead of 8 for the last > value > > Try to change "access" bits. > > > > > BootROM - 1.73 > > > > Booting from MMC > > > > U-Boot SPL 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - 10:05:32 > > +1000) > > High speed PHY - Version: 2.0 > > EEPROM TLV detection failed: Using static config for Clearfog Pro. > > Detected Device ID 6828 > > board SerDes lanes topology details: > > | Lane # | Speed | Type | > > > > | 0| 3 | SATA0 | > > | 1| 0 | SGMII1 | > > | 2| 5 | PCIe1 | > > | 3| 5 | USB3 HOST1 | > > | 4| 5 | PCIe2 | > > | 5| 0 | SGMII2 | > > > > High speed PHY - Ended Successfully > > mv_ddr: 14.0.0 > > DDR3 Training Sequence - Switching XBAR Window to FastPath Window > > mv_ddr: completed successfully > > spl.c spl_boot_device part_config = 255 > > Trying to boot from MMC1 > > > > > > U-Boot 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - 10:05:32 +1000) > > > > SoC: MV88F6828-A0 at 1600 MHz > > DRAM: 1 GiB (800 MHz, 32-bit, ECC not enabled) > > clearfog.c board_init part_config = 255 > > Core: 38 devices, 22 uclasses, devicetree: separate > > MMC: mv_sdh: 0 > > Loading Environment from MMC... *** Warning - bad CRC, using default > > environment > > > > Model: SolidRun Clearfog A1 > > clearfog.c checkboard part_config = 8 > > Board: SolidRun Clearfog Pro > > Net: > > Warning: ethernet@7 (eth1) using random MAC address - > 32:16:0e:b4:d1:d8 > > eth1: ethernet@7 > > Warning: ethernet@3 (eth2) using random MAC address - > 72:30:3f:79:07:12 > > , eth2: ethernet@3 > > Warning: ethernet@34000 (eth3) using random MAC address - > 82:fb:71:23:46:4f > > , eth3: ethernet@34000 > > Hit any key to stop autoboot: 0 > > => mmc partconf 0 > > EXT_CSD[179], PARTITION_CONFIG: > > BOOT_ACK: 0x0 > > BOOT_PARTITION_ENABLE: 0x1 > > PARTITION_ACCESS: 0x0 > > > > > > > > BootROM - 1.73 > > > > Booting from MMC > > > > U-Boot SPL 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - 10:05:32 > > +1000) > > High speed PHY - Version: 2.0 > > EEPROM TLV detection failed: Using static config for Clearfog Pro. > > Detected Device ID 6828 > > board SerDes lanes topology details: > > | Lane # | Speed | Type | > > > > | 0| 3 | SATA0 | > > | 1| 0 | SGMII1 | > > | 2| 5 | PCIe1 | > > | 3| 5 | USB3 HOST1 | > > | 4| 5 | PCIe2 | > > | 5| 0 | SGMII2 | > > > > High speed PHY - Ended Successfully > > mv_ddr: 14.0.0 > > DDR3 Training Sequence - Switching XBAR Window to FastPath Window > > mv_ddr: completed successfully > > spl.c spl_boot_device part_config = 255 > > Trying to boot from MMC1 > > > > > > U-Boot 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - 10:05:32 +1000) > > > > SoC: MV88F6828-A0 at 1600 MHz > > DRAM: 1 GiB (800 MHz, 32-bit, ECC not enabled) > > clearfog.c board_init part_config = 255 > > Core: 38 devices, 22 uclasses, devicetree: separate > > MMC: mv_sdh: 0 > > Loading Environment from MMC... *** Warning - bad CRC, using default > > environment > > > > Model: SolidRun Clearfog A1 > > clearfog.c checkboard part_config = 16 > > Board: SolidRun Clearfog Pro > > Net: > > Warning: ethernet@7 (eth1) using random MAC address - > 92:5a:fc:14:e8:f6 > > eth1: ethernet@7 > > Warning: ethernet@3 (eth2) using random MAC address - > 42:9c:d8:3a:cb:b2 > > , eth2: ethernet@3 > > Warning: ethernet@34000 (eth3) using random MAC address - > c6:99:20:f4:02:a0 > > , eth3: ethernet@34000 > > Hit any key to stop autoboot: 0 > > => mmc partconf 0 > > EXT_CSD[179], PARTITION_CONFIG: > > BOOT_ACK: 0x0 > > BOOT_PARTITION_ENABLE: 0x2 > > PARTITION_ACCESS: 0x0 > > > > Are both logs from the configuration when SPL+u-boot is stored on Boot0? > Could you try to erase Boot0 and store SPL+u-boot to Boot1? I'm > interested to see if "access" bits are changed in SPL (before loading > main u-boot). > > > I'm having trouble trying to find the hooks which run between board_init > > and checkboard. If you can point me in the right direction I'm happy to > > re-run and try to narrow down where the valid values are being set
Re: [PATCH RFC u-boot-mvebu 0/2] arm: mvebu: Fix eMMC boot
On Sunday 19 March 2023 02:30:07 Martin Rowe wrote: > On Mon, 6 Mar 2023 at 18:40, Pali Rohár wrote: > > > On Monday 06 March 2023 11:15:35 Martin Rowe wrote: > > > On Sun, 5 Mar 2023 at 16:04, Pali Rohár wrote: > > > > Could you try another test by completely erasing BOOT0, BOOT1 and USER > > > > > data? And see what BootROM prints. > > > > > > > > > > = > > > BootROM - 1.73 > > > > > > Booting from MMC > > > BootROM: Bad header at offset > > > BootROM: Bad header at offset 0020 > > > Switching BootPartitions. > > > BootROM: Bad header at offset > > > BootROM: Bad header at offset 0020 > > > Switching BootPartitions. > > > BootROM: Bad header at offset > > > BootROM: Bad header at offset 0020 > > > Switching BootPartitions. > > > BootROM: Bad header at offset > > > BootROM: Bad header at offset 0020 > > > Switching BootPartitions. > > > BootROM: Bad header at offset > > > BootROM: Bad header at offset 0020 > > > Switching BootPartitions. > > > BootROM: Bad header at offset > > > BootROM: Bad header at offset 0020 > > > Switching BootPartitions. > > > BootROM: Bad header at offset > > > BootROM: Bad header at offset 0020 > > > Switching BootPartitions. > > > BootROM: Bad header at offset > > > BootROM: Bad header at offset 0020 > > > Switching BootPartitions. > > > BootROM: Bad header at offset > > > BootROM: Bad header at offset 0020 > > > Switching BootPartitions. > > > BootROM: Bad header at offset > > > BootROM: Bad h > > > Trying Uart > > > = > > > > Originally I though that I did not understand disassembled bootrom code > > correctly but this logs proves that I did it correctly. Log is very > > strange. > > > > There is a loop which tries partition numbers 0x1, 0x2, ... 0x9, 0xa. > > > > And if I'm looking at the bootrom code correctly it does bit-AND > > operation on partition number with constant 0x7 and result is set into > > mmc register 179 (partition_config). > > > > So if I understand it correctly it means that bootrom automatically > > clears boot_ack and boot_partition. And into partition_access it sets > > the partition number. Hence numbers 0x9 and 0xa are trimmed and > > aliased to 0x1 and 0x2; and number 0x8 overflows to 0x0. > > > > Completely strange behavior and probably against how HW mmc boot > > partitions should be used. > > > > eMMC spec defines: > > partition_access (low 3 bits of mmc 179/partition_config register): > > 0x0 : No access to boot partition (default) > > 0x1 : R/W boot partition 1 > > 0x2 : R/W boot partition 2 > > 0x3 : R/W Replay Protected Memory Block (RPMB) > > 0x4 : Access to General Purpose partition 1 > > 0x5 : Access to General Purpose partition 2 > > 0x6 : Access to General Purpose partition 3 > > 0x7 : Access to General Purpose partition 4 > > > > I can only set 0, 1, 2, and 7; the others result in `exit not allowed from > main input shell.` Bingo, you found a new bug in u-boot mmc code. I hope that this patch fixes it: https://patchwork.ozlabs.org/project/uboot/patch/20230319163342.15385-1-p...@kernel.org/ > > I guess that you do not have general purpose partitions layout on emmc > > and RPMB is not used too. So technically only 0x0, 0x1, and 0x2 are > > available. > > > > To confirm my theory, could you try to do following tests? > > > > 1. Check u-boot's "mmc partconf" settings are not preserved across > > reboots. > > > > The only part that seems to be preserved is the partition_enable; ack and > access both reset to 0. Ok, it is possible that U-Boot itself overwrite access bits and hence via "mmc partconf" command it is not possible to "print it". Could you try to check current settings in SPL via mmc.c hook which I described in previous email? > > 2. Put valid image into userdata partition; erase boot 0 and boot 1; and > > post bootrom output. There should be 7 invalid attempts with Switching > > BootPartitions message. > > > > 7 invalid attempts before it finds u-boot in the userdata partition: > > > BootROM - 1.73 > > Booting from MMC > BootROM: Bad header at offset > BootROM: Bad header at offset 0020 > Switching BootPartitions. > BootROM: Bad header at offset > BootROM: Bad header at offset 0020 > Switching BootPartitions. > BootROM: Bad header at offset > BootROM: Bad header at offset 0020 > Switching BootPartitions. > BootROM: Bad header at offset > BootROM: Bad header at offset 0020 > Switching BootPartitions. > BootROM: Bad header at offset > BootROM: Bad header at offset 0020 > Switching BootPartitions. > BootROM: Bad header at offset > BootROM: Bad header at offset 0020 > Switching BootPartitions. > BootROM: Bad header at offset > BootROM: Bad header at offset 0020 > Switching BootPartitions. > > U-Boot SPL
Re: [PATCH RFC u-boot-mvebu 0/2] arm: mvebu: Fix eMMC boot
On Sunday 19 March 2023 00:32:01 Martin Rowe wrote: > On Mon, 6 Mar 2023 at 11:53, Pali Rohár wrote: > > > Could you try to print mmc->part_config (ideally as early as possible)? > > > > In SPL mmc->part_config is 255 > In main u-boot at the start of clearfog.c board_init() mmc->part_config is > 255 > In main u-boot at the start of clearfog.c checkboard() mmc->part_config is > 8 (ack: 0, partition_enable: 1, access: 0) 255 is uninitialized value. > If I set partition_enable to 2, I get the same result except the value is > 16 (ack: 0, partition_enable: 2, access: 0) instead of 8 for the last value Try to change "access" bits. > > BootROM - 1.73 > > Booting from MMC > > U-Boot SPL 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - 10:05:32 > +1000) > High speed PHY - Version: 2.0 > EEPROM TLV detection failed: Using static config for Clearfog Pro. > Detected Device ID 6828 > board SerDes lanes topology details: > | Lane # | Speed | Type | > > | 0| 3 | SATA0 | > | 1| 0 | SGMII1 | > | 2| 5 | PCIe1 | > | 3| 5 | USB3 HOST1 | > | 4| 5 | PCIe2 | > | 5| 0 | SGMII2 | > > High speed PHY - Ended Successfully > mv_ddr: 14.0.0 > DDR3 Training Sequence - Switching XBAR Window to FastPath Window > mv_ddr: completed successfully > spl.c spl_boot_device part_config = 255 > Trying to boot from MMC1 > > > U-Boot 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - 10:05:32 +1000) > > SoC: MV88F6828-A0 at 1600 MHz > DRAM: 1 GiB (800 MHz, 32-bit, ECC not enabled) > clearfog.c board_init part_config = 255 > Core: 38 devices, 22 uclasses, devicetree: separate > MMC: mv_sdh: 0 > Loading Environment from MMC... *** Warning - bad CRC, using default > environment > > Model: SolidRun Clearfog A1 > clearfog.c checkboard part_config = 8 > Board: SolidRun Clearfog Pro > Net: > Warning: ethernet@7 (eth1) using random MAC address - 32:16:0e:b4:d1:d8 > eth1: ethernet@7 > Warning: ethernet@3 (eth2) using random MAC address - 72:30:3f:79:07:12 > , eth2: ethernet@3 > Warning: ethernet@34000 (eth3) using random MAC address - 82:fb:71:23:46:4f > , eth3: ethernet@34000 > Hit any key to stop autoboot: 0 > => mmc partconf 0 > EXT_CSD[179], PARTITION_CONFIG: > BOOT_ACK: 0x0 > BOOT_PARTITION_ENABLE: 0x1 > PARTITION_ACCESS: 0x0 > > > > BootROM - 1.73 > > Booting from MMC > > U-Boot SPL 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - 10:05:32 > +1000) > High speed PHY - Version: 2.0 > EEPROM TLV detection failed: Using static config for Clearfog Pro. > Detected Device ID 6828 > board SerDes lanes topology details: > | Lane # | Speed | Type | > > | 0| 3 | SATA0 | > | 1| 0 | SGMII1 | > | 2| 5 | PCIe1 | > | 3| 5 | USB3 HOST1 | > | 4| 5 | PCIe2 | > | 5| 0 | SGMII2 | > > High speed PHY - Ended Successfully > mv_ddr: 14.0.0 > DDR3 Training Sequence - Switching XBAR Window to FastPath Window > mv_ddr: completed successfully > spl.c spl_boot_device part_config = 255 > Trying to boot from MMC1 > > > U-Boot 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - 10:05:32 +1000) > > SoC: MV88F6828-A0 at 1600 MHz > DRAM: 1 GiB (800 MHz, 32-bit, ECC not enabled) > clearfog.c board_init part_config = 255 > Core: 38 devices, 22 uclasses, devicetree: separate > MMC: mv_sdh: 0 > Loading Environment from MMC... *** Warning - bad CRC, using default > environment > > Model: SolidRun Clearfog A1 > clearfog.c checkboard part_config = 16 > Board: SolidRun Clearfog Pro > Net: > Warning: ethernet@7 (eth1) using random MAC address - 92:5a:fc:14:e8:f6 > eth1: ethernet@7 > Warning: ethernet@3 (eth2) using random MAC address - 42:9c:d8:3a:cb:b2 > , eth2: ethernet@3 > Warning: ethernet@34000 (eth3) using random MAC address - c6:99:20:f4:02:a0 > , eth3: ethernet@34000 > Hit any key to stop autoboot: 0 > => mmc partconf 0 > EXT_CSD[179], PARTITION_CONFIG: > BOOT_ACK: 0x0 > BOOT_PARTITION_ENABLE: 0x2 > PARTITION_ACCESS: 0x0 > Are both logs from the configuration when SPL+u-boot is stored on Boot0? Could you try to erase Boot0 and store SPL+u-boot to Boot1? I'm interested to see if "access" bits are changed in SPL (before loading main u-boot). > I'm having trouble trying to find the hooks which run between board_init > and checkboard. If you can point me in the right direction I'm happy to > re-run and try to narrow down where the valid values are being set from. Print it directly in drivers/mmc/mmc.c mmc_startup_v4() where mmc->part_config = is set from ext_csd[EXT_CSD_PART_CONF] register. I want to see original value from EXT_CSD_PART_CONF. I do not know which hook is the best, so printing it from mmc.c driver should work better.
Re: [PATCH RFC u-boot-mvebu 0/2] arm: mvebu: Fix eMMC boot
On Mon, 6 Mar 2023 at 18:40, Pali Rohár wrote: > On Monday 06 March 2023 11:15:35 Martin Rowe wrote: > > On Sun, 5 Mar 2023 at 16:04, Pali Rohár wrote: > > > Could you try another test by completely erasing BOOT0, BOOT1 and USER > > > > data? And see what BootROM prints. > > > > > > > = > > BootROM - 1.73 > > > > Booting from MMC > > BootROM: Bad header at offset > > BootROM: Bad header at offset 0020 > > Switching BootPartitions. > > BootROM: Bad header at offset > > BootROM: Bad header at offset 0020 > > Switching BootPartitions. > > BootROM: Bad header at offset > > BootROM: Bad header at offset 0020 > > Switching BootPartitions. > > BootROM: Bad header at offset > > BootROM: Bad header at offset 0020 > > Switching BootPartitions. > > BootROM: Bad header at offset > > BootROM: Bad header at offset 0020 > > Switching BootPartitions. > > BootROM: Bad header at offset > > BootROM: Bad header at offset 0020 > > Switching BootPartitions. > > BootROM: Bad header at offset > > BootROM: Bad header at offset 0020 > > Switching BootPartitions. > > BootROM: Bad header at offset > > BootROM: Bad header at offset 0020 > > Switching BootPartitions. > > BootROM: Bad header at offset > > BootROM: Bad header at offset 0020 > > Switching BootPartitions. > > BootROM: Bad header at offset > > BootROM: Bad h > > Trying Uart > > = > > Originally I though that I did not understand disassembled bootrom code > correctly but this logs proves that I did it correctly. Log is very > strange. > > There is a loop which tries partition numbers 0x1, 0x2, ... 0x9, 0xa. > > And if I'm looking at the bootrom code correctly it does bit-AND > operation on partition number with constant 0x7 and result is set into > mmc register 179 (partition_config). > > So if I understand it correctly it means that bootrom automatically > clears boot_ack and boot_partition. And into partition_access it sets > the partition number. Hence numbers 0x9 and 0xa are trimmed and > aliased to 0x1 and 0x2; and number 0x8 overflows to 0x0. > > Completely strange behavior and probably against how HW mmc boot > partitions should be used. > > eMMC spec defines: > partition_access (low 3 bits of mmc 179/partition_config register): > 0x0 : No access to boot partition (default) > 0x1 : R/W boot partition 1 > 0x2 : R/W boot partition 2 > 0x3 : R/W Replay Protected Memory Block (RPMB) > 0x4 : Access to General Purpose partition 1 > 0x5 : Access to General Purpose partition 2 > 0x6 : Access to General Purpose partition 3 > 0x7 : Access to General Purpose partition 4 > I can only set 0, 1, 2, and 7; the others result in `exit not allowed from main input shell.` > I guess that you do not have general purpose partitions layout on emmc > and RPMB is not used too. So technically only 0x0, 0x1, and 0x2 are > available. > > To confirm my theory, could you try to do following tests? > > 1. Check u-boot's "mmc partconf" settings are not preserved across > reboots. > The only part that seems to be preserved is the partition_enable; ack and access both reset to 0. > 2. Put valid image into userdata partition; erase boot 0 and boot 1; and > post bootrom output. There should be 7 invalid attempts with Switching > BootPartitions message. > 7 invalid attempts before it finds u-boot in the userdata partition: BootROM - 1.73 Booting from MMC BootROM: Bad header at offset BootROM: Bad header at offset 0020 Switching BootPartitions. BootROM: Bad header at offset BootROM: Bad header at offset 0020 Switching BootPartitions. BootROM: Bad header at offset BootROM: Bad header at offset 0020 Switching BootPartitions. BootROM: Bad header at offset BootROM: Bad header at offset 0020 Switching BootPartitions. BootROM: Bad header at offset BootROM: Bad header at offset 0020 Switching BootPartitions. BootROM: Bad header at offset BootROM: Bad header at offset 0020 Switching BootPartitions. BootROM: Bad header at offset BootROM: Bad header at offset 0020 Switching BootPartitions. U-Boot SPL 2023.04-rc3-00159-gd1653548d2-dirty (Mar 19 2023 - 10:05:32 +1000) > 3. Take valid image, invalidate kwb header checksum and put it on boot0; > plus erase boot1 and user. Bootrom should print "Invalid header > checksum" message and it should be two times. Once for 0x1 and second > time for overflowed 0x9. > Changing just the checksum at 0x1F results in BootROM producing no output and just hanging. I've tried on each boot partition (with the others zeroed) and can't get any results at all. I also tried a valid header and zeroes for the rest of the image; same result.
Re: [PATCH RFC u-boot-mvebu 0/2] arm: mvebu: Fix eMMC boot
On Mon, 6 Mar 2023 at 11:53, Pali Rohár wrote: > On Monday 06 March 2023 11:15:35 Martin Rowe wrote: > > On Sun, 5 Mar 2023 at 16:04, Pali Rohár wrote: > > > > > On Sunday 05 March 2023 12:46:34 Pali Rohár wrote: > > > > On Sunday 05 March 2023 02:24:27 Martin Rowe wrote: > > > > > On Sat, 4 Mar 2023 at 10:40, Pali Rohár wrote: > > > > > > > > > > > Boot configuration stored in EXT_CSC register is completely > ignored > > > by > > > > > > BootROM: > > > > > > > > > > > > > > > > https://lore.kernel.org/u-boot/CAOAjy5SYPPzWKok-BSGYwZwcKOQt_aZPgh6FTbrFd3F=8dm...@mail.gmail.com/ > > > > > > > > > > > > Reflect this eMMC booting in documentation and in the code. > > > > > > > > > > > > Martin, can you test this patch series if SPL and main U-Boot is > > > loaded > > > > > > from the same eMMC HW partition? > > > > > > > > > > > > > > > > boot0: u-boot > > > > > > > > > > Works fine, no issues. > > > > > > > > > > > > > > > boot0: zeroed > > > > > boot1: u-boot > > > > > user: zeroed > > > > > > > > > > It succeeds, eventually... > > > > > == > > > > > BootROM - 1.73 > > > > > > > > > > Booting from MMC > > > > > BootROM: Bad header at offset > > > > > BootROM: Bad header at offset 0020 > > > > > Switching BootPartitions. > > > > > > > > > > U-Boot SPL 2023.04-rc3-00159-gd1653548d2-dirty (Mar 05 2023 - > 11:50:45 > > > > > +1000) > > > > > High speed PHY - Version: 2.0 > > > > > EEPROM TLV detection failed: Using static config for Clearfog Pro. > > > > > Detected Device ID 6828 > > > > > board SerDes lanes topology details: > > > > > | Lane # | Speed | Type | > > > > > > > > > > | 0| 3 | SATA0 | > > > > > | 1| 0 | SGMII1 | > > > > > | 2| 5 | PCIe1 | > > > > > | 3| 5 | USB3 HOST1 | > > > > > | 4| 5 | PCIe2 | > > > > > | 5| 0 | SGMII2 | > > > > > > > > > > High speed PHY - Ended Successfully > > > > > mv_ddr: 14.0.0 > > > > > DDR3 Training Sequence - Switching XBAR Window to FastPath Window > > > > > mv_ddr: completed successfully > > > > > Trying to boot from MMC1 > > > > > ERROR: Invalid kwbimage v1 > > > > > mmc_load_image_raw_sector: mmc block read error > > > > > spl: mmc: wrong boot mode > > > > > Trying to boot from BOOTROM > > > > > Returning to BootROM (return address 0x05c4)... > > > > > Timeout waiting card ready > > > > > BootROM: Image checksum verification PASSED > > > > > > > > > > > > > > > U-Boot 2023.04-rc3-00159-gd1653548d2-dirty (Mar 05 2023 - 11:50:45 > > > +1000) > > > > > > > > > > SoC: MV88F6828-A0 at 1600 MHz > > > > > DRAM: 1 GiB (800 MHz, 32-bit, ECC not enabled) > > > > > Core: 38 devices, 22 uclasses, devicetree: separate > > > > > MMC: mv_sdh: 0 > > > > > Loading Environment from MMC... *** Warning - bad CRC, using > default > > > > > environment > > > > > > > > > > Model: SolidRun Clearfog A1 > > > > > Board: SolidRun Clearfog Pro > > > > > Net: > > > > > Warning: ethernet@7 (eth1) using random MAC address - > > > 12:07:8b:f9:7a:6f > > > > > eth1: ethernet@7 > > > > > Warning: ethernet@3 (eth2) using random MAC address - > > > ee:ed:f3:bb:c2:af > > > > > , eth2: ethernet@3 > > > > > Warning: ethernet@34000 (eth3) using random MAC address - > > > ae:34:b9:bb:28:c6 > > > > > , eth3: ethernet@34000 > > > > > Hit any key to stop autoboot: 0 > > > > > => > > > > > == > > > > > > > > > > Between "Returning to BootROM" and "Timeout waiting card ready" > takes > > > > > around 315 seconds. That's long enough that I thought it had hung > > > > > completely and I only noticed it continue because I left it running > > > while > > > > > working on something else. I tried several things to reduce this > > > timeout, > > > > > including reverting to the "non-removable" dts for shdci, but > nothing > > > seems > > > > > to affect it. > > > > > > > > Ok. So now it is in the state that it is working but is slow. Better > > > > than nothing. > > > > > > > > Message "Returning to BootROM" is printed by SPL and message > > > > "Timeout waiting card ready" is printed by BootROM. After printing > > > > "Returning to BootROM" is SPL jumping back to the BootROM so the > delay > > > > is for sure in the BootROM. So seems that SPL reconfigures eMMC into > > > > state in which BootROM cannot work with it. Something timeouts, > BootROM > > > > reconfigure/retry it and then it work again. It would be needed to > > > > investigate what is happening here. My guess is that this could have > > > > something with eMMC HW partition access, and code for switching > > > > partitions near SPL MMCSD_MODE_EMMCBOOT. > > > > > > Try this change? > > > > > > diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c > > > index b20eac3dcd38..eb59c41a824e 100644 > > > --- a/arch/arm/mach-mvebu/spl.c > > > +++ b/arch/arm/mach-mvebu/spl.c > > > @@ -11,6
Re: [PATCH RFC u-boot-mvebu 0/2] arm: mvebu: Fix eMMC boot
On Monday 06 March 2023 12:53:25 Pali Rohár wrote: > On Monday 06 March 2023 11:15:35 Martin Rowe wrote: > > On Sun, 5 Mar 2023 at 16:04, Pali Rohár wrote: > > > > > On Sunday 05 March 2023 12:46:34 Pali Rohár wrote: > > > > On Sunday 05 March 2023 02:24:27 Martin Rowe wrote: > > > > > On Sat, 4 Mar 2023 at 10:40, Pali Rohár wrote: > > > > > > > > > > > Boot configuration stored in EXT_CSC register is completely ignored > > > by > > > > > > BootROM: > > > > > > > > > > > > > > > https://lore.kernel.org/u-boot/CAOAjy5SYPPzWKok-BSGYwZwcKOQt_aZPgh6FTbrFd3F=8dm...@mail.gmail.com/ > > > > > > > > > > > > Reflect this eMMC booting in documentation and in the code. > > > > > > > > > > > > Martin, can you test this patch series if SPL and main U-Boot is > > > loaded > > > > > > from the same eMMC HW partition? > > > > > > > > > > > > > > > > boot0: u-boot > > > > > > > > > > Works fine, no issues. > > > > > > > > > > > > > > > boot0: zeroed > > > > > boot1: u-boot > > > > > user: zeroed > > > > > > > > > > It succeeds, eventually... > > > > > == > > > > > BootROM - 1.73 > > > > > > > > > > Booting from MMC > > > > > BootROM: Bad header at offset > > > > > BootROM: Bad header at offset 0020 > > > > > Switching BootPartitions. > > > > > > > > > > U-Boot SPL 2023.04-rc3-00159-gd1653548d2-dirty (Mar 05 2023 - 11:50:45 > > > > > +1000) > > > > > High speed PHY - Version: 2.0 > > > > > EEPROM TLV detection failed: Using static config for Clearfog Pro. > > > > > Detected Device ID 6828 > > > > > board SerDes lanes topology details: > > > > > | Lane # | Speed | Type | > > > > > > > > > > | 0| 3 | SATA0 | > > > > > | 1| 0 | SGMII1 | > > > > > | 2| 5 | PCIe1 | > > > > > | 3| 5 | USB3 HOST1 | > > > > > | 4| 5 | PCIe2 | > > > > > | 5| 0 | SGMII2 | > > > > > > > > > > High speed PHY - Ended Successfully > > > > > mv_ddr: 14.0.0 > > > > > DDR3 Training Sequence - Switching XBAR Window to FastPath Window > > > > > mv_ddr: completed successfully > > > > > Trying to boot from MMC1 > > > > > ERROR: Invalid kwbimage v1 > > > > > mmc_load_image_raw_sector: mmc block read error > > > > > spl: mmc: wrong boot mode > > > > > Trying to boot from BOOTROM > > > > > Returning to BootROM (return address 0x05c4)... > > > > > Timeout waiting card ready > > > > > BootROM: Image checksum verification PASSED > > > > > > > > > > > > > > > U-Boot 2023.04-rc3-00159-gd1653548d2-dirty (Mar 05 2023 - 11:50:45 > > > +1000) > > > > > > > > > > SoC: MV88F6828-A0 at 1600 MHz > > > > > DRAM: 1 GiB (800 MHz, 32-bit, ECC not enabled) > > > > > Core: 38 devices, 22 uclasses, devicetree: separate > > > > > MMC: mv_sdh: 0 > > > > > Loading Environment from MMC... *** Warning - bad CRC, using default > > > > > environment > > > > > > > > > > Model: SolidRun Clearfog A1 > > > > > Board: SolidRun Clearfog Pro > > > > > Net: > > > > > Warning: ethernet@7 (eth1) using random MAC address - > > > 12:07:8b:f9:7a:6f > > > > > eth1: ethernet@7 > > > > > Warning: ethernet@3 (eth2) using random MAC address - > > > ee:ed:f3:bb:c2:af > > > > > , eth2: ethernet@3 > > > > > Warning: ethernet@34000 (eth3) using random MAC address - > > > ae:34:b9:bb:28:c6 > > > > > , eth3: ethernet@34000 > > > > > Hit any key to stop autoboot: 0 > > > > > => > > > > > == > > > > > > > > > > Between "Returning to BootROM" and "Timeout waiting card ready" takes > > > > > around 315 seconds. That's long enough that I thought it had hung > > > > > completely and I only noticed it continue because I left it running > > > while > > > > > working on something else. I tried several things to reduce this > > > timeout, > > > > > including reverting to the "non-removable" dts for shdci, but nothing > > > seems > > > > > to affect it. > > > > > > > > Ok. So now it is in the state that it is working but is slow. Better > > > > than nothing. > > > > > > > > Message "Returning to BootROM" is printed by SPL and message > > > > "Timeout waiting card ready" is printed by BootROM. After printing > > > > "Returning to BootROM" is SPL jumping back to the BootROM so the delay > > > > is for sure in the BootROM. So seems that SPL reconfigures eMMC into > > > > state in which BootROM cannot work with it. Something timeouts, BootROM > > > > reconfigure/retry it and then it work again. It would be needed to > > > > investigate what is happening here. My guess is that this could have > > > > something with eMMC HW partition access, and code for switching > > > > partitions near SPL MMCSD_MODE_EMMCBOOT. > > > > > > Try this change? > > > > > > diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c > > > index b20eac3dcd38..eb59c41a824e 100644 > > > --- a/arch/arm/mach-mvebu/spl.c > > > +++ b/arch/arm/mach-mvebu/spl.c > > > @@ -11,6 +11,7 @@ > >
Re: [PATCH RFC u-boot-mvebu 0/2] arm: mvebu: Fix eMMC boot
On Monday 06 March 2023 11:15:35 Martin Rowe wrote: > On Sun, 5 Mar 2023 at 16:04, Pali Rohár wrote: > > Could you try another test by completely erasing BOOT0, BOOT1 and USER > > > data? And see what BootROM prints. > > > > = > BootROM - 1.73 > > Booting from MMC > BootROM: Bad header at offset > BootROM: Bad header at offset 0020 > Switching BootPartitions. > BootROM: Bad header at offset > BootROM: Bad header at offset 0020 > Switching BootPartitions. > BootROM: Bad header at offset > BootROM: Bad header at offset 0020 > Switching BootPartitions. > BootROM: Bad header at offset > BootROM: Bad header at offset 0020 > Switching BootPartitions. > BootROM: Bad header at offset > BootROM: Bad header at offset 0020 > Switching BootPartitions. > BootROM: Bad header at offset > BootROM: Bad header at offset 0020 > Switching BootPartitions. > BootROM: Bad header at offset > BootROM: Bad header at offset 0020 > Switching BootPartitions. > BootROM: Bad header at offset > BootROM: Bad header at offset 0020 > Switching BootPartitions. > BootROM: Bad header at offset > BootROM: Bad header at offset 0020 > Switching BootPartitions. > BootROM: Bad header at offset > BootROM: Bad h > Trying Uart > = Originally I though that I did not understand disassembled bootrom code correctly but this logs proves that I did it correctly. Log is very strange. There is a loop which tries partition numbers 0x1, 0x2, ... 0x9, 0xa. And if I'm looking at the bootrom code correctly it does bit-AND operation on partition number with constant 0x7 and result is set into mmc register 179 (partition_config). So if I understand it correctly it means that bootrom automatically clears boot_ack and boot_partition. And into partition_access it sets the partition number. Hence numbers 0x9 and 0xa are trimmed and aliased to 0x1 and 0x2; and number 0x8 overflows to 0x0. Completely strange behavior and probably against how HW mmc boot partitions should be used. eMMC spec defines: partition_access (low 3 bits of mmc 179/partition_config register): 0x0 : No access to boot partition (default) 0x1 : R/W boot partition 1 0x2 : R/W boot partition 2 0x3 : R/W Replay Protected Memory Block (RPMB) 0x4 : Access to General Purpose partition 1 0x5 : Access to General Purpose partition 2 0x6 : Access to General Purpose partition 3 0x7 : Access to General Purpose partition 4 I guess that you do not have general purpose partitions layout on emmc and RPMB is not used too. So technically only 0x0, 0x1, and 0x2 are available. To confirm my theory, could you try to do following tests? 1. Check u-boot's "mmc partconf" settings are not preserved across reboots. 2. Put valid image into userdata partition; erase boot 0 and boot 1; and post bootrom output. There should be 7 invalid attempts with Switching BootPartitions message. 3. Take valid image, invalidate kwb header checksum and put it on boot0; plus erase boot1 and user. Bootrom should print "Invalid header checksum" message and it should be two times. Once for 0x1 and second time for overflowed 0x9.
Re: [PATCH RFC u-boot-mvebu 0/2] arm: mvebu: Fix eMMC boot
On Monday 06 March 2023 11:15:35 Martin Rowe wrote:
> On Sun, 5 Mar 2023 at 16:04, Pali Rohár wrote:
>
> > On Sunday 05 March 2023 12:46:34 Pali Rohár wrote:
> > > On Sunday 05 March 2023 02:24:27 Martin Rowe wrote:
> > > > On Sat, 4 Mar 2023 at 10:40, Pali Rohár wrote:
> > > >
> > > > > Boot configuration stored in EXT_CSC register is completely ignored
> > by
> > > > > BootROM:
> > > > >
> > > > >
> > https://lore.kernel.org/u-boot/CAOAjy5SYPPzWKok-BSGYwZwcKOQt_aZPgh6FTbrFd3F=8dm...@mail.gmail.com/
> > > > >
> > > > > Reflect this eMMC booting in documentation and in the code.
> > > > >
> > > > > Martin, can you test this patch series if SPL and main U-Boot is
> > loaded
> > > > > from the same eMMC HW partition?
> > > > >
> > > >
> > > > boot0: u-boot
> > > >
> > > > Works fine, no issues.
> > > >
> > > >
> > > > boot0: zeroed
> > > > boot1: u-boot
> > > > user: zeroed
> > > >
> > > > It succeeds, eventually...
> > > > ==
> > > > BootROM - 1.73
> > > >
> > > > Booting from MMC
> > > > BootROM: Bad header at offset
> > > > BootROM: Bad header at offset 0020
> > > > Switching BootPartitions.
> > > >
> > > > U-Boot SPL 2023.04-rc3-00159-gd1653548d2-dirty (Mar 05 2023 - 11:50:45
> > > > +1000)
> > > > High speed PHY - Version: 2.0
> > > > EEPROM TLV detection failed: Using static config for Clearfog Pro.
> > > > Detected Device ID 6828
> > > > board SerDes lanes topology details:
> > > > | Lane # | Speed | Type |
> > > >
> > > > | 0| 3 | SATA0 |
> > > > | 1| 0 | SGMII1 |
> > > > | 2| 5 | PCIe1 |
> > > > | 3| 5 | USB3 HOST1 |
> > > > | 4| 5 | PCIe2 |
> > > > | 5| 0 | SGMII2 |
> > > >
> > > > High speed PHY - Ended Successfully
> > > > mv_ddr: 14.0.0
> > > > DDR3 Training Sequence - Switching XBAR Window to FastPath Window
> > > > mv_ddr: completed successfully
> > > > Trying to boot from MMC1
> > > > ERROR: Invalid kwbimage v1
> > > > mmc_load_image_raw_sector: mmc block read error
> > > > spl: mmc: wrong boot mode
> > > > Trying to boot from BOOTROM
> > > > Returning to BootROM (return address 0x05c4)...
> > > > Timeout waiting card ready
> > > > BootROM: Image checksum verification PASSED
> > > >
> > > >
> > > > U-Boot 2023.04-rc3-00159-gd1653548d2-dirty (Mar 05 2023 - 11:50:45
> > +1000)
> > > >
> > > > SoC: MV88F6828-A0 at 1600 MHz
> > > > DRAM: 1 GiB (800 MHz, 32-bit, ECC not enabled)
> > > > Core: 38 devices, 22 uclasses, devicetree: separate
> > > > MMC: mv_sdh: 0
> > > > Loading Environment from MMC... *** Warning - bad CRC, using default
> > > > environment
> > > >
> > > > Model: SolidRun Clearfog A1
> > > > Board: SolidRun Clearfog Pro
> > > > Net:
> > > > Warning: ethernet@7 (eth1) using random MAC address -
> > 12:07:8b:f9:7a:6f
> > > > eth1: ethernet@7
> > > > Warning: ethernet@3 (eth2) using random MAC address -
> > ee:ed:f3:bb:c2:af
> > > > , eth2: ethernet@3
> > > > Warning: ethernet@34000 (eth3) using random MAC address -
> > ae:34:b9:bb:28:c6
> > > > , eth3: ethernet@34000
> > > > Hit any key to stop autoboot: 0
> > > > =>
> > > > ==
> > > >
> > > > Between "Returning to BootROM" and "Timeout waiting card ready" takes
> > > > around 315 seconds. That's long enough that I thought it had hung
> > > > completely and I only noticed it continue because I left it running
> > while
> > > > working on something else. I tried several things to reduce this
> > timeout,
> > > > including reverting to the "non-removable" dts for shdci, but nothing
> > seems
> > > > to affect it.
> > >
> > > Ok. So now it is in the state that it is working but is slow. Better
> > > than nothing.
> > >
> > > Message "Returning to BootROM" is printed by SPL and message
> > > "Timeout waiting card ready" is printed by BootROM. After printing
> > > "Returning to BootROM" is SPL jumping back to the BootROM so the delay
> > > is for sure in the BootROM. So seems that SPL reconfigures eMMC into
> > > state in which BootROM cannot work with it. Something timeouts, BootROM
> > > reconfigure/retry it and then it work again. It would be needed to
> > > investigate what is happening here. My guess is that this could have
> > > something with eMMC HW partition access, and code for switching
> > > partitions near SPL MMCSD_MODE_EMMCBOOT.
> >
> > Try this change?
> >
> > diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c
> > index b20eac3dcd38..eb59c41a824e 100644
> > --- a/arch/arm/mach-mvebu/spl.c
> > +++ b/arch/arm/mach-mvebu/spl.c
> > @@ -11,6 +11,7 @@
> > #include
> > #include
> > #include
> > +#include
> > #include
> > #include
> > #include
> > @@ -297,11 +298,33 @@ u32 spl_boot_device(void)
> >
> > #endif
> >
> > +void restore_emmc_boot_part_config(void)
> > +{
> > +#ifdef CONFIG_SPL_MMC
> > + struct mmc *mmc;
> > + int
Re: [PATCH RFC u-boot-mvebu 0/2] arm: mvebu: Fix eMMC boot
On Sun, 5 Mar 2023 at 16:04, Pali Rohár wrote:
> On Sunday 05 March 2023 12:46:34 Pali Rohár wrote:
> > On Sunday 05 March 2023 02:24:27 Martin Rowe wrote:
> > > On Sat, 4 Mar 2023 at 10:40, Pali Rohár wrote:
> > >
> > > > Boot configuration stored in EXT_CSC register is completely ignored
> by
> > > > BootROM:
> > > >
> > > >
> https://lore.kernel.org/u-boot/CAOAjy5SYPPzWKok-BSGYwZwcKOQt_aZPgh6FTbrFd3F=8dm...@mail.gmail.com/
> > > >
> > > > Reflect this eMMC booting in documentation and in the code.
> > > >
> > > > Martin, can you test this patch series if SPL and main U-Boot is
> loaded
> > > > from the same eMMC HW partition?
> > > >
> > >
> > > boot0: u-boot
> > >
> > > Works fine, no issues.
> > >
> > >
> > > boot0: zeroed
> > > boot1: u-boot
> > > user: zeroed
> > >
> > > It succeeds, eventually...
> > > ==
> > > BootROM - 1.73
> > >
> > > Booting from MMC
> > > BootROM: Bad header at offset
> > > BootROM: Bad header at offset 0020
> > > Switching BootPartitions.
> > >
> > > U-Boot SPL 2023.04-rc3-00159-gd1653548d2-dirty (Mar 05 2023 - 11:50:45
> > > +1000)
> > > High speed PHY - Version: 2.0
> > > EEPROM TLV detection failed: Using static config for Clearfog Pro.
> > > Detected Device ID 6828
> > > board SerDes lanes topology details:
> > > | Lane # | Speed | Type |
> > >
> > > | 0| 3 | SATA0 |
> > > | 1| 0 | SGMII1 |
> > > | 2| 5 | PCIe1 |
> > > | 3| 5 | USB3 HOST1 |
> > > | 4| 5 | PCIe2 |
> > > | 5| 0 | SGMII2 |
> > >
> > > High speed PHY - Ended Successfully
> > > mv_ddr: 14.0.0
> > > DDR3 Training Sequence - Switching XBAR Window to FastPath Window
> > > mv_ddr: completed successfully
> > > Trying to boot from MMC1
> > > ERROR: Invalid kwbimage v1
> > > mmc_load_image_raw_sector: mmc block read error
> > > spl: mmc: wrong boot mode
> > > Trying to boot from BOOTROM
> > > Returning to BootROM (return address 0x05c4)...
> > > Timeout waiting card ready
> > > BootROM: Image checksum verification PASSED
> > >
> > >
> > > U-Boot 2023.04-rc3-00159-gd1653548d2-dirty (Mar 05 2023 - 11:50:45
> +1000)
> > >
> > > SoC: MV88F6828-A0 at 1600 MHz
> > > DRAM: 1 GiB (800 MHz, 32-bit, ECC not enabled)
> > > Core: 38 devices, 22 uclasses, devicetree: separate
> > > MMC: mv_sdh: 0
> > > Loading Environment from MMC... *** Warning - bad CRC, using default
> > > environment
> > >
> > > Model: SolidRun Clearfog A1
> > > Board: SolidRun Clearfog Pro
> > > Net:
> > > Warning: ethernet@7 (eth1) using random MAC address -
> 12:07:8b:f9:7a:6f
> > > eth1: ethernet@7
> > > Warning: ethernet@3 (eth2) using random MAC address -
> ee:ed:f3:bb:c2:af
> > > , eth2: ethernet@3
> > > Warning: ethernet@34000 (eth3) using random MAC address -
> ae:34:b9:bb:28:c6
> > > , eth3: ethernet@34000
> > > Hit any key to stop autoboot: 0
> > > =>
> > > ==
> > >
> > > Between "Returning to BootROM" and "Timeout waiting card ready" takes
> > > around 315 seconds. That's long enough that I thought it had hung
> > > completely and I only noticed it continue because I left it running
> while
> > > working on something else. I tried several things to reduce this
> timeout,
> > > including reverting to the "non-removable" dts for shdci, but nothing
> seems
> > > to affect it.
> >
> > Ok. So now it is in the state that it is working but is slow. Better
> > than nothing.
> >
> > Message "Returning to BootROM" is printed by SPL and message
> > "Timeout waiting card ready" is printed by BootROM. After printing
> > "Returning to BootROM" is SPL jumping back to the BootROM so the delay
> > is for sure in the BootROM. So seems that SPL reconfigures eMMC into
> > state in which BootROM cannot work with it. Something timeouts, BootROM
> > reconfigure/retry it and then it work again. It would be needed to
> > investigate what is happening here. My guess is that this could have
> > something with eMMC HW partition access, and code for switching
> > partitions near SPL MMCSD_MODE_EMMCBOOT.
>
> Try this change?
>
> diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c
> index b20eac3dcd38..eb59c41a824e 100644
> --- a/arch/arm/mach-mvebu/spl.c
> +++ b/arch/arm/mach-mvebu/spl.c
> @@ -11,6 +11,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
> #include
> @@ -297,11 +298,33 @@ u32 spl_boot_device(void)
>
> #endif
>
> +void restore_emmc_boot_part_config(void)
> +{
> +#ifdef CONFIG_SPL_MMC
> + struct mmc *mmc;
> + int ret;
> +
> + mmc = find_mmc_device(0);
> + if (!mmc || !mmc->has_init || mmc->part_config ==
> MMCPART_NOAVAILABLE)
> + return;
> +
> + ret = mmc_set_part_conf(mmc,
> + EXT_CSD_EXTRACT_BOOT_ACK(mmc->part_config),
> + EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config),
> +
Re: [PATCH RFC u-boot-mvebu 0/2] arm: mvebu: Fix eMMC boot
On Sunday 05 March 2023 12:46:34 Pali Rohár wrote:
> On Sunday 05 March 2023 02:24:27 Martin Rowe wrote:
> > On Sat, 4 Mar 2023 at 10:40, Pali Rohár wrote:
> >
> > > Boot configuration stored in EXT_CSC register is completely ignored by
> > > BootROM:
> > >
> > > https://lore.kernel.org/u-boot/CAOAjy5SYPPzWKok-BSGYwZwcKOQt_aZPgh6FTbrFd3F=8dm...@mail.gmail.com/
> > >
> > > Reflect this eMMC booting in documentation and in the code.
> > >
> > > Martin, can you test this patch series if SPL and main U-Boot is loaded
> > > from the same eMMC HW partition?
> > >
> >
> > boot0: u-boot
> >
> > Works fine, no issues.
> >
> >
> > boot0: zeroed
> > boot1: u-boot
> > user: zeroed
> >
> > It succeeds, eventually...
> > ==
> > BootROM - 1.73
> >
> > Booting from MMC
> > BootROM: Bad header at offset
> > BootROM: Bad header at offset 0020
> > Switching BootPartitions.
> >
> > U-Boot SPL 2023.04-rc3-00159-gd1653548d2-dirty (Mar 05 2023 - 11:50:45
> > +1000)
> > High speed PHY - Version: 2.0
> > EEPROM TLV detection failed: Using static config for Clearfog Pro.
> > Detected Device ID 6828
> > board SerDes lanes topology details:
> > | Lane # | Speed | Type |
> >
> > | 0| 3 | SATA0 |
> > | 1| 0 | SGMII1 |
> > | 2| 5 | PCIe1 |
> > | 3| 5 | USB3 HOST1 |
> > | 4| 5 | PCIe2 |
> > | 5| 0 | SGMII2 |
> >
> > High speed PHY - Ended Successfully
> > mv_ddr: 14.0.0
> > DDR3 Training Sequence - Switching XBAR Window to FastPath Window
> > mv_ddr: completed successfully
> > Trying to boot from MMC1
> > ERROR: Invalid kwbimage v1
> > mmc_load_image_raw_sector: mmc block read error
> > spl: mmc: wrong boot mode
> > Trying to boot from BOOTROM
> > Returning to BootROM (return address 0x05c4)...
> > Timeout waiting card ready
> > BootROM: Image checksum verification PASSED
> >
> >
> > U-Boot 2023.04-rc3-00159-gd1653548d2-dirty (Mar 05 2023 - 11:50:45 +1000)
> >
> > SoC: MV88F6828-A0 at 1600 MHz
> > DRAM: 1 GiB (800 MHz, 32-bit, ECC not enabled)
> > Core: 38 devices, 22 uclasses, devicetree: separate
> > MMC: mv_sdh: 0
> > Loading Environment from MMC... *** Warning - bad CRC, using default
> > environment
> >
> > Model: SolidRun Clearfog A1
> > Board: SolidRun Clearfog Pro
> > Net:
> > Warning: ethernet@7 (eth1) using random MAC address - 12:07:8b:f9:7a:6f
> > eth1: ethernet@7
> > Warning: ethernet@3 (eth2) using random MAC address - ee:ed:f3:bb:c2:af
> > , eth2: ethernet@3
> > Warning: ethernet@34000 (eth3) using random MAC address - ae:34:b9:bb:28:c6
> > , eth3: ethernet@34000
> > Hit any key to stop autoboot: 0
> > =>
> > ==
> >
> > Between "Returning to BootROM" and "Timeout waiting card ready" takes
> > around 315 seconds. That's long enough that I thought it had hung
> > completely and I only noticed it continue because I left it running while
> > working on something else. I tried several things to reduce this timeout,
> > including reverting to the "non-removable" dts for shdci, but nothing seems
> > to affect it.
>
> Ok. So now it is in the state that it is working but is slow. Better
> than nothing.
>
> Message "Returning to BootROM" is printed by SPL and message
> "Timeout waiting card ready" is printed by BootROM. After printing
> "Returning to BootROM" is SPL jumping back to the BootROM so the delay
> is for sure in the BootROM. So seems that SPL reconfigures eMMC into
> state in which BootROM cannot work with it. Something timeouts, BootROM
> reconfigure/retry it and then it work again. It would be needed to
> investigate what is happening here. My guess is that this could have
> something with eMMC HW partition access, and code for switching
> partitions near SPL MMCSD_MODE_EMMCBOOT.
Try this change?
diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c
index b20eac3dcd38..eb59c41a824e 100644
--- a/arch/arm/mach-mvebu/spl.c
+++ b/arch/arm/mach-mvebu/spl.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -297,11 +298,33 @@ u32 spl_boot_device(void)
#endif
+void restore_emmc_boot_part_config(void)
+{
+#ifdef CONFIG_SPL_MMC
+ struct mmc *mmc;
+ int ret;
+
+ mmc = find_mmc_device(0);
+ if (!mmc || !mmc->has_init || mmc->part_config == MMCPART_NOAVAILABLE)
+ return;
+
+ ret = mmc_set_part_conf(mmc,
+ EXT_CSD_EXTRACT_BOOT_ACK(mmc->part_config),
+ EXT_CSD_EXTRACT_BOOT_PART(mmc->part_config),
+ EXT_CSD_EXTRACT_PARTITION_ACCESS(mmc->part_config));
+ if (ret)
+ printf("Failed to restore eMMC boot partition configuration\n");
+#endif
+}
+
int board_return_to_bootrom(struct spl_image_info *spl_image,
struct spl_boot_device *bootdev)
{
u32 *regs =
Re: [PATCH RFC u-boot-mvebu 0/2] arm: mvebu: Fix eMMC boot
On Sunday 05 March 2023 02:24:27 Martin Rowe wrote: > On Sat, 4 Mar 2023 at 10:40, Pali Rohár wrote: > > > Boot configuration stored in EXT_CSC register is completely ignored by > > BootROM: > > > > https://lore.kernel.org/u-boot/CAOAjy5SYPPzWKok-BSGYwZwcKOQt_aZPgh6FTbrFd3F=8dm...@mail.gmail.com/ > > > > Reflect this eMMC booting in documentation and in the code. > > > > Martin, can you test this patch series if SPL and main U-Boot is loaded > > from the same eMMC HW partition? > > > > boot0: u-boot > > Works fine, no issues. > > > boot0: zeroed > boot1: u-boot > user: zeroed > > It succeeds, eventually... > == > BootROM - 1.73 > > Booting from MMC > BootROM: Bad header at offset > BootROM: Bad header at offset 0020 > Switching BootPartitions. > > U-Boot SPL 2023.04-rc3-00159-gd1653548d2-dirty (Mar 05 2023 - 11:50:45 > +1000) > High speed PHY - Version: 2.0 > EEPROM TLV detection failed: Using static config for Clearfog Pro. > Detected Device ID 6828 > board SerDes lanes topology details: > | Lane # | Speed | Type | > > | 0| 3 | SATA0 | > | 1| 0 | SGMII1 | > | 2| 5 | PCIe1 | > | 3| 5 | USB3 HOST1 | > | 4| 5 | PCIe2 | > | 5| 0 | SGMII2 | > > High speed PHY - Ended Successfully > mv_ddr: 14.0.0 > DDR3 Training Sequence - Switching XBAR Window to FastPath Window > mv_ddr: completed successfully > Trying to boot from MMC1 > ERROR: Invalid kwbimage v1 > mmc_load_image_raw_sector: mmc block read error > spl: mmc: wrong boot mode > Trying to boot from BOOTROM > Returning to BootROM (return address 0x05c4)... > Timeout waiting card ready > BootROM: Image checksum verification PASSED > > > U-Boot 2023.04-rc3-00159-gd1653548d2-dirty (Mar 05 2023 - 11:50:45 +1000) > > SoC: MV88F6828-A0 at 1600 MHz > DRAM: 1 GiB (800 MHz, 32-bit, ECC not enabled) > Core: 38 devices, 22 uclasses, devicetree: separate > MMC: mv_sdh: 0 > Loading Environment from MMC... *** Warning - bad CRC, using default > environment > > Model: SolidRun Clearfog A1 > Board: SolidRun Clearfog Pro > Net: > Warning: ethernet@7 (eth1) using random MAC address - 12:07:8b:f9:7a:6f > eth1: ethernet@7 > Warning: ethernet@3 (eth2) using random MAC address - ee:ed:f3:bb:c2:af > , eth2: ethernet@3 > Warning: ethernet@34000 (eth3) using random MAC address - ae:34:b9:bb:28:c6 > , eth3: ethernet@34000 > Hit any key to stop autoboot: 0 > => > == > > Between "Returning to BootROM" and "Timeout waiting card ready" takes > around 315 seconds. That's long enough that I thought it had hung > completely and I only noticed it continue because I left it running while > working on something else. I tried several things to reduce this timeout, > including reverting to the "non-removable" dts for shdci, but nothing seems > to affect it. Ok. So now it is in the state that it is working but is slow. Better than nothing. Message "Returning to BootROM" is printed by SPL and message "Timeout waiting card ready" is printed by BootROM. After printing "Returning to BootROM" is SPL jumping back to the BootROM so the delay is for sure in the BootROM. So seems that SPL reconfigures eMMC into state in which BootROM cannot work with it. Something timeouts, BootROM reconfigure/retry it and then it work again. It would be needed to investigate what is happening here. My guess is that this could have something with eMMC HW partition access, and code for switching partitions near SPL MMCSD_MODE_EMMCBOOT. Could you try another test by completely erasing BOOT0, BOOT1 and USER data? And see what BootROM prints. > > When bootloader is stored on Boot 0, then SPL should take care of > > loading and executing main U-Boot. When it is stored on Boot 1 or User > > Data then SPL should return back to BootROM and let BootROM to load and > > execute main U-Boot. > > > > Pali Rohár (2): > > tools: kwboot: Fix MMC HW boot partitions info > > arm: mvebu: spl: Load proper U-Boot from eMMC Boot 0 partition > > > > arch/arm/mach-mvebu/Kconfig | 1 + > > arch/arm/mach-mvebu/spl.c | 13 +++-- > > tools/kwboot.c | 6 +++--- > > 3 files changed, 11 insertions(+), 9 deletions(-) > > > > -- > > 2.20.1 > > > >
Re: [PATCH RFC u-boot-mvebu 0/2] arm: mvebu: Fix eMMC boot
On Sat, 4 Mar 2023 at 10:40, Pali Rohár wrote: > Boot configuration stored in EXT_CSC register is completely ignored by > BootROM: > > https://lore.kernel.org/u-boot/CAOAjy5SYPPzWKok-BSGYwZwcKOQt_aZPgh6FTbrFd3F=8dm...@mail.gmail.com/ > > Reflect this eMMC booting in documentation and in the code. > > Martin, can you test this patch series if SPL and main U-Boot is loaded > from the same eMMC HW partition? > boot0: u-boot Works fine, no issues. boot0: zeroed boot1: u-boot user: zeroed It succeeds, eventually... == BootROM - 1.73 Booting from MMC BootROM: Bad header at offset BootROM: Bad header at offset 0020 Switching BootPartitions. U-Boot SPL 2023.04-rc3-00159-gd1653548d2-dirty (Mar 05 2023 - 11:50:45 +1000) High speed PHY - Version: 2.0 EEPROM TLV detection failed: Using static config for Clearfog Pro. Detected Device ID 6828 board SerDes lanes topology details: | Lane # | Speed | Type | | 0| 3 | SATA0 | | 1| 0 | SGMII1 | | 2| 5 | PCIe1 | | 3| 5 | USB3 HOST1 | | 4| 5 | PCIe2 | | 5| 0 | SGMII2 | High speed PHY - Ended Successfully mv_ddr: 14.0.0 DDR3 Training Sequence - Switching XBAR Window to FastPath Window mv_ddr: completed successfully Trying to boot from MMC1 ERROR: Invalid kwbimage v1 mmc_load_image_raw_sector: mmc block read error spl: mmc: wrong boot mode Trying to boot from BOOTROM Returning to BootROM (return address 0x05c4)... Timeout waiting card ready BootROM: Image checksum verification PASSED U-Boot 2023.04-rc3-00159-gd1653548d2-dirty (Mar 05 2023 - 11:50:45 +1000) SoC: MV88F6828-A0 at 1600 MHz DRAM: 1 GiB (800 MHz, 32-bit, ECC not enabled) Core: 38 devices, 22 uclasses, devicetree: separate MMC: mv_sdh: 0 Loading Environment from MMC... *** Warning - bad CRC, using default environment Model: SolidRun Clearfog A1 Board: SolidRun Clearfog Pro Net: Warning: ethernet@7 (eth1) using random MAC address - 12:07:8b:f9:7a:6f eth1: ethernet@7 Warning: ethernet@3 (eth2) using random MAC address - ee:ed:f3:bb:c2:af , eth2: ethernet@3 Warning: ethernet@34000 (eth3) using random MAC address - ae:34:b9:bb:28:c6 , eth3: ethernet@34000 Hit any key to stop autoboot: 0 => == Between "Returning to BootROM" and "Timeout waiting card ready" takes around 315 seconds. That's long enough that I thought it had hung completely and I only noticed it continue because I left it running while working on something else. I tried several things to reduce this timeout, including reverting to the "non-removable" dts for shdci, but nothing seems to affect it. When bootloader is stored on Boot 0, then SPL should take care of > loading and executing main U-Boot. When it is stored on Boot 1 or User > Data then SPL should return back to BootROM and let BootROM to load and > execute main U-Boot. > > Pali Rohár (2): > tools: kwboot: Fix MMC HW boot partitions info > arm: mvebu: spl: Load proper U-Boot from eMMC Boot 0 partition > > arch/arm/mach-mvebu/Kconfig | 1 + > arch/arm/mach-mvebu/spl.c | 13 +++-- > tools/kwboot.c | 6 +++--- > 3 files changed, 11 insertions(+), 9 deletions(-) > > -- > 2.20.1 > >
[PATCH RFC u-boot-mvebu 0/2] arm: mvebu: Fix eMMC boot
Boot configuration stored in EXT_CSC register is completely ignored by BootROM: https://lore.kernel.org/u-boot/CAOAjy5SYPPzWKok-BSGYwZwcKOQt_aZPgh6FTbrFd3F=8dm...@mail.gmail.com/ Reflect this eMMC booting in documentation and in the code. Martin, can you test this patch series if SPL and main U-Boot is loaded from the same eMMC HW partition? When bootloader is stored on Boot 0, then SPL should take care of loading and executing main U-Boot. When it is stored on Boot 1 or User Data then SPL should return back to BootROM and let BootROM to load and execute main U-Boot. Pali Rohár (2): tools: kwboot: Fix MMC HW boot partitions info arm: mvebu: spl: Load proper U-Boot from eMMC Boot 0 partition arch/arm/mach-mvebu/Kconfig | 1 + arch/arm/mach-mvebu/spl.c | 13 +++-- tools/kwboot.c | 6 +++--- 3 files changed, 11 insertions(+), 9 deletions(-) -- 2.20.1
