Beacon Embedded has an i.MX8M Plus development kit which consists
of a SOM + baseboard. The SOM includes Bluetooth, WiFi, QSPI, eMMC,
and one Ethernet PHY. The baseboard includes audio, HDMI, USB-C Dual
Role port, USB Hub with five ports, a PCIe slot, and a second Ethernet
PHY. The device trees are already queued for inclusion in Linux 6.3.
Signed-off-by: Adam Ford
Reviewed-by: Tom Rini
---
V5: Rebase off next instead of imx branch.
Replace u-boot,dm-spl with bootph-pre-ram
V4: Rebase off Marek V's EQOS series.
Remove code no longer needed from the EQOS series
Remove unnecessary include files.
V3: Fix Doc indicies to fix errors with 'make htmldocs'
Remove duplicated entries in imx8mp_beacon.env found in env_default.h
Remove unnecessary include options from imx8mp_beacon.h
V2: Move default environment from imx8mp_beacon.h to imx8mp_beacon.env
Move README to beacon-imx8mp.rst
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c160e884bf..eff9c69969 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -995,6 +995,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mn-beacon-kit.dtb \
imx8mq-mnt-reform2.dtb \
imx8mq-phanbell.dtb \
+ imx8mp-beacon-kit.dtb \
imx8mp-dhcom-pdk2.dtb \
imx8mp-evk.dtb \
imx8mp-icore-mx8mp-edimm2.2.dtb \
diff --git a/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi
b/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi
new file mode 100644
index 00..5ca631e9d8
--- /dev/null
+++ b/arch/arm/dts/imx8mp-beacon-kit-u-boot.dtsi
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Logic PD, Inc DBA Beacon EmbeddedWorks
+ */
+
+#include "imx8mp-u-boot.dtsi"
+
+/ {
+ wdt-reboot {
+ compatible = "wdt-reboot";
+ wdt = <>;
+ bootph-pre-ram;
+ };
+
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+};
+
+&{/soc@0/bus@3080/i2c@30a2/pmic@25} {
+ bootph-pre-ram;
+};
+
+&{/soc@0/bus@3080/i2c@30a2/pmic@25/regulators} {
+ bootph-pre-ram;
+};
+
+ {
+ bootph-pre-ram;
+};
+
+ {
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-parents;
+ /delete-property/ assigned-clock-rates;
+};
+
+ {
+ reset-gpios = < 22 GPIO_ACTIVE_LOW>;
+ reset-assert-us = <15000>;
+ reset-deassert-us = <10>;
+};
+
+ {
+ phy-reset-gpios = < 18 GPIO_ACTIVE_LOW>;
+ phy-reset-duration = <15>;
+ phy-reset-post-delay = <100>;
+};
+
+ {
+ assigned-clock-parents = < IMX8MP_SYS_PLL1_400M>;
+};
+
+ {
+ bootph-pre-ram;
+};
+
+ {
+ bootph-pre-ram;
+};
+
+ {
+ bootph-pre-ram;
+};
+
+ {
+ bootph-pre-ram;
+};
+
+ {
+ bootph-pre-ram;
+};
+
+ {
+ bootph-pre-ram;
+};
+
+ {
+ bootph-pre-ram;
+};
+
+ {
+ bootph-pre-ram;
+};
+
+ {
+ compatible = "ti,tca6416";
+ label = "exp4";
+};
+
+_1 {
+ compatible = "ti,tca6416";
+ label = "exp4";
+};
+
+_3 {
+ compatible = "ti,tca6416";
+ label = "exp2";
+};
+
+_i2c1 {
+ bootph-pre-ram;
+};
+
+_pmic {
+ bootph-pre-ram;
+};
+
+_reg_usdhc2_vmmc {
+ bootph-pre-ram;
+};
+
+_uart2 {
+ bootph-pre-ram;
+};
+
+_usdhc2_gpio {
+ bootph-pre-ram;
+};
+
+_usdhc2 {
+ bootph-pre-ram;
+};
+
+_usdhc3 {
+ bootph-pre-ram;
+};
+
+_wdog {
+ bootph-pre-ram;
+};
+
+_usdhc2_vmmc {
+ bootph-pre-ram;
+ u-boot,off-on-delay-us = <2>;
+};
+
+_jr0 {
+ bootph-pre-ram;
+};
+
+_jr1 {
+ bootph-pre-ram;
+};
+
+_jr2 {
+ bootph-pre-ram;
+};
+
+ {
+ compatible = "tcg,tpm_tis-spi";
+};
+
+ {
+ bootph-pre-ram;
+};
+
+ {
+ bootph-pre-ram;
+ assigned-clocks = < IMX8MP_CLK_USDHC1>;
+ assigned-clock-rates = <4>;
+ assigned-clock-parents = < IMX8MP_SYS_PLL1_400M>;
+};
+
+ {
+ bootph-pre-ram;
+ sd-uhs-sdr104;
+ sd-uhs-ddr50;
+ assigned-clocks = < IMX8MP_CLK_USDHC2>;
+ assigned-clock-rates = <4>;
+ assigned-clock-parents = < IMX8MP_SYS_PLL1_400M>;
+};
+
+ {
+ bootph-pre-ram;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ assigned-clocks = < IMX8MP_CLK_USDHC3>;
+ assigned-clock-rates = <4>;
+ assigned-clock-parents = < IMX8MP_SYS_PLL1_400M>;
+};
+
+_0 {
+ dma-ranges = <0x4000 0x4000 0xc000>;
+ /delete-property/ power-domains;
+};
+
+_1 {
+ dma-ranges = <0x4000 0x4000 0xc000>;
+ /delete-property/ power-domains;
+};
+
+_dwc3_0 {
+ compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
+ assigned-clocks = < IMX8MP_CLK_HSIO_AXI>;
+ assigned-clock-parents = < IMX8MP_SYS_PLL1_800M>;
+ assigned-clock-rates = <4>;
+};
+
+_dwc3_1 {
+ compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
+
