Re: [PATCH v1 1/1] drivers: misc: Add socfpga_dtreg driver for Intel SoCFPGA
On Fri, Jan 05, 2024 at 01:54:34AM +, Lau, Wan Yee wrote: > > > > -Original Message- > > From: Tom Rini > > Sent: Thursday, December 21, 2023 10:26 PM > > To: Lau, Wan Yee > > Cc: Marek Vasut ; Chee, Tien Fong > > ; u-boot@lists.denx.de; Hea, Kok Kiang > > ; Maniyam, Dinesh ; > > Ng, Boon Khai ; Yuslaimi, Alif Zakuan > > ; Chong, Teik Heng > > ; Zamri, Muhammad Hazim Izzat > > ; Lim, Jit Loon > > ; Tang, Sieu Mun > > Subject: Re: [PATCH v1 1/1] drivers: misc: Add socfpga_dtreg driver for > > Intel > > SoCFPGA > > > > On Thu, Dec 21, 2023 at 01:59:02AM +, Lau, Wan Yee wrote: > > > > > > > > > > -Original Message- > > > > From: Marek Vasut > > > > Sent: Thursday, December 21, 2023 12:11 AM > > > > To: Lau, Wan Yee ; Chee, Tien Fong > > > > ; u-boot@lists.denx.de > > > > Cc: Simon Glass ; Kever Yang > > > > ; Bin Meng ; Jonas > > > > Karlman ; Jean- Marie Lemetayer > > > > ; Peng Fan ; Vladimir > > > > Zapolskiy ; Konrad Dybcio > > > > ; Simon Goldschmidt > > > > ; Hea, Kok Kiang > > > > ; Maniyam, Dinesh > > > > ; Ng, Boon Khai ; > > > > Yuslaimi, Alif Zakuan ; Chong, Teik > > > > Heng ; Zamri, Muhammad Hazim Izzat > > > > ; Lim, Jit Loon > > > > ; Tang, Sieu Mun ; > > > > Tom Rini > > > > Subject: Re: [PATCH v1 1/1] drivers: misc: Add socfpga_dtreg driver > > > > for Intel SoCFPGA > > > > > > > > On 12/20/23 04:09, Lau, Wan Yee wrote: > > > > > > > > Hi, > > > > > > > > can you trim the CC list to relevant people ? > > > > > > > > [...] > > > > > > > > >>>> +++ b/drivers/misc/socfpga_dtreg.c > > > > >>>> @@ -0,0 +1,117 @@ > > > > >>>> +// SPDX-License-Identifier: GPL-2.0 > > > > >>>> +/* > > > > >>>> + * Copyright (C) 2023 Intel Corporation */ > > > > >>>> + > > > > >>>> +#include > > > > >>>> +#include > > > > >>>> +#include > > > > >>>> +#include > > > > >>> > > > > >>> Please move above to here > > > > >>> > > > > >>>> +#include > > > > >> > > > > >> A good starting point would be to have socfpga 64bit maintainer , > > > > >> without that , these patches are only being archived . > > > > > > > > > > Hi, > > > > > > > > > > Is only one socfpga 64bit maintainer needed or the whole socfpga > > > > > 64bit > > > > maintainer need to be included for this driver? > > > > > > > > U-Boot currently does not have any SoCFPGA 64bit maintainer, that > > > > needs to be fixed . > > > > > > Can you share the steps on how to get this fixed? Is there a guide on > > > how to add/process new maintainers? > > > > Well, the first step is to identify someone with familiarity with SoCFPGA > > and U- > > Boot and time to spend in the community. > > > > -- > > Tom > > Thanks. What is the next step after identifying the person that fits the > requirement? > How do I proceed with adding the new maintainers. Having them talk with me, off list. -- Tom signature.asc Description: PGP signature
RE: [PATCH v1 1/1] drivers: misc: Add socfpga_dtreg driver for Intel SoCFPGA
> -Original Message- > From: Tom Rini > Sent: Thursday, December 21, 2023 10:26 PM > To: Lau, Wan Yee > Cc: Marek Vasut ; Chee, Tien Fong > ; u-boot@lists.denx.de; Hea, Kok Kiang > ; Maniyam, Dinesh ; > Ng, Boon Khai ; Yuslaimi, Alif Zakuan > ; Chong, Teik Heng > ; Zamri, Muhammad Hazim Izzat > ; Lim, Jit Loon > ; Tang, Sieu Mun > Subject: Re: [PATCH v1 1/1] drivers: misc: Add socfpga_dtreg driver for Intel > SoCFPGA > > On Thu, Dec 21, 2023 at 01:59:02AM +, Lau, Wan Yee wrote: > > > > > > > -Original Message- > > > From: Marek Vasut > > > Sent: Thursday, December 21, 2023 12:11 AM > > > To: Lau, Wan Yee ; Chee, Tien Fong > > > ; u-boot@lists.denx.de > > > Cc: Simon Glass ; Kever Yang > > > ; Bin Meng ; Jonas > > > Karlman ; Jean- Marie Lemetayer > > > ; Peng Fan ; Vladimir > > > Zapolskiy ; Konrad Dybcio > > > ; Simon Goldschmidt > > > ; Hea, Kok Kiang > > > ; Maniyam, Dinesh > > > ; Ng, Boon Khai ; > > > Yuslaimi, Alif Zakuan ; Chong, Teik > > > Heng ; Zamri, Muhammad Hazim Izzat > > > ; Lim, Jit Loon > > > ; Tang, Sieu Mun ; > > > Tom Rini > > > Subject: Re: [PATCH v1 1/1] drivers: misc: Add socfpga_dtreg driver > > > for Intel SoCFPGA > > > > > > On 12/20/23 04:09, Lau, Wan Yee wrote: > > > > > > Hi, > > > > > > can you trim the CC list to relevant people ? > > > > > > [...] > > > > > > >>>> +++ b/drivers/misc/socfpga_dtreg.c > > > >>>> @@ -0,0 +1,117 @@ > > > >>>> +// SPDX-License-Identifier: GPL-2.0 > > > >>>> +/* > > > >>>> + * Copyright (C) 2023 Intel Corporation */ > > > >>>> + > > > >>>> +#include > > > >>>> +#include > > > >>>> +#include > > > >>>> +#include > > > >>> > > > >>> Please move above to here > > > >>> > > > >>>> +#include > > > >> > > > >> A good starting point would be to have socfpga 64bit maintainer , > > > >> without that , these patches are only being archived . > > > > > > > > Hi, > > > > > > > > Is only one socfpga 64bit maintainer needed or the whole socfpga > > > > 64bit > > > maintainer need to be included for this driver? > > > > > > U-Boot currently does not have any SoCFPGA 64bit maintainer, that > > > needs to be fixed . > > > > Can you share the steps on how to get this fixed? Is there a guide on > > how to add/process new maintainers? > > Well, the first step is to identify someone with familiarity with SoCFPGA and > U- > Boot and time to spend in the community. > > -- > Tom Thanks. What is the next step after identifying the person that fits the requirement? How do I proceed with adding the new maintainers.
Re: [PATCH v1 1/1] drivers: misc: Add socfpga_dtreg driver for Intel SoCFPGA
On Thu, Dec 21, 2023 at 01:59:02AM +, Lau, Wan Yee wrote: > > > > -Original Message- > > From: Marek Vasut > > Sent: Thursday, December 21, 2023 12:11 AM > > To: Lau, Wan Yee ; Chee, Tien Fong > > ; u-boot@lists.denx.de > > Cc: Simon Glass ; Kever Yang ; > > Bin Meng ; Jonas Karlman ; Jean- > > Marie Lemetayer ; Peng Fan ; > > Vladimir Zapolskiy ; Konrad Dybcio > > ; Simon Goldschmidt > > ; Hea, Kok Kiang > > ; Maniyam, Dinesh ; > > Ng, Boon Khai ; Yuslaimi, Alif Zakuan > > ; Chong, Teik Heng > > ; Zamri, Muhammad Hazim Izzat > > ; Lim, Jit Loon > > ; Tang, Sieu Mun ; Tom Rini > > > > Subject: Re: [PATCH v1 1/1] drivers: misc: Add socfpga_dtreg driver for > > Intel > > SoCFPGA > > > > On 12/20/23 04:09, Lau, Wan Yee wrote: > > > > Hi, > > > > can you trim the CC list to relevant people ? > > > > [...] > > > > >>>> +++ b/drivers/misc/socfpga_dtreg.c > > >>>> @@ -0,0 +1,117 @@ > > >>>> +// SPDX-License-Identifier: GPL-2.0 > > >>>> +/* > > >>>> + * Copyright (C) 2023 Intel Corporation */ > > >>>> + > > >>>> +#include > > >>>> +#include > > >>>> +#include > > >>>> +#include > > >>> > > >>> Please move above to here > > >>> > > >>>> +#include > > >> > > >> A good starting point would be to have socfpga 64bit maintainer , > > >> without that , these patches are only being archived . > > > > > > Hi, > > > > > > Is only one socfpga 64bit maintainer needed or the whole socfpga 64bit > > maintainer need to be included for this driver? > > > > U-Boot currently does not have any SoCFPGA 64bit maintainer, that needs to > > be > > fixed . > > Can you share the steps on how to get this fixed? Is there a guide on how to > add/process new maintainers? Well, the first step is to identify someone with familiarity with SoCFPGA and U-Boot and time to spend in the community. -- Tom signature.asc Description: PGP signature
RE: [PATCH v1 1/1] drivers: misc: Add socfpga_dtreg driver for Intel SoCFPGA
> -Original Message- > From: Marek Vasut > Sent: Thursday, December 21, 2023 12:11 AM > To: Lau, Wan Yee ; Chee, Tien Fong > ; u-boot@lists.denx.de > Cc: Simon Glass ; Kever Yang ; > Bin Meng ; Jonas Karlman ; Jean- > Marie Lemetayer ; Peng Fan ; > Vladimir Zapolskiy ; Konrad Dybcio > ; Simon Goldschmidt > ; Hea, Kok Kiang > ; Maniyam, Dinesh ; > Ng, Boon Khai ; Yuslaimi, Alif Zakuan > ; Chong, Teik Heng > ; Zamri, Muhammad Hazim Izzat > ; Lim, Jit Loon > ; Tang, Sieu Mun ; Tom Rini > > Subject: Re: [PATCH v1 1/1] drivers: misc: Add socfpga_dtreg driver for Intel > SoCFPGA > > On 12/20/23 04:09, Lau, Wan Yee wrote: > > Hi, > > can you trim the CC list to relevant people ? > > [...] > > >>>> +++ b/drivers/misc/socfpga_dtreg.c > >>>> @@ -0,0 +1,117 @@ > >>>> +// SPDX-License-Identifier: GPL-2.0 > >>>> +/* > >>>> + * Copyright (C) 2023 Intel Corporation */ > >>>> + > >>>> +#include > >>>> +#include > >>>> +#include > >>>> +#include > >>> > >>> Please move above to here > >>> > >>>> +#include > >> > >> A good starting point would be to have socfpga 64bit maintainer , > >> without that , these patches are only being archived . > > > > Hi, > > > > Is only one socfpga 64bit maintainer needed or the whole socfpga 64bit > maintainer need to be included for this driver? > > U-Boot currently does not have any SoCFPGA 64bit maintainer, that needs to be > fixed . Can you share the steps on how to get this fixed? Is there a guide on how to add/process new maintainers?
Re: [PATCH v1 1/1] drivers: misc: Add socfpga_dtreg driver for Intel SoCFPGA
On 12/20/23 04:09, Lau, Wan Yee wrote: Hi, can you trim the CC list to relevant people ? [...] +++ b/drivers/misc/socfpga_dtreg.c @@ -0,0 +1,117 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 Intel Corporation */ + +#include +#include +#include +#include Please move above to here +#include A good starting point would be to have socfpga 64bit maintainer , without that , these patches are only being archived . Hi, Is only one socfpga 64bit maintainer needed or the whole socfpga 64bit maintainer need to be included for this driver? U-Boot currently does not have any SoCFPGA 64bit maintainer, that needs to be fixed .
RE: [PATCH v1 1/1] drivers: misc: Add socfpga_dtreg driver for Intel SoCFPGA
> -Original Message-
> From: Marek Vasut
> Sent: Tuesday, December 19, 2023 5:54 PM
> To: Chee, Tien Fong ; Lau, Wan Yee
> ; u-boot@lists.denx.de
> Cc: Simon Glass ; Kever Yang ;
> Bin Meng ; Jonas Karlman ; Jean-
> Marie Lemetayer ; Peng Fan ;
> Vladimir Zapolskiy ; Konrad Dybcio
> ; Simon Goldschmidt
> ; Hea, Kok Kiang
> ; Maniyam, Dinesh ;
> Ng, Boon Khai ; Yuslaimi, Alif Zakuan
> ; Chong, Teik Heng
> ; Zamri, Muhammad Hazim Izzat
> ; Lim, Jit Loon
> ; Tang, Sieu Mun
> Subject: Re: [PATCH v1 1/1] drivers: misc: Add socfpga_dtreg driver for Intel
> SoCFPGA
>
> On 12/19/23 08:03, Chee, Tien Fong wrote:
> > Hi,
> >
> >> -Original Message-
> >> From: Lau, Wan Yee
> >> Sent: Friday, December 8, 2023 4:37 PM
> >> To: u-boot@lists.denx.de
> >> Cc: Simon Glass ; Kever Yang >> chips.com>; Bin Meng ; Jonas Karlman
> >> ; Jean-Marie Lemetayer ;
> >> Peng Fan ; Vladimir Zapolskiy
> >> ; Konrad Dybcio
> >> ; Marek Vasut ; Simon
> >> Goldschmidt ; Chee, Tien Fong
> >> ; Hea, Kok Kiang ;
> >> Maniyam, Dinesh ; Ng, Boon Khai
> >> ; Yuslaimi, Alif Zakuan
> >> ; Chong, Teik Heng
> >> ; Zamri, Muhammad Hazim Izzat
> >> ; Lim, Jit Loon
> >> ; Tang, Sieu Mun
> >> Subject: [PATCH v1 1/1] drivers: misc: Add socfpga_dtreg driver for
> >> Intel SoCFPGA
> >>
> >> From: Wan Yee Lau
> >>
> >> This driver can be used to provide user a clean interface and all
> >> register settings are centralized in one place, device tree without
> >> need for hardcoding in the source code.
> >>
> >> Signed-off-by: Wan Yee Lau
> >> ---
> >> .../misc/socfpga_dtreg.txt| 66 ++
> >> drivers/misc/Kconfig | 7 ++
> >> drivers/misc/Makefile | 1 +
> >> drivers/misc/socfpga_dtreg.c | 117 ++
> >> 4 files changed, 191 insertions(+)
> >> create mode 100644 doc/device-tree-bindings/misc/socfpga_dtreg.txt
> >> create mode 100644 drivers/misc/socfpga_dtreg.c
> >>
> >> diff --git a/doc/device-tree-bindings/misc/socfpga_dtreg.txt
> >> b/doc/device- tree-bindings/misc/socfpga_dtreg.txt
> >> new file mode 100644
> >> index 00..5458103f88
> >> --- /dev/null
> >> +++ b/doc/device-tree-bindings/misc/socfpga_dtreg.txt
> >> @@ -0,0 +1,66 @@
> >> +* Firewall and privilege register settings in device tree
> >> +
> >> +Required properties:
> >> +
> >> +
> >> +- compatible: should contain "intel,socfpga-dtreg"
> >> +- reg: Physical base address and size of block register.
> >> +- intel,offset-settings: 32-bit offset address of block register,
> >> + followed by 32-bit value settings and
> >> + the masking bits, only masking bit
> >> + set to 1 allows modification.
> >> +
> >> +This driver can be used to provide user a clean interface and all
> >> +register settings are centralized in one place, device tree without
> >> +need for hardcoding in the source code.
> >> +
> >> +General setup would be to set the memory address used by the
> >> +register, followed by the offset-settings containing the 32-bit
> >> +offset address of the block register, then the 32-bit value settings
> >> +and lastly the masking bits.
> >> +
> >> +Example:
> >> +
> >> +
> >> +Configuration for multiple dtreg node support in device tree:
> >> +
> >> + socfpga_mainfirewall: socfpga-mainfirewall {
> >> + compatible = "intel,socfpga-dtreg";
> >> + #address-cells = <1>;
> >> +#size-cells = <1>;
> >> + bootph-all;
> >> +
> >> +
> >> coh_cpu0_bypass_OC_Firewall_main_Firewall@f7100200 {
> >> + reg = <0xf7100200 0x0014>;
> >> +intel,offset-settings =
> >> + /* Disable ocram security at CCU
> >> + for non secure
> >> access */
> >> +<0x004 0x8000 0xe007>,
> >> +<0x008 0x8000 0xe007>,
> >>
Re: [PATCH v1 1/1] drivers: misc: Add socfpga_dtreg driver for Intel SoCFPGA
On 12/19/23 08:03, Chee, Tien Fong wrote:
Hi,
-Original Message-
From: Lau, Wan Yee
Sent: Friday, December 8, 2023 4:37 PM
To: u-boot@lists.denx.de
Cc: Simon Glass ; Kever Yang ; Bin Meng ; Jonas Karlman
; Jean-Marie Lemetayer ; Peng
Fan ; Vladimir Zapolskiy
; Konrad Dybcio ;
Marek Vasut ; Simon Goldschmidt
; Chee, Tien Fong
; Hea, Kok Kiang ;
Maniyam, Dinesh ; Ng, Boon Khai
; Yuslaimi, Alif Zakuan
; Chong, Teik Heng
; Zamri, Muhammad Hazim Izzat
; Lim, Jit Loon
; Tang, Sieu Mun
Subject: [PATCH v1 1/1] drivers: misc: Add socfpga_dtreg driver for Intel
SoCFPGA
From: Wan Yee Lau
This driver can be used to provide user a clean interface and all register
settings are centralized in one place, device tree without need for
hardcoding in the source code.
Signed-off-by: Wan Yee Lau
---
.../misc/socfpga_dtreg.txt| 66 ++
drivers/misc/Kconfig | 7 ++
drivers/misc/Makefile | 1 +
drivers/misc/socfpga_dtreg.c | 117 ++
4 files changed, 191 insertions(+)
create mode 100644 doc/device-tree-bindings/misc/socfpga_dtreg.txt
create mode 100644 drivers/misc/socfpga_dtreg.c
diff --git a/doc/device-tree-bindings/misc/socfpga_dtreg.txt b/doc/device-
tree-bindings/misc/socfpga_dtreg.txt
new file mode 100644
index 00..5458103f88
--- /dev/null
+++ b/doc/device-tree-bindings/misc/socfpga_dtreg.txt
@@ -0,0 +1,66 @@
+* Firewall and privilege register settings in device tree
+
+Required properties:
+
+
+- compatible: should contain "intel,socfpga-dtreg"
+- reg: Physical base address and size of block register.
+- intel,offset-settings: 32-bit offset address of block register,
+followed by 32-bit value settings and
+the masking bits, only masking bit
+set to 1 allows modification.
+
+This driver can be used to provide user a clean interface and all
+register settings are centralized in one place, device tree without
+need for hardcoding in the source code.
+
+General setup would be to set the memory address used by the register,
+followed by the offset-settings containing the 32-bit offset address of
+the block register, then the 32-bit value settings and lastly the
+masking bits.
+
+Example:
+
+
+Configuration for multiple dtreg node support in device tree:
+
+ socfpga_mainfirewall: socfpga-mainfirewall {
+ compatible = "intel,socfpga-dtreg";
+ #address-cells = <1>;
+#size-cells = <1>;
+ bootph-all;
+
+coh_cpu0_bypass_OC_Firewall_main_Firewall@f7100200 {
+ reg = <0xf7100200 0x0014>;
+intel,offset-settings =
+ /* Disable ocram security at CCU for
non secure
access */
+<0x004 0x8000 0xe007>,
+<0x008 0x8000 0xe007>,
+<0x00c 0x8000 0xe007>,
+<0x010 0x8000 0xe007>;
+bootph-all;
+};
+};
+
+ socfpga_mpfefirewall: socfpga-mpfefirewall {
+ compatible = "intel,socfpga-dtreg";
+ #address-cells = <1>;
+#size-cells = <1>;
+ bootph-all;
+
+soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f802 {
+reg = <0xf802 0x001c>;
+intel,offset-settings =
+/* Disable MPFE firewall for SMMU */
+<0x 0x00010101 0x00010101>,
+/* Disable MPFE firewall for HMC
adapter */
+<0x0004 0x0001 0x00010101>;
+ bootph-all;
+};
+};
+
+To call the nodes use:
+
+ ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-
mainfirewall", );
+ ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-
mpfefirewall",
+);
+
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index
fccd9b89b8..c423905ba2 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -683,4 +683,11 @@ config SL28CPLD
the base driver which provides common access methods for the
sub-drivers.
+config SPL_SOCFPGA_DT_REG
+ bool "Enable register setting from device tree in SPL"
+ depends on SPL
+ help
+ Enable register setting from device tree. This also
+ provides
RE: [PATCH v1 1/1] drivers: misc: Add socfpga_dtreg driver for Intel SoCFPGA
Hi,
> -Original Message-
> From: Lau, Wan Yee
> Sent: Friday, December 8, 2023 4:37 PM
> To: u-boot@lists.denx.de
> Cc: Simon Glass ; Kever Yang chips.com>; Bin Meng ; Jonas Karlman
> ; Jean-Marie Lemetayer ; Peng
> Fan ; Vladimir Zapolskiy
> ; Konrad Dybcio ;
> Marek Vasut ; Simon Goldschmidt
> ; Chee, Tien Fong
> ; Hea, Kok Kiang ;
> Maniyam, Dinesh ; Ng, Boon Khai
> ; Yuslaimi, Alif Zakuan
> ; Chong, Teik Heng
> ; Zamri, Muhammad Hazim Izzat
> ; Lim, Jit Loon
> ; Tang, Sieu Mun
> Subject: [PATCH v1 1/1] drivers: misc: Add socfpga_dtreg driver for Intel
> SoCFPGA
>
> From: Wan Yee Lau
>
> This driver can be used to provide user a clean interface and all register
> settings are centralized in one place, device tree without need for
> hardcoding in the source code.
>
> Signed-off-by: Wan Yee Lau
> ---
> .../misc/socfpga_dtreg.txt| 66 ++
> drivers/misc/Kconfig | 7 ++
> drivers/misc/Makefile | 1 +
> drivers/misc/socfpga_dtreg.c | 117 ++
> 4 files changed, 191 insertions(+)
> create mode 100644 doc/device-tree-bindings/misc/socfpga_dtreg.txt
> create mode 100644 drivers/misc/socfpga_dtreg.c
>
> diff --git a/doc/device-tree-bindings/misc/socfpga_dtreg.txt b/doc/device-
> tree-bindings/misc/socfpga_dtreg.txt
> new file mode 100644
> index 00..5458103f88
> --- /dev/null
> +++ b/doc/device-tree-bindings/misc/socfpga_dtreg.txt
> @@ -0,0 +1,66 @@
> +* Firewall and privilege register settings in device tree
> +
> +Required properties:
> +
> +
> +- compatible: should contain "intel,socfpga-dtreg"
> +- reg: Physical base address and size of block register.
> +- intel,offset-settings: 32-bit offset address of block register,
> + followed by 32-bit value settings and
> + the masking bits, only masking bit
> + set to 1 allows modification.
> +
> +This driver can be used to provide user a clean interface and all
> +register settings are centralized in one place, device tree without
> +need for hardcoding in the source code.
> +
> +General setup would be to set the memory address used by the register,
> +followed by the offset-settings containing the 32-bit offset address of
> +the block register, then the 32-bit value settings and lastly the
> +masking bits.
> +
> +Example:
> +
> +
> +Configuration for multiple dtreg node support in device tree:
> +
> + socfpga_mainfirewall: socfpga-mainfirewall {
> + compatible = "intel,socfpga-dtreg";
> + #address-cells = <1>;
> +#size-cells = <1>;
> + bootph-all;
> +
> +coh_cpu0_bypass_OC_Firewall_main_Firewall@f7100200 {
> + reg = <0xf7100200 0x0014>;
> +intel,offset-settings =
> + /* Disable ocram security at CCU for
> non secure
> access */
> +<0x004 0x8000 0xe007>,
> +<0x008 0x8000 0xe007>,
> +<0x00c 0x8000 0xe007>,
> +<0x010 0x8000 0xe007>;
> +bootph-all;
> +};
> +};
> +
> + socfpga_mpfefirewall: socfpga-mpfefirewall {
> + compatible = "intel,socfpga-dtreg";
> + #address-cells = <1>;
> +#size-cells = <1>;
> + bootph-all;
> +
> +soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f802 {
> +reg = <0xf802 0x001c>;
> +intel,offset-settings =
> +/* Disable MPFE firewall for SMMU */
> +<0x 0x00010101 0x00010101>,
> +/* Disable MPFE firewall for HMC
> adapter */
> +<0x0004 0x0001 0x00010101>;
> + bootph-all;
> +};
> +};
> +
> +To call the nodes use:
> +
> + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-
> mainfirewall", );
> + ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-
> mpfefirewall",
>
[PATCH v1 1/1] drivers: misc: Add socfpga_dtreg driver for Intel SoCFPGA
From: Wan Yee Lau
This driver can be used to provide user a clean interface and all register
settings are centralized in one place, device tree without need for
hardcoding in the source code.
Signed-off-by: Wan Yee Lau
---
.../misc/socfpga_dtreg.txt| 66 ++
drivers/misc/Kconfig | 7 ++
drivers/misc/Makefile | 1 +
drivers/misc/socfpga_dtreg.c | 117 ++
4 files changed, 191 insertions(+)
create mode 100644 doc/device-tree-bindings/misc/socfpga_dtreg.txt
create mode 100644 drivers/misc/socfpga_dtreg.c
diff --git a/doc/device-tree-bindings/misc/socfpga_dtreg.txt
b/doc/device-tree-bindings/misc/socfpga_dtreg.txt
new file mode 100644
index 00..5458103f88
--- /dev/null
+++ b/doc/device-tree-bindings/misc/socfpga_dtreg.txt
@@ -0,0 +1,66 @@
+* Firewall and privilege register settings in device tree
+
+Required properties:
+
+
+- compatible: should contain "intel,socfpga-dtreg"
+- reg: Physical base address and size of block register.
+- intel,offset-settings: 32-bit offset address of block register,
+followed by 32-bit value settings and
+the masking bits, only masking bit
+set to 1 allows modification.
+
+This driver can be used to provide user a clean interface and all register
+settings are centralized in one place, device tree without need for
+hardcoding in the source code.
+
+General setup would be to set the memory address used by the register,
+followed by the offset-settings containing the 32-bit offset address
+of the block register, then the 32-bit value settings and
+lastly the masking bits.
+
+Example:
+
+
+Configuration for multiple dtreg node support in device tree:
+
+ socfpga_mainfirewall: socfpga-mainfirewall {
+ compatible = "intel,socfpga-dtreg";
+ #address-cells = <1>;
+#size-cells = <1>;
+ bootph-all;
+
+coh_cpu0_bypass_OC_Firewall_main_Firewall@f7100200 {
+ reg = <0xf7100200 0x0014>;
+intel,offset-settings =
+ /* Disable ocram security at CCU for
non secure access */
+<0x004 0x8000 0xe007>,
+<0x008 0x8000 0xe007>,
+<0x00c 0x8000 0xe007>,
+<0x010 0x8000 0xe007>;
+bootph-all;
+};
+};
+
+ socfpga_mpfefirewall: socfpga-mpfefirewall {
+ compatible = "intel,socfpga-dtreg";
+ #address-cells = <1>;
+#size-cells = <1>;
+ bootph-all;
+
+soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f802 {
+reg = <0xf802 0x001c>;
+intel,offset-settings =
+/* Disable MPFE firewall for SMMU */
+<0x 0x00010101 0x00010101>,
+/* Disable MPFE firewall for HMC
adapter */
+<0x0004 0x0001 0x00010101>;
+ bootph-all;
+};
+};
+
+To call the nodes use:
+
+ ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-mainfirewall",
);
+ ret = uclass_get_device_by_name(UCLASS_NOP, "socfpga-mpfefirewall",
);
+
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index fccd9b89b8..c423905ba2 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -683,4 +683,11 @@ config SL28CPLD
the base driver which provides common access methods for the
sub-drivers.
+config SPL_SOCFPGA_DT_REG
+ bool "Enable register setting from device tree in SPL"
+ depends on SPL
+ help
+ Enable register setting from device tree. This also
+ provides user a clean interface and all register settings are
+ centralized in one place, device tree.
endmenu
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index b67b82358a..8f813edd84 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -89,3 +89,4 @@ obj-$(CONFIG_K3_AVS0) += k3_avs.o
obj-$(CONFIG_ESM_K3) += k3_esm.o
obj-$(CONFIG_ESM_PMIC) += esm_pmic.o
obj-$(CONFIG_SL28CPLD) += sl28cpld.o
+obj-$(CONFIG_SPL_SOCFPGA_DT_REG) += socfpga_dtreg.o
diff --git a/drivers/misc/socfpga_dtreg.c b/drivers/misc/socfpga_dtreg.c
new file mode 100644
index 00..982f9592cb
--- /dev/null
+++ b/drivers/misc/socfpga_dtreg.c
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright
