Re: [RESEND PATCH v1 1/2] dt-bindings: clock: Add Amlogic A1 clock bindings
On Sun, 17 Sept 2023 at 04:14, Igor Prusov wrote: > > Add clock bindings for Amlogic A1 from linux-next next-20230821. > > Signed-off-by: Igor Prusov > --- > .../clock/amlogic,a1-peripherals-clkc.h | 168 ++ > .../dt-bindings/clock/amlogic,a1-pll-clkc.h | 25 +++ > 2 files changed, 193 insertions(+) > create mode 100644 include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h > create mode 100644 include/dt-bindings/clock/amlogic,a1-pll-clkc.h Reviewed-by: Simon Glass
[RESEND PATCH v1 1/2] dt-bindings: clock: Add Amlogic A1 clock bindings
Add clock bindings for Amlogic A1 from linux-next next-20230821. Signed-off-by: Igor Prusov --- .../clock/amlogic,a1-peripherals-clkc.h | 168 ++ .../dt-bindings/clock/amlogic,a1-pll-clkc.h | 25 +++ 2 files changed, 193 insertions(+) create mode 100644 include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h create mode 100644 include/dt-bindings/clock/amlogic,a1-pll-clkc.h diff --git a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h new file mode 100644 index 00..06f198ee76 --- /dev/null +++ b/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h @@ -0,0 +1,168 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + * Author: Jian Hu + * + * Copyright (c) 2023, SberDevices. All Rights Reserved. + * Author: Dmitry Rokosov + */ + +#ifndef __A1_PERIPHERALS_CLKC_H +#define __A1_PERIPHERALS_CLKC_H + +#define CLKID_XTAL_IN 0 +#define CLKID_FIXPLL_IN1 +#define CLKID_USB_PHY_IN 2 +#define CLKID_USB_CTRL_IN 3 +#define CLKID_HIFIPLL_IN 4 +#define CLKID_SYSPLL_IN5 +#define CLKID_DDS_IN 6 +#define CLKID_SYS 7 +#define CLKID_CLKTREE 8 +#define CLKID_RESET_CTRL 9 +#define CLKID_ANALOG_CTRL 10 +#define CLKID_PWR_CTRL 11 +#define CLKID_PAD_CTRL 12 +#define CLKID_SYS_CTRL 13 +#define CLKID_TEMP_SENSOR 14 +#define CLKID_AM2AXI_DIV 15 +#define CLKID_SPICC_B 16 +#define CLKID_SPICC_A 17 +#define CLKID_MSR 18 +#define CLKID_AUDIO19 +#define CLKID_JTAG_CTRL20 +#define CLKID_SARADC_EN21 +#define CLKID_PWM_EF 22 +#define CLKID_PWM_CD 23 +#define CLKID_PWM_AB 24 +#define CLKID_CEC 25 +#define CLKID_I2C_S26 +#define CLKID_IR_CTRL 27 +#define CLKID_I2C_M_D 28 +#define CLKID_I2C_M_C 29 +#define CLKID_I2C_M_B 30 +#define CLKID_I2C_M_A 31 +#define CLKID_ACODEC 32 +#define CLKID_OTP 33 +#define CLKID_SD_EMMC_A34 +#define CLKID_USB_PHY 35 +#define CLKID_USB_CTRL 36 +#define CLKID_SYS_DSPB 37 +#define CLKID_SYS_DSPA 38 +#define CLKID_DMA 39 +#define CLKID_IRQ_CTRL 40 +#define CLKID_NIC 41 +#define CLKID_GIC 42 +#define CLKID_UART_C 43 +#define CLKID_UART_B 44 +#define CLKID_UART_A 45 +#define CLKID_SYS_PSRAM46 +#define CLKID_RSA 47 +#define CLKID_CORESIGHT48 +#define CLKID_AM2AXI_VAD 49 +#define CLKID_AUDIO_VAD50 +#define CLKID_AXI_DMC 51 +#define CLKID_AXI_PSRAM52 +#define CLKID_RAMB 53 +#define CLKID_RAMA 54 +#define CLKID_AXI_SPIFC55 +#define CLKID_AXI_NIC 56 +#define CLKID_AXI_DMA 57 +#define CLKID_CPU_CTRL 58 +#define CLKID_ROM 59 +#define CLKID_PROC_I2C 60 +#define CLKID_DSPA_SEL 61 +#define CLKID_DSPB_SEL 62 +#define CLKID_DSPA_EN 63 +#define CLKID_DSPA_EN_NIC 64 +#define CLKID_DSPB_EN 65 +#define CLKID_DSPB_EN_NIC 66 +#define CLKID_RTC 67 +#define CLKID_CECA_32K 68 +#define CLKID_CECB_32K 69 +#define CLKID_24M 70 +#define CLKID_12M 71 +#define CLKID_FCLK_DIV2_DIVN 72 +#define CLKID_GEN 73 +#define CLKID_SARADC_SEL 74 +#define CLKID_SARADC 75 +#define CLKID_PWM_A76 +#define CLKID_PWM_B77 +#define CLKID_PWM_C78 +#define CLKID_PWM_D79 +#define CLKID_PWM_E80 +#define CLKID_PWM_F81 +#define CLKID_SPICC82 +#define CLKID_TS 83 +#define CLKID_SPIFC84 +#define CLKID_USB_BUS 85 +#define CLKID_SD_EMMC 86 +#define CLKID_PSRAM87 +#define CLKID_DMC 88 +#define CLKID_SYS_A_SEL89 +#define CLKID_SYS_A_DIV90 +#define CLKID_SYS_A91 +#define CLKID_SYS_B_SEL92 +#define CLKID_SYS_B_DIV93 +#define CLKID_SYS_B94 +#define CLKID_DSPA_A_SEL 95 +#define CLKID_DSPA_A_DIV 96 +#define CLKID_DSPA_A 97 +#define CLKID_DSPA_B_SEL 98 +#define CLKID_DSPA_B_DIV 99 +#define CLKID_DSPA_B 100 +#define CLKID_DSPB_A_SEL 101 +#define CLKID_DSPB_A_DIV 102 +#define CLKID_DSPB_A 103 +#define CLKID_DSPB_B_SEL 104 +#define CLKID_DSPB_B_DIV 105 +#define CLKID_DSPB_B 106 +#define CLKID_RTC_32K_IN 107 +#define CLKID_RTC_32K_DIV 108 +#define CLKID_RTC_32K_XTAL 109 +#define CLKID_RTC_32K_SEL 110 +#define
[PATCH v1 1/2] dt-bindings: clock: Add Amlogic A1 clock bindings
Add clock bindings for Amlogic A1 from linux-next next-20230821. Signed-off-by: Igor Prusov --- .../clock/amlogic,a1-peripherals-clkc.h | 168 ++ .../dt-bindings/clock/amlogic,a1-pll-clkc.h | 25 +++ 2 files changed, 193 insertions(+) create mode 100644 include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h create mode 100644 include/dt-bindings/clock/amlogic,a1-pll-clkc.h diff --git a/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h b/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h new file mode 100644 index 00..06f198ee76 --- /dev/null +++ b/include/dt-bindings/clock/amlogic,a1-peripherals-clkc.h @@ -0,0 +1,168 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + * Author: Jian Hu + * + * Copyright (c) 2023, SberDevices. All Rights Reserved. + * Author: Dmitry Rokosov + */ + +#ifndef __A1_PERIPHERALS_CLKC_H +#define __A1_PERIPHERALS_CLKC_H + +#define CLKID_XTAL_IN 0 +#define CLKID_FIXPLL_IN1 +#define CLKID_USB_PHY_IN 2 +#define CLKID_USB_CTRL_IN 3 +#define CLKID_HIFIPLL_IN 4 +#define CLKID_SYSPLL_IN5 +#define CLKID_DDS_IN 6 +#define CLKID_SYS 7 +#define CLKID_CLKTREE 8 +#define CLKID_RESET_CTRL 9 +#define CLKID_ANALOG_CTRL 10 +#define CLKID_PWR_CTRL 11 +#define CLKID_PAD_CTRL 12 +#define CLKID_SYS_CTRL 13 +#define CLKID_TEMP_SENSOR 14 +#define CLKID_AM2AXI_DIV 15 +#define CLKID_SPICC_B 16 +#define CLKID_SPICC_A 17 +#define CLKID_MSR 18 +#define CLKID_AUDIO19 +#define CLKID_JTAG_CTRL20 +#define CLKID_SARADC_EN21 +#define CLKID_PWM_EF 22 +#define CLKID_PWM_CD 23 +#define CLKID_PWM_AB 24 +#define CLKID_CEC 25 +#define CLKID_I2C_S26 +#define CLKID_IR_CTRL 27 +#define CLKID_I2C_M_D 28 +#define CLKID_I2C_M_C 29 +#define CLKID_I2C_M_B 30 +#define CLKID_I2C_M_A 31 +#define CLKID_ACODEC 32 +#define CLKID_OTP 33 +#define CLKID_SD_EMMC_A34 +#define CLKID_USB_PHY 35 +#define CLKID_USB_CTRL 36 +#define CLKID_SYS_DSPB 37 +#define CLKID_SYS_DSPA 38 +#define CLKID_DMA 39 +#define CLKID_IRQ_CTRL 40 +#define CLKID_NIC 41 +#define CLKID_GIC 42 +#define CLKID_UART_C 43 +#define CLKID_UART_B 44 +#define CLKID_UART_A 45 +#define CLKID_SYS_PSRAM46 +#define CLKID_RSA 47 +#define CLKID_CORESIGHT48 +#define CLKID_AM2AXI_VAD 49 +#define CLKID_AUDIO_VAD50 +#define CLKID_AXI_DMC 51 +#define CLKID_AXI_PSRAM52 +#define CLKID_RAMB 53 +#define CLKID_RAMA 54 +#define CLKID_AXI_SPIFC55 +#define CLKID_AXI_NIC 56 +#define CLKID_AXI_DMA 57 +#define CLKID_CPU_CTRL 58 +#define CLKID_ROM 59 +#define CLKID_PROC_I2C 60 +#define CLKID_DSPA_SEL 61 +#define CLKID_DSPB_SEL 62 +#define CLKID_DSPA_EN 63 +#define CLKID_DSPA_EN_NIC 64 +#define CLKID_DSPB_EN 65 +#define CLKID_DSPB_EN_NIC 66 +#define CLKID_RTC 67 +#define CLKID_CECA_32K 68 +#define CLKID_CECB_32K 69 +#define CLKID_24M 70 +#define CLKID_12M 71 +#define CLKID_FCLK_DIV2_DIVN 72 +#define CLKID_GEN 73 +#define CLKID_SARADC_SEL 74 +#define CLKID_SARADC 75 +#define CLKID_PWM_A76 +#define CLKID_PWM_B77 +#define CLKID_PWM_C78 +#define CLKID_PWM_D79 +#define CLKID_PWM_E80 +#define CLKID_PWM_F81 +#define CLKID_SPICC82 +#define CLKID_TS 83 +#define CLKID_SPIFC84 +#define CLKID_USB_BUS 85 +#define CLKID_SD_EMMC 86 +#define CLKID_PSRAM87 +#define CLKID_DMC 88 +#define CLKID_SYS_A_SEL89 +#define CLKID_SYS_A_DIV90 +#define CLKID_SYS_A91 +#define CLKID_SYS_B_SEL92 +#define CLKID_SYS_B_DIV93 +#define CLKID_SYS_B94 +#define CLKID_DSPA_A_SEL 95 +#define CLKID_DSPA_A_DIV 96 +#define CLKID_DSPA_A 97 +#define CLKID_DSPA_B_SEL 98 +#define CLKID_DSPA_B_DIV 99 +#define CLKID_DSPA_B 100 +#define CLKID_DSPB_A_SEL 101 +#define CLKID_DSPB_A_DIV 102 +#define CLKID_DSPB_A 103 +#define CLKID_DSPB_B_SEL 104 +#define CLKID_DSPB_B_DIV 105 +#define CLKID_DSPB_B 106 +#define CLKID_RTC_32K_IN 107 +#define CLKID_RTC_32K_DIV 108 +#define CLKID_RTC_32K_XTAL 109 +#define CLKID_RTC_32K_SEL 110 +#define
