Re: [PATCH v12] driver: spi: add bcm iproc qspi support

2022-02-24 Thread Jagan Teki
On Thu, Feb 10, 2022 at 3:46 AM Roman Bacik  wrote:
>
> From: Rayagonda Kokatanur 
>
> IPROC qspi driver supports both BSPI and MSPI modes.
>
> Signed-off-by: Rayagonda Kokatanur 
> Signed-off-by: Bharat Gooty 
> Acked-by: Rayagonda Kokatanur 
>
> Signed-off-by: Roman Bacik 
> ---

Applied to u-boot-spi/master


[PATCH v12] driver: spi: add bcm iproc qspi support

2022-02-09 Thread Roman Bacik
From: Rayagonda Kokatanur 

IPROC qspi driver supports both BSPI and MSPI modes.

Signed-off-by: Rayagonda Kokatanur 
Signed-off-by: Bharat Gooty 
Acked-by: Rayagonda Kokatanur 

Signed-off-by: Roman Bacik 
---

Changes in v12:
- fix typo FLASH_BIT to FLUSH_BIT
- return -EBUSY instead of -1 from bspi_disable
- replace (bytes+3)/4 with macro CEIL(bytes,4)
- replace constants with macros
- remove misleading comment
- remove debug instructions
- replace void __iomem * with fdt_addr_t

Changes in v11:
- fix condition for readl_poll_timeout in bspi_read_via_raf

Changes in v10:
- remove binding document
- use defined values for delays and timeouts
- replace timer-based logic with readl_poll_timeout
- format selected commands to single line
- remove unnecessary entries from struct bcmspi_priv
- simplify and move bspi strap override to bspi_set_flex_mode

Changes in v9:
- merge bspi_set_4byte_mode to bspi_set_flex_mode
- simplify bspi_set_flex_mode using data from spi_mem_op
- rename mode_4byte to bspi_4byte
- use BIT(x) istead of 1cmd.opcode for BSPI_CMD_AND_MODE_BYTE_REG
- move iproc_qspi.c to spi

Changes in v4:
- move iproc_qspi.c from spi to mtd/spi
- remove iproc_qspi.h
- rename IPROC_QSPI to SPI_FLASH_IPROC

Changes in v3:
- fix warning by including linux/delay.h
- change ofdata_to_platdata to of_to_plat
- change priv_auto_alloc_size to priv_auto

Changes in v2:
- remove include spi-nor.h
- define and use named BITs for writing register values
- remove bspi_set_4byte_mode() method

 drivers/spi/Kconfig  |   6 +
 drivers/spi/Makefile |   1 +
 drivers/spi/iproc_qspi.c | 576 +++
 3 files changed, 583 insertions(+)
 create mode 100644 drivers/spi/iproc_qspi.c

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index d07e9a28af82..faebc212753e 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -178,6 +178,12 @@ config ICH_SPI
  access the SPI NOR flash on platforms embedding this Intel
  ICH IP core.
 
+config IPROC_QSPI
+   bool "Broadcom iProc QSPI Flash Controller driver"
+   help
+ Enable Broadcom iProc QSPI Flash Controller driver.
+ This driver can be used to access the SPI NOR flash.
+
 config KIRKWOOD_SPI
bool "Marvell Kirkwood SPI Driver"
help
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index d2f24bccefd3..869763187062 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -33,6 +33,7 @@ obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
 obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
 obj-$(CONFIG_SYNQUACER_SPI) += spi-synquacer.o
 obj-$(CONFIG_ICH_SPI) +=  ich.o
+obj-$(CONFIG_IPROC_QSPI) += iproc_qspi.o
 obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
 obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o
 obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
diff --git a/drivers/spi/iproc_qspi.c b/drivers/spi/iproc_qspi.c
new file mode 100644
index ..b5c274314b5b
--- /dev/null
+++ b/drivers/spi/iproc_qspi.c
@@ -0,0 +1,576 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2020-2021 Broadcom
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Delay required to change the mode of operation */
+#define BUSY_DELAY_US  1
+#define BUSY_TIMEOUT_US20
+#define DWORD_ALIGNED(a)   (!(((ulong)(a)) & 3))
+
+/* Chip attributes */
+#define QSPI_AXI_CLK   17500
+#define SPBR_MIN   8U
+#define SPBR_MAX   255U
+#define NUM_CDRAM  16U
+
+#define CDRAM_PCS0 2
+#define CDRAM_CONT BIT(7)
+#define CDRAM_BITS_EN  BIT(6)
+#define CDRAM_QUAD_MODEBIT(8)
+#define CDRAM_RBIT_INPUT   BIT(10)
+#define MSPI_SPE   BIT(6)
+#define MSPI_CONT_AFTER_CMDBIT(7)
+#define MSPI_MSTR  BIT(7)
+
+/* Register fields */
+#define MSPI_SPCR0_MSB_BITS_8  0x0020
+#define BSPI_RAF_CONTROL_START_MASK0x0001
+#define BSPI_RAF_STATUS_SESSION_BUSY_MASK  0x0001
+#define BSPI_RAF_STATUS_FIFO_EMPTY_MASK0x0002
+#define BSPI_STRAP_OVERRIDE_DATA_QUAD_SHIFT3
+#define BSPI_STRAP_OVERRIDE_4BYTE_SHIFT2
+#define BSPI_STRAP_OVERRIDE_DATA_DUAL_SHIFT1
+#define BSPI_STRAP_OVERRIDE_SHIFT  0
+#define BSPI_BPC_DATA_SHIFT0
+#define BSPI_BPC_MODE_SHIFT8
+#define BSPI_BPC_ADDR_SHIFT16
+#define BSPI_BPC_CMD_SHIFT 24
+#define BSPI_BPP_ADDR_SHIFT16
+
+/* MSPI registers */
+#define