Re: [PATCH v2 1/3] starfive: pci: Add StarFive JH7110 pcie driver
On Wed, Mar 8, 2023 at 1:49 PM Minda Chen wrote:
>
> From: Mason Huo
>
> Add pcie driver for StarFive JH7110, the driver depends on
> starfive gpio, pinctrl, clk and reset driver to do init.
>
> Several devices are tested:
> a) M.2 NVMe SSD
> b) Realtek 8169 Ethernet adapter.
>
> Signed-off-by: Mason Huo
> Signed-off-by: Minda Chen
> ---
> drivers/pci/Kconfig| 11 +
> drivers/pci/Makefile | 1 +
> drivers/pci/pcie_starfive_jh7110.c | 478 +
> 3 files changed, 490 insertions(+)
> create mode 100644 drivers/pci/pcie_starfive_jh7110.c
>
> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
> index ef328d2652..e7b0ff5bc3 100644
> --- a/drivers/pci/Kconfig
> +++ b/drivers/pci/Kconfig
> @@ -374,4 +374,15 @@ config PCIE_UNIPHIER
> Say Y here if you want to enable PCIe controller support on
> UniPhier SoCs.
>
> +config PCIE_STARFIVE_JH7110
> + bool "Enable Starfive JH7110 PCIe driver"
> + depends on STARFIVE_JH7110
> + depends on PINCTRL_STARFIVE_JH7110
> + depends on CLK_JH7110
> + depends on RESET_JH7110
> + default y
> + help
> + Say Y here if you want to enable PCIe controller support on
> + StarFive JH7110 SoC.
> +
> endif
> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
> index 49506e7ba5..bbe3323bb5 100644
> --- a/drivers/pci/Makefile
> +++ b/drivers/pci/Makefile
> @@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
> obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
> obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
> obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
> +obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
> diff --git a/drivers/pci/pcie_starfive_jh7110.c
> b/drivers/pci/pcie_starfive_jh7110.c
> new file mode 100644
> index 00..5ccef1ef02
> --- /dev/null
> +++ b/drivers/pci/pcie_starfive_jh7110.c
> @@ -0,0 +1,478 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * StarFive PLDA PCIe host controller driver
> + *
> + * Copyright (c) 2023 Starfive, Inc.
> + * Author: Mason Huo
> + *
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define GEN_SETTINGS 0x80
> +#define PCIE_PCI_IDS 0x9C
> +#define PCIE_WINROM0xFC
> +#define PMSG_SUPPORT_RX0x3F0
> +#define PCI_MISC 0xB4
> +
> +#define PLDA_EP_ENABLE 0
> +#define PLDA_RP_ENABLE 1
> +
> +#define IDS_REVISION_ID0x02
> +#define IDS_PCI_TO_PCI_BRIDGE 0x060400
> +#define IDS_CLASS_CODE_SHIFT 8
> +
> +#define PREF_MEM_WIN_64_SUPPORTBIT(3)
> +#define PMSG_LTR_SUPPORT BIT(2)
> +#define PLDA_FUNCTION_DIS BIT(15)
> +#define PLDA_FUNC_NUM 4
> +#define PLDA_PHY_FUNC_SHIFT9
> +
> +#define XR3PCI_ATR_AXI4_SLV0 0x800
> +#define XR3PCI_ATR_SRC_ADDR_LOW0x0
> +#define XR3PCI_ATR_SRC_ADDR_HIGH 0x4
> +#define XR3PCI_ATR_TRSL_ADDR_LOW 0x8
> +#define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc
> +#define XR3PCI_ATR_TRSL_PARAM 0x10
> +#define XR3PCI_ATR_TABLE_OFFSET0x20
> +#define XR3PCI_ATR_MAX_TABLE_NUM 8
> +
> +#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT 1
> +#define XR3PCI_ATR_SRC_ADDR_MASK GENMASK(31, 12)
> +#define XR3PCI_ATR_TRSL_ADDR_MASK GENMASK(31, 12)
> +#define XR3_PCI_ECAM_SIZE 28
> +#define XR3PCI_ATR_TRSL_DIRBIT(22)
> +/* IDs used in the XR3PCI_ATR_TRSL_PARAM */
> +#define XR3PCI_ATR_TRSLID_PCIE_MEMORY 0x0
> +#define XR3PCI_ATR_TRSLID_PCIE_CONFIG 0x1
> +
> +#define ECAM_BUS_SHIFT 20
> +#define ECAM_DEV_SHIFT 15
> +#define ECAM_FUNC_SHIFT12
> +/* Secondary bus number offset in config space */
> +#define PCI_SECONDARY_BUS 0x19
> +
> +/* system control */
> +#define STG_SYSCON_K_RP_NEP_MASK BIT(8)
> +#define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK GENMASK(22, 8)
> +#define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT 8
> +#define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK GENMASK(14, 0)
> +#define STG_SYSCON_CLKREQ_MASK BIT(22)
> +#define STG_SYSCON_CKREF_SRC_SHIFT 18
> +#define STG_SYSCON_CKREF_SRC_MASK GENMASK(19, 18)
> +
> +struct starfive_pcie {
> + struct udevice *dev;
> +
> + void __iomem *reg_base;
> + void __iomem *cfg_base;
> +
> + struct regmap *regmap;
> + u32 stg_arfun;
> + u32 stg_awfun;
> + u32 stg_rp_nep;
> +
> + struct clk_bulk clks;
> + struct reset_ctl_bulk rsts;
> +
> + int atr_table_num;
> + int first_busno;
> +};
> +
>
Re: [PATCH v2 1/3] starfive: pci: Add StarFive JH7110 pcie driver
On Monday 27 March 2023 09:03:46 Minda Chen wrote: > > > On 2023/3/25 20:31, Pali Rohár wrote: > > On Friday 24 March 2023 18:57:33 Minda Chen wrote: > >> On 2023/3/24 2:19, Pali Rohár wrote: > >> > On Thursday 23 March 2023 18:51:38 Minda Chen wrote: > >> >> On 2023/3/11 1:42, Pali Rohár wrote: > >> >> > On Friday 10 March 2023 18:36:44 Minda Chen wrote: > >> >> >> On 2023/3/8 15:31, Pali Rohár wrote: > >> >> >> > Hello! See few comments below. > >> >> >> > > >> >> >> > On Wednesday 08 March 2023 13:48:31 Minda Chen wrote: > >> >> >> >> From: Mason Huo > >> >> >> >> > >> >> >> >> Add pcie driver for StarFive JH7110, the driver depends on > >> >> >> >> starfive gpio, pinctrl, clk and reset driver to do init. > >> >> >> >> > >> >> >> >> Several devices are tested: > >> >> >> >> a) M.2 NVMe SSD > >> >> >> >> b) Realtek 8169 Ethernet adapter. > >> >> >> >> > >> >> >> >> Signed-off-by: Mason Huo > >> >> >> >> Signed-off-by: Minda Chen > >> >> >> >> --- > >> >> >> >> drivers/pci/Kconfig| 11 + > >> >> >> >> drivers/pci/Makefile | 1 + > >> >> >> >> drivers/pci/pcie_starfive_jh7110.c | 478 > >> >> >> >> + > >> >> >> >> 3 files changed, 490 insertions(+) > >> >> >> >> create mode 100644 drivers/pci/pcie_starfive_jh7110.c > >> >> >> >> > >> >> >> >> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig > >> >> >> >> index ef328d2652..e7b0ff5bc3 100644 > >> >> >> >> --- a/drivers/pci/Kconfig > >> >> >> >> +++ b/drivers/pci/Kconfig > >> >> >> >> @@ -374,4 +374,15 @@ config PCIE_UNIPHIER > >> >> >> >> Say Y here if you want to enable PCIe controller support on > >> >> >> >> UniPhier SoCs. > >> >> >> >> > >> >> >> >> +config PCIE_STARFIVE_JH7110 > >> >> >> >> + bool "Enable Starfive JH7110 PCIe driver" > >> >> >> >> + depends on STARFIVE_JH7110 > >> >> >> >> + depends on PINCTRL_STARFIVE_JH7110 > >> >> >> >> + depends on CLK_JH7110 > >> >> >> >> + depends on RESET_JH7110 > >> >> >> >> + default y > >> >> >> >> + help > >> >> >> >> + Say Y here if you want to enable PCIe controller support on > >> >> >> >> + StarFive JH7110 SoC. > >> >> >> >> + > >> >> >> >> endif > >> >> >> >> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile > >> >> >> >> index 49506e7ba5..bbe3323bb5 100644 > >> >> >> >> --- a/drivers/pci/Makefile > >> >> >> >> +++ b/drivers/pci/Makefile > >> >> >> >> @@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o > >> >> >> >> obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o > >> >> >> >> obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o > >> >> >> >> obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o > >> >> >> >> +obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o > >> >> >> >> diff --git a/drivers/pci/pcie_starfive_jh7110.c > >> >> >> >> b/drivers/pci/pcie_starfive_jh7110.c > >> >> >> >> new file mode 100644 > >> >> >> >> index 00..5ccef1ef02 > >> >> >> >> --- /dev/null > >> >> >> >> +++ b/drivers/pci/pcie_starfive_jh7110.c > >> >> >> >> @@ -0,0 +1,478 @@ > >> >> >> >> +// SPDX-License-Identifier: GPL-2.0+ > >> >> >> >> +/* > >> >> >> >> + * StarFive PLDA PCIe host controller driver > >> >> >> >> + * > >> >> >> >> + * Copyright (c) 2023 Starfive, Inc. > >> >> >> >> + * Author: Mason Huo > >> >> >> >> + * > >> >> >> >> + */ > >> >> >> >> + > >> >> >> >> +#include > >> >> >> >> +#include > >> >> >> >> +#include > >> >> >> >> +#include > >> >> >> >> +#include > >> >> >> >> +#include > >> >> >> >> +#include > >> >> >> >> +#include > >> >> >> >> +#include > >> >> >> >> +#include > >> >> >> >> +#include > >> >> >> >> +#include > >> >> >> >> +#include > >> >> >> >> +#include > >> >> >> >> +#include > >> >> >> >> +#include > >> >> >> >> +#include > >> >> >> >> + > >> >> >> >> +DECLARE_GLOBAL_DATA_PTR; > >> >> >> >> + > >> >> >> >> +#define GEN_SETTINGS 0x80 > >> >> >> >> +#define PCIE_PCI_IDS 0x9C > >> >> >> >> +#define PCIE_WINROM 0xFC > >> >> >> >> +#define PMSG_SUPPORT_RX 0x3F0 > >> >> >> >> +#define PCI_MISC 0xB4 > >> >> >> >> + > >> >> >> >> +#define PLDA_EP_ENABLE 0 > >> >> >> >> +#define PLDA_RP_ENABLE 1 > >> >> >> >> + > >> >> >> >> +#define IDS_REVISION_ID 0x02 > >> >> >> >> +#define IDS_PCI_TO_PCI_BRIDGE0x060400 > >> >> >> >> +#define IDS_CLASS_CODE_SHIFT 8 > >> >> >> > > >> >> >> > Please do not duplicate standard PCI macros and constants. In > >> >> >> > U-Boot > >> >> >> > they are already available in include/pci_ids.h header file. > >> >> >> > > >> >> >> ok > >> >> >> >> +#define PREF_MEM_WIN_64_SUPPORT BIT(3) > >> >> >> >> +#define PMSG_LTR_SUPPORT BIT(2) > >> >> >> >> +#define PLDA_FUNCTION_DISBIT(15) > >> >> >> >> +#define PLDA_FUNC_NUM4 > >> >> >> >> +#define PLDA_PHY_FUNC_SHIFT 9 > >> >> >> >> + > >> >> >> >> +#define
Re: [PATCH v2 1/3] starfive: pci: Add StarFive JH7110 pcie driver
On 2023/3/25 20:31, Pali Rohár wrote: > On Friday 24 March 2023 18:57:33 Minda Chen wrote: >> On 2023/3/24 2:19, Pali Rohár wrote: >> > On Thursday 23 March 2023 18:51:38 Minda Chen wrote: >> >> On 2023/3/11 1:42, Pali Rohár wrote: >> >> > On Friday 10 March 2023 18:36:44 Minda Chen wrote: >> >> >> On 2023/3/8 15:31, Pali Rohár wrote: >> >> >> > Hello! See few comments below. >> >> >> > >> >> >> > On Wednesday 08 March 2023 13:48:31 Minda Chen wrote: >> >> >> >> From: Mason Huo >> >> >> >> >> >> >> >> Add pcie driver for StarFive JH7110, the driver depends on >> >> >> >> starfive gpio, pinctrl, clk and reset driver to do init. >> >> >> >> >> >> >> >> Several devices are tested: >> >> >> >> a) M.2 NVMe SSD >> >> >> >> b) Realtek 8169 Ethernet adapter. >> >> >> >> >> >> >> >> Signed-off-by: Mason Huo >> >> >> >> Signed-off-by: Minda Chen >> >> >> >> --- >> >> >> >> drivers/pci/Kconfig| 11 + >> >> >> >> drivers/pci/Makefile | 1 + >> >> >> >> drivers/pci/pcie_starfive_jh7110.c | 478 >> >> >> >> + >> >> >> >> 3 files changed, 490 insertions(+) >> >> >> >> create mode 100644 drivers/pci/pcie_starfive_jh7110.c >> >> >> >> >> >> >> >> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig >> >> >> >> index ef328d2652..e7b0ff5bc3 100644 >> >> >> >> --- a/drivers/pci/Kconfig >> >> >> >> +++ b/drivers/pci/Kconfig >> >> >> >> @@ -374,4 +374,15 @@ config PCIE_UNIPHIER >> >> >> >> Say Y here if you want to enable PCIe controller support on >> >> >> >> UniPhier SoCs. >> >> >> >> >> >> >> >> +config PCIE_STARFIVE_JH7110 >> >> >> >> + bool "Enable Starfive JH7110 PCIe driver" >> >> >> >> + depends on STARFIVE_JH7110 >> >> >> >> + depends on PINCTRL_STARFIVE_JH7110 >> >> >> >> + depends on CLK_JH7110 >> >> >> >> + depends on RESET_JH7110 >> >> >> >> + default y >> >> >> >> + help >> >> >> >> + Say Y here if you want to enable PCIe controller support on >> >> >> >> + StarFive JH7110 SoC. >> >> >> >> + >> >> >> >> endif >> >> >> >> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile >> >> >> >> index 49506e7ba5..bbe3323bb5 100644 >> >> >> >> --- a/drivers/pci/Makefile >> >> >> >> +++ b/drivers/pci/Makefile >> >> >> >> @@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o >> >> >> >> obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o >> >> >> >> obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o >> >> >> >> obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o >> >> >> >> +obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o >> >> >> >> diff --git a/drivers/pci/pcie_starfive_jh7110.c >> >> >> >> b/drivers/pci/pcie_starfive_jh7110.c >> >> >> >> new file mode 100644 >> >> >> >> index 00..5ccef1ef02 >> >> >> >> --- /dev/null >> >> >> >> +++ b/drivers/pci/pcie_starfive_jh7110.c >> >> >> >> @@ -0,0 +1,478 @@ >> >> >> >> +// SPDX-License-Identifier: GPL-2.0+ >> >> >> >> +/* >> >> >> >> + * StarFive PLDA PCIe host controller driver >> >> >> >> + * >> >> >> >> + * Copyright (c) 2023 Starfive, Inc. >> >> >> >> + * Author: Mason Huo >> >> >> >> + * >> >> >> >> + */ >> >> >> >> + >> >> >> >> +#include >> >> >> >> +#include >> >> >> >> +#include >> >> >> >> +#include >> >> >> >> +#include >> >> >> >> +#include >> >> >> >> +#include >> >> >> >> +#include >> >> >> >> +#include >> >> >> >> +#include >> >> >> >> +#include >> >> >> >> +#include >> >> >> >> +#include >> >> >> >> +#include >> >> >> >> +#include >> >> >> >> +#include >> >> >> >> +#include >> >> >> >> + >> >> >> >> +DECLARE_GLOBAL_DATA_PTR; >> >> >> >> + >> >> >> >> +#define GEN_SETTINGS 0x80 >> >> >> >> +#define PCIE_PCI_IDS 0x9C >> >> >> >> +#define PCIE_WINROM0xFC >> >> >> >> +#define PMSG_SUPPORT_RX0x3F0 >> >> >> >> +#define PCI_MISC 0xB4 >> >> >> >> + >> >> >> >> +#define PLDA_EP_ENABLE 0 >> >> >> >> +#define PLDA_RP_ENABLE 1 >> >> >> >> + >> >> >> >> +#define IDS_REVISION_ID0x02 >> >> >> >> +#define IDS_PCI_TO_PCI_BRIDGE 0x060400 >> >> >> >> +#define IDS_CLASS_CODE_SHIFT 8 >> >> >> > >> >> >> > Please do not duplicate standard PCI macros and constants. In U-Boot >> >> >> > they are already available in include/pci_ids.h header file. >> >> >> > >> >> >> ok >> >> >> >> +#define PREF_MEM_WIN_64_SUPPORTBIT(3) >> >> >> >> +#define PMSG_LTR_SUPPORT BIT(2) >> >> >> >> +#define PLDA_FUNCTION_DIS BIT(15) >> >> >> >> +#define PLDA_FUNC_NUM 4 >> >> >> >> +#define PLDA_PHY_FUNC_SHIFT9 >> >> >> >> + >> >> >> >> +#define XR3PCI_ATR_AXI4_SLV0 0x800 >> >> >> >> +#define XR3PCI_ATR_SRC_ADDR_LOW0x0 >> >> >> >> +#define XR3PCI_ATR_SRC_ADDR_HIGH 0x4 >> >> >> >> +#define XR3PCI_ATR_TRSL_ADDR_LOW 0x8 >> >> >> >> +#define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc >> >> >>
Re: [PATCH v2 1/3] starfive: pci: Add StarFive JH7110 pcie driver
On Friday 24 March 2023 18:57:33 Minda Chen wrote: > On 2023/3/24 2:19, Pali Rohár wrote: > > On Thursday 23 March 2023 18:51:38 Minda Chen wrote: > >> On 2023/3/11 1:42, Pali Rohár wrote: > >> > On Friday 10 March 2023 18:36:44 Minda Chen wrote: > >> >> On 2023/3/8 15:31, Pali Rohár wrote: > >> >> > Hello! See few comments below. > >> >> > > >> >> > On Wednesday 08 March 2023 13:48:31 Minda Chen wrote: > >> >> >> From: Mason Huo > >> >> >> > >> >> >> Add pcie driver for StarFive JH7110, the driver depends on > >> >> >> starfive gpio, pinctrl, clk and reset driver to do init. > >> >> >> > >> >> >> Several devices are tested: > >> >> >> a) M.2 NVMe SSD > >> >> >> b) Realtek 8169 Ethernet adapter. > >> >> >> > >> >> >> Signed-off-by: Mason Huo > >> >> >> Signed-off-by: Minda Chen > >> >> >> --- > >> >> >> drivers/pci/Kconfig| 11 + > >> >> >> drivers/pci/Makefile | 1 + > >> >> >> drivers/pci/pcie_starfive_jh7110.c | 478 > >> >> >> + > >> >> >> 3 files changed, 490 insertions(+) > >> >> >> create mode 100644 drivers/pci/pcie_starfive_jh7110.c > >> >> >> > >> >> >> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig > >> >> >> index ef328d2652..e7b0ff5bc3 100644 > >> >> >> --- a/drivers/pci/Kconfig > >> >> >> +++ b/drivers/pci/Kconfig > >> >> >> @@ -374,4 +374,15 @@ config PCIE_UNIPHIER > >> >> >>Say Y here if you want to enable PCIe controller support on > >> >> >>UniPhier SoCs. > >> >> >> > >> >> >> +config PCIE_STARFIVE_JH7110 > >> >> >> +bool "Enable Starfive JH7110 PCIe driver" > >> >> >> +depends on STARFIVE_JH7110 > >> >> >> +depends on PINCTRL_STARFIVE_JH7110 > >> >> >> +depends on CLK_JH7110 > >> >> >> +depends on RESET_JH7110 > >> >> >> +default y > >> >> >> +help > >> >> >> + Say Y here if you want to enable PCIe controller support on > >> >> >> + StarFive JH7110 SoC. > >> >> >> + > >> >> >> endif > >> >> >> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile > >> >> >> index 49506e7ba5..bbe3323bb5 100644 > >> >> >> --- a/drivers/pci/Makefile > >> >> >> +++ b/drivers/pci/Makefile > >> >> >> @@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o > >> >> >> obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o > >> >> >> obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o > >> >> >> obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o > >> >> >> +obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o > >> >> >> diff --git a/drivers/pci/pcie_starfive_jh7110.c > >> >> >> b/drivers/pci/pcie_starfive_jh7110.c > >> >> >> new file mode 100644 > >> >> >> index 00..5ccef1ef02 > >> >> >> --- /dev/null > >> >> >> +++ b/drivers/pci/pcie_starfive_jh7110.c > >> >> >> @@ -0,0 +1,478 @@ > >> >> >> +// SPDX-License-Identifier: GPL-2.0+ > >> >> >> +/* > >> >> >> + * StarFive PLDA PCIe host controller driver > >> >> >> + * > >> >> >> + * Copyright (c) 2023 Starfive, Inc. > >> >> >> + * Author: Mason Huo > >> >> >> + * > >> >> >> + */ > >> >> >> + > >> >> >> +#include > >> >> >> +#include > >> >> >> +#include > >> >> >> +#include > >> >> >> +#include > >> >> >> +#include > >> >> >> +#include > >> >> >> +#include > >> >> >> +#include > >> >> >> +#include > >> >> >> +#include > >> >> >> +#include > >> >> >> +#include > >> >> >> +#include > >> >> >> +#include > >> >> >> +#include > >> >> >> +#include > >> >> >> + > >> >> >> +DECLARE_GLOBAL_DATA_PTR; > >> >> >> + > >> >> >> +#define GEN_SETTINGS0x80 > >> >> >> +#define PCIE_PCI_IDS0x9C > >> >> >> +#define PCIE_WINROM 0xFC > >> >> >> +#define PMSG_SUPPORT_RX 0x3F0 > >> >> >> +#define PCI_MISC0xB4 > >> >> >> + > >> >> >> +#define PLDA_EP_ENABLE 0 > >> >> >> +#define PLDA_RP_ENABLE 1 > >> >> >> + > >> >> >> +#define IDS_REVISION_ID 0x02 > >> >> >> +#define IDS_PCI_TO_PCI_BRIDGE 0x060400 > >> >> >> +#define IDS_CLASS_CODE_SHIFT8 > >> >> > > >> >> > Please do not duplicate standard PCI macros and constants. In U-Boot > >> >> > they are already available in include/pci_ids.h header file. > >> >> > > >> >> ok > >> >> >> +#define PREF_MEM_WIN_64_SUPPORT BIT(3) > >> >> >> +#define PMSG_LTR_SUPPORTBIT(2) > >> >> >> +#define PLDA_FUNCTION_DIS BIT(15) > >> >> >> +#define PLDA_FUNC_NUM 4 > >> >> >> +#define PLDA_PHY_FUNC_SHIFT 9 > >> >> >> + > >> >> >> +#define XR3PCI_ATR_AXI4_SLV00x800 > >> >> >> +#define XR3PCI_ATR_SRC_ADDR_LOW 0x0 > >> >> >> +#define XR3PCI_ATR_SRC_ADDR_HIGH0x4 > >> >> >> +#define XR3PCI_ATR_TRSL_ADDR_LOW0x8 > >> >> >> +#define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc > >> >> >> +#define XR3PCI_ATR_TRSL_PARAM 0x10 > >> >> >> +#define XR3PCI_ATR_TABLE_OFFSET 0x20 > >> >> >> +#define
Re: [PATCH v2 1/3] starfive: pci: Add StarFive JH7110 pcie driver
On 2023/3/24 2:19, Pali Rohár wrote: > On Thursday 23 March 2023 18:51:38 Minda Chen wrote: >> On 2023/3/11 1:42, Pali Rohár wrote: >> > On Friday 10 March 2023 18:36:44 Minda Chen wrote: >> >> On 2023/3/8 15:31, Pali Rohár wrote: >> >> > Hello! See few comments below. >> >> > >> >> > On Wednesday 08 March 2023 13:48:31 Minda Chen wrote: >> >> >> From: Mason Huo >> >> >> >> >> >> Add pcie driver for StarFive JH7110, the driver depends on >> >> >> starfive gpio, pinctrl, clk and reset driver to do init. >> >> >> >> >> >> Several devices are tested: >> >> >> a) M.2 NVMe SSD >> >> >> b) Realtek 8169 Ethernet adapter. >> >> >> >> >> >> Signed-off-by: Mason Huo >> >> >> Signed-off-by: Minda Chen >> >> >> --- >> >> >> drivers/pci/Kconfig| 11 + >> >> >> drivers/pci/Makefile | 1 + >> >> >> drivers/pci/pcie_starfive_jh7110.c | 478 + >> >> >> 3 files changed, 490 insertions(+) >> >> >> create mode 100644 drivers/pci/pcie_starfive_jh7110.c >> >> >> >> >> >> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig >> >> >> index ef328d2652..e7b0ff5bc3 100644 >> >> >> --- a/drivers/pci/Kconfig >> >> >> +++ b/drivers/pci/Kconfig >> >> >> @@ -374,4 +374,15 @@ config PCIE_UNIPHIER >> >> >> Say Y here if you want to enable PCIe controller support on >> >> >> UniPhier SoCs. >> >> >> >> >> >> +config PCIE_STARFIVE_JH7110 >> >> >> + bool "Enable Starfive JH7110 PCIe driver" >> >> >> + depends on STARFIVE_JH7110 >> >> >> + depends on PINCTRL_STARFIVE_JH7110 >> >> >> + depends on CLK_JH7110 >> >> >> + depends on RESET_JH7110 >> >> >> + default y >> >> >> + help >> >> >> +Say Y here if you want to enable PCIe controller support on >> >> >> +StarFive JH7110 SoC. >> >> >> + >> >> >> endif >> >> >> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile >> >> >> index 49506e7ba5..bbe3323bb5 100644 >> >> >> --- a/drivers/pci/Makefile >> >> >> +++ b/drivers/pci/Makefile >> >> >> @@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o >> >> >> obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o >> >> >> obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o >> >> >> obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o >> >> >> +obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o >> >> >> diff --git a/drivers/pci/pcie_starfive_jh7110.c >> >> >> b/drivers/pci/pcie_starfive_jh7110.c >> >> >> new file mode 100644 >> >> >> index 00..5ccef1ef02 >> >> >> --- /dev/null >> >> >> +++ b/drivers/pci/pcie_starfive_jh7110.c >> >> >> @@ -0,0 +1,478 @@ >> >> >> +// SPDX-License-Identifier: GPL-2.0+ >> >> >> +/* >> >> >> + * StarFive PLDA PCIe host controller driver >> >> >> + * >> >> >> + * Copyright (c) 2023 Starfive, Inc. >> >> >> + * Author: Mason Huo >> >> >> + * >> >> >> + */ >> >> >> + >> >> >> +#include >> >> >> +#include >> >> >> +#include >> >> >> +#include >> >> >> +#include >> >> >> +#include >> >> >> +#include >> >> >> +#include >> >> >> +#include >> >> >> +#include >> >> >> +#include >> >> >> +#include >> >> >> +#include >> >> >> +#include >> >> >> +#include >> >> >> +#include >> >> >> +#include >> >> >> + >> >> >> +DECLARE_GLOBAL_DATA_PTR; >> >> >> + >> >> >> +#define GEN_SETTINGS 0x80 >> >> >> +#define PCIE_PCI_IDS 0x9C >> >> >> +#define PCIE_WINROM 0xFC >> >> >> +#define PMSG_SUPPORT_RX 0x3F0 >> >> >> +#define PCI_MISC 0xB4 >> >> >> + >> >> >> +#define PLDA_EP_ENABLE0 >> >> >> +#define PLDA_RP_ENABLE1 >> >> >> + >> >> >> +#define IDS_REVISION_ID 0x02 >> >> >> +#define IDS_PCI_TO_PCI_BRIDGE 0x060400 >> >> >> +#define IDS_CLASS_CODE_SHIFT 8 >> >> > >> >> > Please do not duplicate standard PCI macros and constants. In U-Boot >> >> > they are already available in include/pci_ids.h header file. >> >> > >> >> ok >> >> >> +#define PREF_MEM_WIN_64_SUPPORT BIT(3) >> >> >> +#define PMSG_LTR_SUPPORT BIT(2) >> >> >> +#define PLDA_FUNCTION_DIS BIT(15) >> >> >> +#define PLDA_FUNC_NUM 4 >> >> >> +#define PLDA_PHY_FUNC_SHIFT 9 >> >> >> + >> >> >> +#define XR3PCI_ATR_AXI4_SLV0 0x800 >> >> >> +#define XR3PCI_ATR_SRC_ADDR_LOW 0x0 >> >> >> +#define XR3PCI_ATR_SRC_ADDR_HIGH 0x4 >> >> >> +#define XR3PCI_ATR_TRSL_ADDR_LOW 0x8 >> >> >> +#define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc >> >> >> +#define XR3PCI_ATR_TRSL_PARAM 0x10 >> >> >> +#define XR3PCI_ATR_TABLE_OFFSET 0x20 >> >> >> +#define XR3PCI_ATR_MAX_TABLE_NUM 8 >> >> >> + >> >> >> +#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT 1 >> >> >> +#define XR3PCI_ATR_SRC_ADDR_MASK GENMASK(31, 12) >> >> >> +#define XR3PCI_ATR_TRSL_ADDR_MASK GENMASK(31, 12) >> >> >> +#define XR3_PCI_ECAM_SIZE 28 >> >> >> +#define XR3PCI_ATR_TRSL_DIR
Re: [PATCH v2 1/3] starfive: pci: Add StarFive JH7110 pcie driver
On Thursday 23 March 2023 18:51:38 Minda Chen wrote: > On 2023/3/11 1:42, Pali Rohár wrote: > > On Friday 10 March 2023 18:36:44 Minda Chen wrote: > >> On 2023/3/8 15:31, Pali Rohár wrote: > >> > Hello! See few comments below. > >> > > >> > On Wednesday 08 March 2023 13:48:31 Minda Chen wrote: > >> >> From: Mason Huo > >> >> > >> >> Add pcie driver for StarFive JH7110, the driver depends on > >> >> starfive gpio, pinctrl, clk and reset driver to do init. > >> >> > >> >> Several devices are tested: > >> >> a) M.2 NVMe SSD > >> >> b) Realtek 8169 Ethernet adapter. > >> >> > >> >> Signed-off-by: Mason Huo > >> >> Signed-off-by: Minda Chen > >> >> --- > >> >> drivers/pci/Kconfig| 11 + > >> >> drivers/pci/Makefile | 1 + > >> >> drivers/pci/pcie_starfive_jh7110.c | 478 + > >> >> 3 files changed, 490 insertions(+) > >> >> create mode 100644 drivers/pci/pcie_starfive_jh7110.c > >> >> > >> >> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig > >> >> index ef328d2652..e7b0ff5bc3 100644 > >> >> --- a/drivers/pci/Kconfig > >> >> +++ b/drivers/pci/Kconfig > >> >> @@ -374,4 +374,15 @@ config PCIE_UNIPHIER > >> >> Say Y here if you want to enable PCIe controller support on > >> >> UniPhier SoCs. > >> >> > >> >> +config PCIE_STARFIVE_JH7110 > >> >> + bool "Enable Starfive JH7110 PCIe driver" > >> >> + depends on STARFIVE_JH7110 > >> >> + depends on PINCTRL_STARFIVE_JH7110 > >> >> + depends on CLK_JH7110 > >> >> + depends on RESET_JH7110 > >> >> + default y > >> >> + help > >> >> + Say Y here if you want to enable PCIe controller support on > >> >> + StarFive JH7110 SoC. > >> >> + > >> >> endif > >> >> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile > >> >> index 49506e7ba5..bbe3323bb5 100644 > >> >> --- a/drivers/pci/Makefile > >> >> +++ b/drivers/pci/Makefile > >> >> @@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o > >> >> obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o > >> >> obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o > >> >> obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o > >> >> +obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o > >> >> diff --git a/drivers/pci/pcie_starfive_jh7110.c > >> >> b/drivers/pci/pcie_starfive_jh7110.c > >> >> new file mode 100644 > >> >> index 00..5ccef1ef02 > >> >> --- /dev/null > >> >> +++ b/drivers/pci/pcie_starfive_jh7110.c > >> >> @@ -0,0 +1,478 @@ > >> >> +// SPDX-License-Identifier: GPL-2.0+ > >> >> +/* > >> >> + * StarFive PLDA PCIe host controller driver > >> >> + * > >> >> + * Copyright (c) 2023 Starfive, Inc. > >> >> + * Author: Mason Huo > >> >> + * > >> >> + */ > >> >> + > >> >> +#include > >> >> +#include > >> >> +#include > >> >> +#include > >> >> +#include > >> >> +#include > >> >> +#include > >> >> +#include > >> >> +#include > >> >> +#include > >> >> +#include > >> >> +#include > >> >> +#include > >> >> +#include > >> >> +#include > >> >> +#include > >> >> +#include > >> >> + > >> >> +DECLARE_GLOBAL_DATA_PTR; > >> >> + > >> >> +#define GEN_SETTINGS 0x80 > >> >> +#define PCIE_PCI_IDS 0x9C > >> >> +#define PCIE_WINROM0xFC > >> >> +#define PMSG_SUPPORT_RX0x3F0 > >> >> +#define PCI_MISC 0xB4 > >> >> + > >> >> +#define PLDA_EP_ENABLE 0 > >> >> +#define PLDA_RP_ENABLE 1 > >> >> + > >> >> +#define IDS_REVISION_ID0x02 > >> >> +#define IDS_PCI_TO_PCI_BRIDGE 0x060400 > >> >> +#define IDS_CLASS_CODE_SHIFT 8 > >> > > >> > Please do not duplicate standard PCI macros and constants. In U-Boot > >> > they are already available in include/pci_ids.h header file. > >> > > >> ok > >> >> +#define PREF_MEM_WIN_64_SUPPORTBIT(3) > >> >> +#define PMSG_LTR_SUPPORT BIT(2) > >> >> +#define PLDA_FUNCTION_DIS BIT(15) > >> >> +#define PLDA_FUNC_NUM 4 > >> >> +#define PLDA_PHY_FUNC_SHIFT9 > >> >> + > >> >> +#define XR3PCI_ATR_AXI4_SLV0 0x800 > >> >> +#define XR3PCI_ATR_SRC_ADDR_LOW0x0 > >> >> +#define XR3PCI_ATR_SRC_ADDR_HIGH 0x4 > >> >> +#define XR3PCI_ATR_TRSL_ADDR_LOW 0x8 > >> >> +#define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc > >> >> +#define XR3PCI_ATR_TRSL_PARAM 0x10 > >> >> +#define XR3PCI_ATR_TABLE_OFFSET0x20 > >> >> +#define XR3PCI_ATR_MAX_TABLE_NUM 8 > >> >> + > >> >> +#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT 1 > >> >> +#define XR3PCI_ATR_SRC_ADDR_MASK GENMASK(31, 12) > >> >> +#define XR3PCI_ATR_TRSL_ADDR_MASK GENMASK(31, 12) > >> >> +#define XR3_PCI_ECAM_SIZE 28 > >> >> +#define XR3PCI_ATR_TRSL_DIRBIT(22) > >> >> +/* IDs used in the XR3PCI_ATR_TRSL_PARAM */ > >> >> +#define XR3PCI_ATR_TRSLID_PCIE_MEMORY 0x0 > >> >> +#define
Re: [PATCH v2 1/3] starfive: pci: Add StarFive JH7110 pcie driver
On 2023/3/11 1:42, Pali Rohár wrote: > On Friday 10 March 2023 18:36:44 Minda Chen wrote: >> On 2023/3/8 15:31, Pali Rohár wrote: >> > Hello! See few comments below. >> > >> > On Wednesday 08 March 2023 13:48:31 Minda Chen wrote: >> >> From: Mason Huo >> >> >> >> Add pcie driver for StarFive JH7110, the driver depends on >> >> starfive gpio, pinctrl, clk and reset driver to do init. >> >> >> >> Several devices are tested: >> >> a) M.2 NVMe SSD >> >> b) Realtek 8169 Ethernet adapter. >> >> >> >> Signed-off-by: Mason Huo >> >> Signed-off-by: Minda Chen >> >> --- >> >> drivers/pci/Kconfig| 11 + >> >> drivers/pci/Makefile | 1 + >> >> drivers/pci/pcie_starfive_jh7110.c | 478 + >> >> 3 files changed, 490 insertions(+) >> >> create mode 100644 drivers/pci/pcie_starfive_jh7110.c >> >> >> >> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig >> >> index ef328d2652..e7b0ff5bc3 100644 >> >> --- a/drivers/pci/Kconfig >> >> +++ b/drivers/pci/Kconfig >> >> @@ -374,4 +374,15 @@ config PCIE_UNIPHIER >> >> Say Y here if you want to enable PCIe controller support on >> >> UniPhier SoCs. >> >> >> >> +config PCIE_STARFIVE_JH7110 >> >> + bool "Enable Starfive JH7110 PCIe driver" >> >> + depends on STARFIVE_JH7110 >> >> + depends on PINCTRL_STARFIVE_JH7110 >> >> + depends on CLK_JH7110 >> >> + depends on RESET_JH7110 >> >> + default y >> >> + help >> >> + Say Y here if you want to enable PCIe controller support on >> >> + StarFive JH7110 SoC. >> >> + >> >> endif >> >> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile >> >> index 49506e7ba5..bbe3323bb5 100644 >> >> --- a/drivers/pci/Makefile >> >> +++ b/drivers/pci/Makefile >> >> @@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o >> >> obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o >> >> obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o >> >> obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o >> >> +obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o >> >> diff --git a/drivers/pci/pcie_starfive_jh7110.c >> >> b/drivers/pci/pcie_starfive_jh7110.c >> >> new file mode 100644 >> >> index 00..5ccef1ef02 >> >> --- /dev/null >> >> +++ b/drivers/pci/pcie_starfive_jh7110.c >> >> @@ -0,0 +1,478 @@ >> >> +// SPDX-License-Identifier: GPL-2.0+ >> >> +/* >> >> + * StarFive PLDA PCIe host controller driver >> >> + * >> >> + * Copyright (c) 2023 Starfive, Inc. >> >> + * Author: Mason Huo >> >> + * >> >> + */ >> >> + >> >> +#include >> >> +#include >> >> +#include >> >> +#include >> >> +#include >> >> +#include >> >> +#include >> >> +#include >> >> +#include >> >> +#include >> >> +#include >> >> +#include >> >> +#include >> >> +#include >> >> +#include >> >> +#include >> >> +#include >> >> + >> >> +DECLARE_GLOBAL_DATA_PTR; >> >> + >> >> +#define GEN_SETTINGS 0x80 >> >> +#define PCIE_PCI_IDS 0x9C >> >> +#define PCIE_WINROM 0xFC >> >> +#define PMSG_SUPPORT_RX 0x3F0 >> >> +#define PCI_MISC 0xB4 >> >> + >> >> +#define PLDA_EP_ENABLE 0 >> >> +#define PLDA_RP_ENABLE 1 >> >> + >> >> +#define IDS_REVISION_ID 0x02 >> >> +#define IDS_PCI_TO_PCI_BRIDGE0x060400 >> >> +#define IDS_CLASS_CODE_SHIFT 8 >> > >> > Please do not duplicate standard PCI macros and constants. In U-Boot >> > they are already available in include/pci_ids.h header file. >> > >> ok >> >> +#define PREF_MEM_WIN_64_SUPPORT BIT(3) >> >> +#define PMSG_LTR_SUPPORT BIT(2) >> >> +#define PLDA_FUNCTION_DISBIT(15) >> >> +#define PLDA_FUNC_NUM4 >> >> +#define PLDA_PHY_FUNC_SHIFT 9 >> >> + >> >> +#define XR3PCI_ATR_AXI4_SLV0 0x800 >> >> +#define XR3PCI_ATR_SRC_ADDR_LOW 0x0 >> >> +#define XR3PCI_ATR_SRC_ADDR_HIGH 0x4 >> >> +#define XR3PCI_ATR_TRSL_ADDR_LOW 0x8 >> >> +#define XR3PCI_ATR_TRSL_ADDR_HIGH0xc >> >> +#define XR3PCI_ATR_TRSL_PARAM0x10 >> >> +#define XR3PCI_ATR_TABLE_OFFSET 0x20 >> >> +#define XR3PCI_ATR_MAX_TABLE_NUM 8 >> >> + >> >> +#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT1 >> >> +#define XR3PCI_ATR_SRC_ADDR_MASK GENMASK(31, 12) >> >> +#define XR3PCI_ATR_TRSL_ADDR_MASKGENMASK(31, 12) >> >> +#define XR3_PCI_ECAM_SIZE28 >> >> +#define XR3PCI_ATR_TRSL_DIR BIT(22) >> >> +/* IDs used in the XR3PCI_ATR_TRSL_PARAM */ >> >> +#define XR3PCI_ATR_TRSLID_PCIE_MEMORY0x0 >> >> +#define XR3PCI_ATR_TRSLID_PCIE_CONFIG0x1 >> >> + >> >> +#define ECAM_BUS_SHIFT 20 >> >> +#define ECAM_DEV_SHIFT 15 >> >> +#define ECAM_FUNC_SHIFT 12 >> > >> > Please do not implement duplicate PCIe ECAM code. U-Boot and also Linux >> > kernel already provides PCIE_ECAM_OFFSET() macro. >> > >> >> +/* Secondary bus number offset in config space */ >> >>
Re: [PATCH v2 1/3] starfive: pci: Add StarFive JH7110 pcie driver
On Friday 10 March 2023 18:36:44 Minda Chen wrote: > On 2023/3/8 15:31, Pali Rohár wrote: > > Hello! See few comments below. > > > > On Wednesday 08 March 2023 13:48:31 Minda Chen wrote: > >> From: Mason Huo > >> > >> Add pcie driver for StarFive JH7110, the driver depends on > >> starfive gpio, pinctrl, clk and reset driver to do init. > >> > >> Several devices are tested: > >> a) M.2 NVMe SSD > >> b) Realtek 8169 Ethernet adapter. > >> > >> Signed-off-by: Mason Huo > >> Signed-off-by: Minda Chen > >> --- > >> drivers/pci/Kconfig| 11 + > >> drivers/pci/Makefile | 1 + > >> drivers/pci/pcie_starfive_jh7110.c | 478 + > >> 3 files changed, 490 insertions(+) > >> create mode 100644 drivers/pci/pcie_starfive_jh7110.c > >> > >> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig > >> index ef328d2652..e7b0ff5bc3 100644 > >> --- a/drivers/pci/Kconfig > >> +++ b/drivers/pci/Kconfig > >> @@ -374,4 +374,15 @@ config PCIE_UNIPHIER > >> Say Y here if you want to enable PCIe controller support on > >> UniPhier SoCs. > >> > >> +config PCIE_STARFIVE_JH7110 > >> + bool "Enable Starfive JH7110 PCIe driver" > >> + depends on STARFIVE_JH7110 > >> + depends on PINCTRL_STARFIVE_JH7110 > >> + depends on CLK_JH7110 > >> + depends on RESET_JH7110 > >> + default y > >> + help > >> +Say Y here if you want to enable PCIe controller support on > >> +StarFive JH7110 SoC. > >> + > >> endif > >> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile > >> index 49506e7ba5..bbe3323bb5 100644 > >> --- a/drivers/pci/Makefile > >> +++ b/drivers/pci/Makefile > >> @@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o > >> obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o > >> obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o > >> obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o > >> +obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o > >> diff --git a/drivers/pci/pcie_starfive_jh7110.c > >> b/drivers/pci/pcie_starfive_jh7110.c > >> new file mode 100644 > >> index 00..5ccef1ef02 > >> --- /dev/null > >> +++ b/drivers/pci/pcie_starfive_jh7110.c > >> @@ -0,0 +1,478 @@ > >> +// SPDX-License-Identifier: GPL-2.0+ > >> +/* > >> + * StarFive PLDA PCIe host controller driver > >> + * > >> + * Copyright (c) 2023 Starfive, Inc. > >> + * Author: Mason Huo > >> + * > >> + */ > >> + > >> +#include > >> +#include > >> +#include > >> +#include > >> +#include > >> +#include > >> +#include > >> +#include > >> +#include > >> +#include > >> +#include > >> +#include > >> +#include > >> +#include > >> +#include > >> +#include > >> +#include > >> + > >> +DECLARE_GLOBAL_DATA_PTR; > >> + > >> +#define GEN_SETTINGS 0x80 > >> +#define PCIE_PCI_IDS 0x9C > >> +#define PCIE_WINROM 0xFC > >> +#define PMSG_SUPPORT_RX 0x3F0 > >> +#define PCI_MISC 0xB4 > >> + > >> +#define PLDA_EP_ENABLE0 > >> +#define PLDA_RP_ENABLE1 > >> + > >> +#define IDS_REVISION_ID 0x02 > >> +#define IDS_PCI_TO_PCI_BRIDGE 0x060400 > >> +#define IDS_CLASS_CODE_SHIFT 8 > > > > Please do not duplicate standard PCI macros and constants. In U-Boot > > they are already available in include/pci_ids.h header file. > > > ok > >> +#define PREF_MEM_WIN_64_SUPPORT BIT(3) > >> +#define PMSG_LTR_SUPPORT BIT(2) > >> +#define PLDA_FUNCTION_DIS BIT(15) > >> +#define PLDA_FUNC_NUM 4 > >> +#define PLDA_PHY_FUNC_SHIFT 9 > >> + > >> +#define XR3PCI_ATR_AXI4_SLV0 0x800 > >> +#define XR3PCI_ATR_SRC_ADDR_LOW 0x0 > >> +#define XR3PCI_ATR_SRC_ADDR_HIGH 0x4 > >> +#define XR3PCI_ATR_TRSL_ADDR_LOW 0x8 > >> +#define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc > >> +#define XR3PCI_ATR_TRSL_PARAM 0x10 > >> +#define XR3PCI_ATR_TABLE_OFFSET 0x20 > >> +#define XR3PCI_ATR_MAX_TABLE_NUM 8 > >> + > >> +#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT 1 > >> +#define XR3PCI_ATR_SRC_ADDR_MASK GENMASK(31, 12) > >> +#define XR3PCI_ATR_TRSL_ADDR_MASK GENMASK(31, 12) > >> +#define XR3_PCI_ECAM_SIZE 28 > >> +#define XR3PCI_ATR_TRSL_DIR BIT(22) > >> +/* IDs used in the XR3PCI_ATR_TRSL_PARAM */ > >> +#define XR3PCI_ATR_TRSLID_PCIE_MEMORY 0x0 > >> +#define XR3PCI_ATR_TRSLID_PCIE_CONFIG 0x1 > >> + > >> +#define ECAM_BUS_SHIFT20 > >> +#define ECAM_DEV_SHIFT15 > >> +#define ECAM_FUNC_SHIFT 12 > > > > Please do not implement duplicate PCIe ECAM code. U-Boot and also Linux > > kernel already provides PCIE_ECAM_OFFSET() macro. > > > >> +/* Secondary bus number offset in config space */ > >> +#define PCI_SECONDARY_BUS 0x19 > > > > Unused. > > > ok > >> + > >> +/* system control */ > >> +#define STG_SYSCON_K_RP_NEP_MASK BIT(8) > >> +#define
Re: [PATCH v2 1/3] starfive: pci: Add StarFive JH7110 pcie driver
On 2023/3/8 15:31, Pali Rohár wrote: > Hello! See few comments below. > > On Wednesday 08 March 2023 13:48:31 Minda Chen wrote: >> From: Mason Huo >> >> Add pcie driver for StarFive JH7110, the driver depends on >> starfive gpio, pinctrl, clk and reset driver to do init. >> >> Several devices are tested: >> a) M.2 NVMe SSD >> b) Realtek 8169 Ethernet adapter. >> >> Signed-off-by: Mason Huo >> Signed-off-by: Minda Chen >> --- >> drivers/pci/Kconfig| 11 + >> drivers/pci/Makefile | 1 + >> drivers/pci/pcie_starfive_jh7110.c | 478 + >> 3 files changed, 490 insertions(+) >> create mode 100644 drivers/pci/pcie_starfive_jh7110.c >> >> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig >> index ef328d2652..e7b0ff5bc3 100644 >> --- a/drivers/pci/Kconfig >> +++ b/drivers/pci/Kconfig >> @@ -374,4 +374,15 @@ config PCIE_UNIPHIER >>Say Y here if you want to enable PCIe controller support on >>UniPhier SoCs. >> >> +config PCIE_STARFIVE_JH7110 >> +bool "Enable Starfive JH7110 PCIe driver" >> +depends on STARFIVE_JH7110 >> +depends on PINCTRL_STARFIVE_JH7110 >> +depends on CLK_JH7110 >> +depends on RESET_JH7110 >> +default y >> +help >> + Say Y here if you want to enable PCIe controller support on >> + StarFive JH7110 SoC. >> + >> endif >> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile >> index 49506e7ba5..bbe3323bb5 100644 >> --- a/drivers/pci/Makefile >> +++ b/drivers/pci/Makefile >> @@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o >> obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o >> obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o >> obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o >> +obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o >> diff --git a/drivers/pci/pcie_starfive_jh7110.c >> b/drivers/pci/pcie_starfive_jh7110.c >> new file mode 100644 >> index 00..5ccef1ef02 >> --- /dev/null >> +++ b/drivers/pci/pcie_starfive_jh7110.c >> @@ -0,0 +1,478 @@ >> +// SPDX-License-Identifier: GPL-2.0+ >> +/* >> + * StarFive PLDA PCIe host controller driver >> + * >> + * Copyright (c) 2023 Starfive, Inc. >> + * Author: Mason Huo >> + * >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +DECLARE_GLOBAL_DATA_PTR; >> + >> +#define GEN_SETTINGS0x80 >> +#define PCIE_PCI_IDS0x9C >> +#define PCIE_WINROM 0xFC >> +#define PMSG_SUPPORT_RX 0x3F0 >> +#define PCI_MISC0xB4 >> + >> +#define PLDA_EP_ENABLE 0 >> +#define PLDA_RP_ENABLE 1 >> + >> +#define IDS_REVISION_ID 0x02 >> +#define IDS_PCI_TO_PCI_BRIDGE 0x060400 >> +#define IDS_CLASS_CODE_SHIFT8 > > Please do not duplicate standard PCI macros and constants. In U-Boot > they are already available in include/pci_ids.h header file. > ok >> +#define PREF_MEM_WIN_64_SUPPORT BIT(3) >> +#define PMSG_LTR_SUPPORTBIT(2) >> +#define PLDA_FUNCTION_DIS BIT(15) >> +#define PLDA_FUNC_NUM 4 >> +#define PLDA_PHY_FUNC_SHIFT 9 >> + >> +#define XR3PCI_ATR_AXI4_SLV00x800 >> +#define XR3PCI_ATR_SRC_ADDR_LOW 0x0 >> +#define XR3PCI_ATR_SRC_ADDR_HIGH0x4 >> +#define XR3PCI_ATR_TRSL_ADDR_LOW0x8 >> +#define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc >> +#define XR3PCI_ATR_TRSL_PARAM 0x10 >> +#define XR3PCI_ATR_TABLE_OFFSET 0x20 >> +#define XR3PCI_ATR_MAX_TABLE_NUM8 >> + >> +#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT 1 >> +#define XR3PCI_ATR_SRC_ADDR_MASKGENMASK(31, 12) >> +#define XR3PCI_ATR_TRSL_ADDR_MASK GENMASK(31, 12) >> +#define XR3_PCI_ECAM_SIZE 28 >> +#define XR3PCI_ATR_TRSL_DIR BIT(22) >> +/* IDs used in the XR3PCI_ATR_TRSL_PARAM */ >> +#define XR3PCI_ATR_TRSLID_PCIE_MEMORY 0x0 >> +#define XR3PCI_ATR_TRSLID_PCIE_CONFIG 0x1 >> + >> +#define ECAM_BUS_SHIFT 20 >> +#define ECAM_DEV_SHIFT 15 >> +#define ECAM_FUNC_SHIFT 12 > > Please do not implement duplicate PCIe ECAM code. U-Boot and also Linux > kernel already provides PCIE_ECAM_OFFSET() macro. > >> +/* Secondary bus number offset in config space */ >> +#define PCI_SECONDARY_BUS 0x19 > > Unused. > ok >> + >> +/* system control */ >> +#define STG_SYSCON_K_RP_NEP_MASKBIT(8) >> +#define STG_SYSCON_AXI4_SLVL_ARFUNC_MASKGENMASK(22, 8) >> +#define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT 8 >> +#define STG_SYSCON_AXI4_SLVL_AWFUNC_MASKGENMASK(14, 0) >> +#define STG_SYSCON_CLKREQ_MASK BIT(22) >> +#define STG_SYSCON_CKREF_SRC_SHIFT
Re: [PATCH v2 1/3] starfive: pci: Add StarFive JH7110 pcie driver
Hello! See few comments below.
On Wednesday 08 March 2023 13:48:31 Minda Chen wrote:
> From: Mason Huo
>
> Add pcie driver for StarFive JH7110, the driver depends on
> starfive gpio, pinctrl, clk and reset driver to do init.
>
> Several devices are tested:
> a) M.2 NVMe SSD
> b) Realtek 8169 Ethernet adapter.
>
> Signed-off-by: Mason Huo
> Signed-off-by: Minda Chen
> ---
> drivers/pci/Kconfig| 11 +
> drivers/pci/Makefile | 1 +
> drivers/pci/pcie_starfive_jh7110.c | 478 +
> 3 files changed, 490 insertions(+)
> create mode 100644 drivers/pci/pcie_starfive_jh7110.c
>
> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
> index ef328d2652..e7b0ff5bc3 100644
> --- a/drivers/pci/Kconfig
> +++ b/drivers/pci/Kconfig
> @@ -374,4 +374,15 @@ config PCIE_UNIPHIER
> Say Y here if you want to enable PCIe controller support on
> UniPhier SoCs.
>
> +config PCIE_STARFIVE_JH7110
> + bool "Enable Starfive JH7110 PCIe driver"
> + depends on STARFIVE_JH7110
> + depends on PINCTRL_STARFIVE_JH7110
> + depends on CLK_JH7110
> + depends on RESET_JH7110
> + default y
> + help
> + Say Y here if you want to enable PCIe controller support on
> + StarFive JH7110 SoC.
> +
> endif
> diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
> index 49506e7ba5..bbe3323bb5 100644
> --- a/drivers/pci/Makefile
> +++ b/drivers/pci/Makefile
> @@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
> obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
> obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
> obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
> +obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
> diff --git a/drivers/pci/pcie_starfive_jh7110.c
> b/drivers/pci/pcie_starfive_jh7110.c
> new file mode 100644
> index 00..5ccef1ef02
> --- /dev/null
> +++ b/drivers/pci/pcie_starfive_jh7110.c
> @@ -0,0 +1,478 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * StarFive PLDA PCIe host controller driver
> + *
> + * Copyright (c) 2023 Starfive, Inc.
> + * Author: Mason Huo
> + *
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define GEN_SETTINGS 0x80
> +#define PCIE_PCI_IDS 0x9C
> +#define PCIE_WINROM 0xFC
> +#define PMSG_SUPPORT_RX 0x3F0
> +#define PCI_MISC 0xB4
> +
> +#define PLDA_EP_ENABLE 0
> +#define PLDA_RP_ENABLE 1
> +
> +#define IDS_REVISION_ID 0x02
> +#define IDS_PCI_TO_PCI_BRIDGE0x060400
> +#define IDS_CLASS_CODE_SHIFT 8
Please do not duplicate standard PCI macros and constants. In U-Boot
they are already available in include/pci_ids.h header file.
> +#define PREF_MEM_WIN_64_SUPPORT BIT(3)
> +#define PMSG_LTR_SUPPORT BIT(2)
> +#define PLDA_FUNCTION_DISBIT(15)
> +#define PLDA_FUNC_NUM4
> +#define PLDA_PHY_FUNC_SHIFT 9
> +
> +#define XR3PCI_ATR_AXI4_SLV0 0x800
> +#define XR3PCI_ATR_SRC_ADDR_LOW 0x0
> +#define XR3PCI_ATR_SRC_ADDR_HIGH 0x4
> +#define XR3PCI_ATR_TRSL_ADDR_LOW 0x8
> +#define XR3PCI_ATR_TRSL_ADDR_HIGH0xc
> +#define XR3PCI_ATR_TRSL_PARAM0x10
> +#define XR3PCI_ATR_TABLE_OFFSET 0x20
> +#define XR3PCI_ATR_MAX_TABLE_NUM 8
> +
> +#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT1
> +#define XR3PCI_ATR_SRC_ADDR_MASK GENMASK(31, 12)
> +#define XR3PCI_ATR_TRSL_ADDR_MASKGENMASK(31, 12)
> +#define XR3_PCI_ECAM_SIZE28
> +#define XR3PCI_ATR_TRSL_DIR BIT(22)
> +/* IDs used in the XR3PCI_ATR_TRSL_PARAM */
> +#define XR3PCI_ATR_TRSLID_PCIE_MEMORY0x0
> +#define XR3PCI_ATR_TRSLID_PCIE_CONFIG0x1
> +
> +#define ECAM_BUS_SHIFT 20
> +#define ECAM_DEV_SHIFT 15
> +#define ECAM_FUNC_SHIFT 12
Please do not implement duplicate PCIe ECAM code. U-Boot and also Linux
kernel already provides PCIE_ECAM_OFFSET() macro.
> +/* Secondary bus number offset in config space */
> +#define PCI_SECONDARY_BUS0x19
Unused.
> +
> +/* system control */
> +#define STG_SYSCON_K_RP_NEP_MASK BIT(8)
> +#define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK GENMASK(22, 8)
> +#define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT8
> +#define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK GENMASK(14, 0)
> +#define STG_SYSCON_CLKREQ_MASK BIT(22)
> +#define STG_SYSCON_CKREF_SRC_SHIFT 18
> +#define STG_SYSCON_CKREF_SRC_MASKGENMASK(19, 18)
> +
> +struct starfive_pcie {
> + struct udevice *dev;
> +
> + void __iomem *reg_base;
> + void
[PATCH v2 1/3] starfive: pci: Add StarFive JH7110 pcie driver
From: Mason Huo
Add pcie driver for StarFive JH7110, the driver depends on
starfive gpio, pinctrl, clk and reset driver to do init.
Several devices are tested:
a) M.2 NVMe SSD
b) Realtek 8169 Ethernet adapter.
Signed-off-by: Mason Huo
Signed-off-by: Minda Chen
---
drivers/pci/Kconfig| 11 +
drivers/pci/Makefile | 1 +
drivers/pci/pcie_starfive_jh7110.c | 478 +
3 files changed, 490 insertions(+)
create mode 100644 drivers/pci/pcie_starfive_jh7110.c
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index ef328d2652..e7b0ff5bc3 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -374,4 +374,15 @@ config PCIE_UNIPHIER
Say Y here if you want to enable PCIe controller support on
UniPhier SoCs.
+config PCIE_STARFIVE_JH7110
+ bool "Enable Starfive JH7110 PCIe driver"
+ depends on STARFIVE_JH7110
+ depends on PINCTRL_STARFIVE_JH7110
+ depends on CLK_JH7110
+ depends on RESET_JH7110
+ default y
+ help
+ Say Y here if you want to enable PCIe controller support on
+ StarFive JH7110 SoC.
+
endif
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 49506e7ba5..bbe3323bb5 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o
obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o
obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o
obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o
+obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o
diff --git a/drivers/pci/pcie_starfive_jh7110.c
b/drivers/pci/pcie_starfive_jh7110.c
new file mode 100644
index 00..5ccef1ef02
--- /dev/null
+++ b/drivers/pci/pcie_starfive_jh7110.c
@@ -0,0 +1,478 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * StarFive PLDA PCIe host controller driver
+ *
+ * Copyright (c) 2023 Starfive, Inc.
+ * Author: Mason Huo
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GEN_SETTINGS 0x80
+#define PCIE_PCI_IDS 0x9C
+#define PCIE_WINROM0xFC
+#define PMSG_SUPPORT_RX0x3F0
+#define PCI_MISC 0xB4
+
+#define PLDA_EP_ENABLE 0
+#define PLDA_RP_ENABLE 1
+
+#define IDS_REVISION_ID0x02
+#define IDS_PCI_TO_PCI_BRIDGE 0x060400
+#define IDS_CLASS_CODE_SHIFT 8
+
+#define PREF_MEM_WIN_64_SUPPORTBIT(3)
+#define PMSG_LTR_SUPPORT BIT(2)
+#define PLDA_FUNCTION_DIS BIT(15)
+#define PLDA_FUNC_NUM 4
+#define PLDA_PHY_FUNC_SHIFT9
+
+#define XR3PCI_ATR_AXI4_SLV0 0x800
+#define XR3PCI_ATR_SRC_ADDR_LOW0x0
+#define XR3PCI_ATR_SRC_ADDR_HIGH 0x4
+#define XR3PCI_ATR_TRSL_ADDR_LOW 0x8
+#define XR3PCI_ATR_TRSL_ADDR_HIGH 0xc
+#define XR3PCI_ATR_TRSL_PARAM 0x10
+#define XR3PCI_ATR_TABLE_OFFSET0x20
+#define XR3PCI_ATR_MAX_TABLE_NUM 8
+
+#define XR3PCI_ATR_SRC_WIN_SIZE_SHIFT 1
+#define XR3PCI_ATR_SRC_ADDR_MASK GENMASK(31, 12)
+#define XR3PCI_ATR_TRSL_ADDR_MASK GENMASK(31, 12)
+#define XR3_PCI_ECAM_SIZE 28
+#define XR3PCI_ATR_TRSL_DIRBIT(22)
+/* IDs used in the XR3PCI_ATR_TRSL_PARAM */
+#define XR3PCI_ATR_TRSLID_PCIE_MEMORY 0x0
+#define XR3PCI_ATR_TRSLID_PCIE_CONFIG 0x1
+
+#define ECAM_BUS_SHIFT 20
+#define ECAM_DEV_SHIFT 15
+#define ECAM_FUNC_SHIFT12
+/* Secondary bus number offset in config space */
+#define PCI_SECONDARY_BUS 0x19
+
+/* system control */
+#define STG_SYSCON_K_RP_NEP_MASK BIT(8)
+#define STG_SYSCON_AXI4_SLVL_ARFUNC_MASK GENMASK(22, 8)
+#define STG_SYSCON_AXI4_SLVL_ARFUNC_SHIFT 8
+#define STG_SYSCON_AXI4_SLVL_AWFUNC_MASK GENMASK(14, 0)
+#define STG_SYSCON_CLKREQ_MASK BIT(22)
+#define STG_SYSCON_CKREF_SRC_SHIFT 18
+#define STG_SYSCON_CKREF_SRC_MASK GENMASK(19, 18)
+
+struct starfive_pcie {
+ struct udevice *dev;
+
+ void __iomem *reg_base;
+ void __iomem *cfg_base;
+
+ struct regmap *regmap;
+ u32 stg_arfun;
+ u32 stg_awfun;
+ u32 stg_rp_nep;
+
+ struct clk_bulk clks;
+ struct reset_ctl_bulk rsts;
+
+ int atr_table_num;
+ int first_busno;
+};
+
+static int starfive_pcie_addr_valid(pci_dev_t bdf, int first_busno)
+{
+ if ((PCI_BUS(bdf) == first_busno) && (PCI_DEV(bdf) > 0))
+ return 0;
+ if ((PCI_BUS(bdf) == first_busno + 1) && (PCI_DEV(bdf) > 0))
+ return 0;
+
+ return 1;
+}
+
+static int starfive_pcie_off_conf(pci_dev_t bdf, uint offset)
+{
+
