This sync's the RZ/G2N clock tables with mainline linux 5.9-rc4
commit f4d51dffc6c0 ("Linux 5.9-rc4")
Signed-off-by: Biju Das
Reviewed-by: Lad Prabhakar
---
V1->V2
* Rebased to u-boot-sh master.
---
arch/arm/mach-rmobile/Kconfig.64| 1 +
drivers/clk/renesas/Kconfig | 6 +
drivers/clk/renesas/Makefile| 1 +
drivers/clk/renesas/r8a774b1-cpg-mssr.c | 336
4 files changed, 344 insertions(+)
create mode 100644 drivers/clk/renesas/r8a774b1-cpg-mssr.c
diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-rmobile/Kconfig.64
index 0d55b74c42..2bf17ddc24 100644
--- a/arch/arm/mach-rmobile/Kconfig.64
+++ b/arch/arm/mach-rmobile/Kconfig.64
@@ -7,6 +7,7 @@ config R8A774A1
config R8A774B1
bool "Renesas SoC R8A774B1"
+ imply CLK_R8A774B1
config R8A774E1
bool "Renesas SoC R8A774E1"
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 284e2138b3..00a173b8c8 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -55,6 +55,12 @@ config CLK_R8A774A1
help
Enable this to support the clocks on Renesas R8A774A1 SoC.
+config CLK_R8A774B1
+ bool "Renesas R8A774B1 clock driver"
+ depends on CLK_RCAR_GEN3
+ help
+ Enable this to support the clocks on Renesas R8A774B1 SoC.
+
config CLK_R8A7795
bool "Renesas R8A7795 clock driver"
depends on CLK_RCAR_GEN3
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index dd599b757e..2e8d796f89 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -1,6 +1,7 @@
obj-$(CONFIG_CLK_RENESAS) += renesas-cpg-mssr.o
obj-$(CONFIG_CLK_RCAR_GEN2) += clk-rcar-gen2.o
obj-$(CONFIG_CLK_R8A774A1) += r8a774a1-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A774B1) += r8a774b1-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7790) += r8a7790-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7791) += r8a7791-cpg-mssr.o
obj-$(CONFIG_CLK_R8A7792) += r8a7792-cpg-mssr.o
diff --git a/drivers/clk/renesas/r8a774b1-cpg-mssr.c
b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
new file mode 100644
index 00..7b6947b5b9
--- /dev/null
+++ b/drivers/clk/renesas/r8a774b1-cpg-mssr.c
@@ -0,0 +1,336 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * r8a774b1 Clock Pulse Generator / Module Standby and Software Reset
+ *
+ * Copyright (C) 2020 Renesas Electronics Corp.
+ *
+ * Based on r8a7796-cpg-mssr.c
+ *
+ * Copyright (C) 2016 Glider bvba
+ */
+
+#include
+#include
+#include
+
+#include
+
+#include "renesas-cpg-mssr.h"
+#include "rcar-gen3-cpg.h"
+
+enum clk_ids {
+ /* Core Clock Outputs exported to DT */
+ LAST_DT_CORE_CLK = R8A774B1_CLK_CANFD,
+
+ /* External Input Clocks */
+ CLK_EXTAL,
+ CLK_EXTALR,
+
+ /* Internal Core Clocks */
+ CLK_MAIN,
+ CLK_PLL0,
+ CLK_PLL1,
+ CLK_PLL3,
+ CLK_PLL4,
+ CLK_PLL1_DIV2,
+ CLK_PLL1_DIV4,
+ CLK_S0,
+ CLK_S1,
+ CLK_S2,
+ CLK_S3,
+ CLK_SDSRC,
+ CLK_RINT,
+
+ /* Module Clocks */
+ MOD_CLK_BASE
+};
+
+static const struct cpg_core_clk r8a774b1_core_clks[] = {
+ /* External Clock Inputs */
+ DEF_INPUT("extal", CLK_EXTAL),
+ DEF_INPUT("extalr", CLK_EXTALR),
+
+ /* Internal Core Clocks */
+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
+ DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
+ DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
+
+ DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
+ DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".s0",CLK_S0,CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED(".s1",CLK_S1,CLK_PLL1_DIV2, 3, 1),
+ DEF_FIXED(".s2",CLK_S2,CLK_PLL1_DIV2, 4, 1),
+ DEF_FIXED(".s3",CLK_S3,CLK_PLL1_DIV2, 6, 1),
+ DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
+
+ DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
+
+ /* Core Clock Outputs */
+ DEF_GEN3_Z("z", R8A774B1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0,
2, 8),
+ DEF_FIXED("ztr",R8A774B1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
+ DEF_FIXED("ztrd2", R8A774B1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
+ DEF_FIXED("zt", R8A774B1_CLK_ZT,CLK_PLL1_DIV2, 4, 1),
+ DEF_FIXED("zx", R8A774B1_CLK_ZX,CLK_PLL1_DIV2, 2, 1),
+ DEF_FIXED("s0d1", R8A774B1_CLK_S0D1, CLK_S0, 1, 1),
+ DEF_FIXED("s0d2", R8A774B1_CLK_S0D2, CLK_S0, 2, 1),
+ DEF_FIXED("s0d3", R8A774B1_CLK_S0D3, CLK_S0, 3, 1),
+ DEF_FIXED("s0d4", R8A774B1_CLK_S0D4, CLK_S0,
