Re: [PATCH v2 1/5] clk: rockchip: rk3568: support dclk_vop select more parent clks

2023-10-13 Thread Kever Yang 



On 2023/10/11 18:29, Elaine Zhang wrote:

For dclk_vop to support more frequencies.

Signed-off-by: Elaine Zhang 

Reviewed-by: Kever Yang 

Thanks,
- Kever

---
  drivers/clk/rockchip/clk_rk3568.c | 10 --
  1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk_rk3568.c 
b/drivers/clk/rockchip/clk_rk3568.c
index 599b7b130eb9..68f59e57 100644
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -1838,7 +1838,7 @@ static ulong rk3568_dclk_vop_set_clk(struct 
rk3568_clk_priv *priv,
rockchip_pll_set_rate(_pll_clks[VPLL],
  priv->cru, VPLL, div * rate);
} else {
-   for (i = 0; i <= DCLK_VOP_SEL_CPLL; i++) {
+   for (i = sel; i <= DCLK_VOP_SEL_CPLL; i++) {
switch (i) {
case DCLK_VOP_SEL_GPLL:
pll_rate = priv->gpll_hz;
@@ -2785,9 +2785,15 @@ static int rk3568_dclk_vop_set_parent(struct clk *clk, 
struct clk *parent)
if (parent->id == PLL_VPLL) {
rk_clrsetreg(>clksel_con[con_id], DCLK0_VOP_SEL_MASK,
 DCLK_VOP_SEL_VPLL << DCLK0_VOP_SEL_SHIFT);
-   } else {
+   } else if (parent->id == PLL_HPLL) {
rk_clrsetreg(>clksel_con[con_id], DCLK0_VOP_SEL_MASK,
 DCLK_VOP_SEL_HPLL << DCLK0_VOP_SEL_SHIFT);
+   } else if (parent->id == PLL_CPLL) {
+   rk_clrsetreg(>clksel_con[con_id], DCLK0_VOP_SEL_MASK,
+DCLK_VOP_SEL_CPLL << DCLK0_VOP_SEL_SHIFT);
+   } else {
+   rk_clrsetreg(>clksel_con[con_id], DCLK0_VOP_SEL_MASK,
+DCLK_VOP_SEL_GPLL << DCLK0_VOP_SEL_SHIFT);
}
  
  	return 0;

[PATCH v2 1/5] clk: rockchip: rk3568: support dclk_vop select more parent clks

2023-10-11 Thread Elaine Zhang 
For dclk_vop to support more frequencies.

Signed-off-by: Elaine Zhang 
---
 drivers/clk/rockchip/clk_rk3568.c | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/rockchip/clk_rk3568.c 
b/drivers/clk/rockchip/clk_rk3568.c
index 599b7b130eb9..68f59e57 100644
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -1838,7 +1838,7 @@ static ulong rk3568_dclk_vop_set_clk(struct 
rk3568_clk_priv *priv,
rockchip_pll_set_rate(_pll_clks[VPLL],
  priv->cru, VPLL, div * rate);
} else {
-   for (i = 0; i <= DCLK_VOP_SEL_CPLL; i++) {
+   for (i = sel; i <= DCLK_VOP_SEL_CPLL; i++) {
switch (i) {
case DCLK_VOP_SEL_GPLL:
pll_rate = priv->gpll_hz;
@@ -2785,9 +2785,15 @@ static int rk3568_dclk_vop_set_parent(struct clk *clk, 
struct clk *parent)
if (parent->id == PLL_VPLL) {
rk_clrsetreg(>clksel_con[con_id], DCLK0_VOP_SEL_MASK,
 DCLK_VOP_SEL_VPLL << DCLK0_VOP_SEL_SHIFT);
-   } else {
+   } else if (parent->id == PLL_HPLL) {
rk_clrsetreg(>clksel_con[con_id], DCLK0_VOP_SEL_MASK,
 DCLK_VOP_SEL_HPLL << DCLK0_VOP_SEL_SHIFT);
+   } else if (parent->id == PLL_CPLL) {
+   rk_clrsetreg(>clksel_con[con_id], DCLK0_VOP_SEL_MASK,
+DCLK_VOP_SEL_CPLL << DCLK0_VOP_SEL_SHIFT);
+   } else {
+   rk_clrsetreg(>clksel_con[con_id], DCLK0_VOP_SEL_MASK,
+DCLK_VOP_SEL_GPLL << DCLK0_VOP_SEL_SHIFT);
}
 
return 0;
-- 
2.17.1