Add info of boot flow and build steps for AM62x SK.
Signed-off-by: Vignesh Raghavendra
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doc/board/ti/am62x_sk.rst | 231 ++
doc/board/ti/index.rst| 1 +
2 files changed, 232 insertions(+)
create mode 100644 doc/board/ti/am62x_sk.rst
diff --git a/doc/board/ti/am62x_sk.rst b/doc/board/ti/am62x_sk.rst
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+.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+.. sectionauthor:: Vignesh Raghavendra
+
+Texas Instruments AM62 Platforms
+
+
+Introduction:
+-
+The AM62 SoC family is the follow on AM335x built on the K3 Multicore
+SoC architecture platform, providing ultra-low-power modes, dual
+display, multi-sensor edge compute, security and other BOM-saving
+integrations. The AM62 SoC targets a broad market to enable
+applications such as Industrial HMI, PLC/CNC/Robot control, Medical
+Equipment, Building Automation, Appliances and more.
+
+Some highlights of this SoC are:
+
+* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster.
+ Pin-to-pin compatible options for single and quad core are available.
+* Cortex-M4F for general-purpose or safety usage.
+* Dual display support, providing 24-bit RBG parallel interface and
+ OLDI/LVDS-4 Lane x2, up to 200MHz pixel clock support for 2K display
+ resolution.
+* Selectable GPU support, up to 8GFLOPS, providing better user experience
+ in 3D graphic display case and Android.
+* PRU(Programmable Realtime Unit) support for customized programmable
+ interfaces/IOs.
+* Integrated Giga-bit Ethernet switch supporting up to a total of two
+ external ports (TSN capable).
+* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for
+ NAND/FPGA connection, OSPI memory controller, 3xMcASP for audio,
+ 1x CSI-RX-4L for Camera, eCAP/eQEP, ePWM, among other peripherals.
+* Dedicated Centralized System Controller for Security, Power, and
+ Resource Management.
+* Multiple low power modes support, ex: Deep sleep, Standby, MCU-only,
+ enabling battery powered system design.
+
+More details can be found in the Technical Reference Manual:
+https://www.ti.com/lit/pdf/spruiv7
+
+Boot Flow:
+--
+Below is the pictorial representation of boot flow:
+
+.. code-block:: text
+
+ ++
+ |TIFS| Main R5 |A53|
+ ++
+ |++ | | |
+ || Reset | | | |
+ |++ | | |
+ | : | | |
+ |++ | +---+ | |
+ || *ROM* |--|-->| Reset rls | | |
+ |++ | +---+ | |
+ ||| | : | |
+ || ROM | | : | |
+ ||services| | : | |
+ ||| | +-+ | |
+ ||| | | *R5 ROM* | | |
+ ||| | +-+ | |
+ |||<-|---|Load and auth| | |
+ ||| | | tiboot3.bin | | |
+ |++ | +-+ | |
+ |||<-|---| Load sysfw | | |
+ ||| | | part to TIFS| | |
+ ||| | | core| | |
+ ||| | +-+ | |
+ ||| | : | |
+ ||| | : | |
+ ||| | : | |
+ ||| | +-+ | |
+ ||| | | *R5 SPL* | | |
+ ||| | +-+ | |
+ ||| | |DDR | | |
+ ||| | | config| | |
+ ||| | +-+ | |
+ ||| | |Load | | |
+ ||| | | tispl.bin | | |
+ |||
