Re: [PATCH v2 15/28] dt-bindings: clk: Add dt-binding header for RV1126

2022-09-28 Thread Kever Yang 



On 2022/8/18 22:52, Jagan Teki wrote:

Add the dt-bindings header for the Rockchip RV1126, that gets shared
between the clock controller and the clock references in the dts.

Signed-off-by: Finley Xiao 
Signed-off-by: Jagan Teki 

Reviewed-by: Kever Yang 

Thanks,
- Kever

---
Changes for v2:
- update cru header

  .../dt-bindings/clock/rockchip,rv1126-cru.h   | 632 ++
  1 file changed, 632 insertions(+)
  create mode 100644 include/dt-bindings/clock/rockchip,rv1126-cru.h

diff --git a/include/dt-bindings/clock/rockchip,rv1126-cru.h 
b/include/dt-bindings/clock/rockchip,rv1126-cru.h
new file mode 100644
index 00..cfba8226de
--- /dev/null
+++ b/include/dt-bindings/clock/rockchip,rv1126-cru.h
@@ -0,0 +1,632 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 Rockchip Electronics Co. Ltd.
+ * Author: Finley Xiao 
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H
+
+/* pmucru-clocks indices */
+
+/* pll clocks */
+#define PLL_GPLL   1
+
+/* sclk (special clocks) */
+#define CLK_OSC0_DIV32K2
+#define CLK_RTC32K 3
+#define CLK_WIFI_DIV   4
+#define CLK_WIFI_OSC0  5
+#define CLK_WIFI   6
+#define CLK_PMU7
+#define SCLK_UART1_DIV 8
+#define SCLK_UART1_FRACDIV 9
+#define SCLK_UART1_MUX 10
+#define SCLK_UART1 11
+#define CLK_I2C0   12
+#define CLK_I2C2   13
+#define CLK_CAPTURE_PWM0   14
+#define CLK_PWM0   15
+#define CLK_CAPTURE_PWM1   16
+#define CLK_PWM1   17
+#define CLK_SPI0   18
+#define DBCLK_GPIO019
+#define CLK_PMUPVTM20
+#define CLK_CORE_PMUPVTM   21
+#define CLK_REF12M 22
+#define CLK_USBPHY_OTG_REF 23
+#define CLK_USBPHY_HOST_REF24
+#define CLK_REF24M 25
+#define CLK_MIPIDSIPHY_REF 26
+
+/* pclk */
+#define PCLK_PDPMU 30
+#define PCLK_PMU   31
+#define PCLK_UART1 32
+#define PCLK_I2C0  33
+#define PCLK_I2C2  34
+#define PCLK_PWM0  35
+#define PCLK_PWM1  36
+#define PCLK_SPI0  37
+#define PCLK_GPIO0 38
+#define PCLK_PMUSGRF   39
+#define PCLK_PMUGRF40
+#define PCLK_PMUCRU41
+#define PCLK_CHIPVEROTP42
+#define PCLK_PDPMU_NIU 43
+#define PCLK_PMUPVTM   44
+#define PCLK_SCRKEYGEN 45
+
+#define CLKPMU_NR_CLKS (PCLK_SCRKEYGEN + 1)
+
+/* cru-clocks indices */
+
+/* pll clocks */
+#define PLL_APLL   1
+#define PLL_DPLL   2
+#define PLL_CPLL   3
+#define PLL_HPLL   4
+
+/* sclk (special clocks) */
+#define ARMCLK 5
+#define USB480M6
+#define CLK_CORE_CPUPVTM   7
+#define CLK_CPUPVTM8
+#define CLK_SCR1   9
+#define CLK_SCR1_CORE  10
+#define CLK_SCR1_RTC   11
+#define CLK_SCR1_JTAG  12
+#define SCLK_UART0_DIV 13
+#define SCLK_UART0_FRAC14
+#define SCLK_UART0_MUX 15
+#define SCLK_UART0 16
+#define SCLK_UART2_DIV 17
+#define SCLK_UART2_FRAC18
+#define SCLK_UART2_MUX 19
+#define SCLK_UART2 20
+#define SCLK_UART3_DIV 21
+#define SCLK_UART3_FRAC22
+#define SCLK_UART3_MUX 23
+#define SCLK_UART3 24
+#define SCLK_UART4_DIV 25
+#define SCLK_UART4_FRAC26
+#define SCLK_UART4_MUX 27
+#define SCLK_UART4 28
+#define SCLK_UART5_DIV 29
+#define SCLK_UART5_FRAC30
+#define SCLK_UART5_MUX 31
+#define SCLK_UART5 32
+#define CLK_I2C1   33
+#define CLK_I2C3   34
+#define CLK_I2C4   35
+#define CLK_I2C5   36
+#define CLK_SPI1   37
+#define CLK_CAPTURE_PWM2   38
+#define CLK_PWM2   39
+#define DBCLK_GPIO140
+#define DBCLK_GPIO241
+#define DBCLK_GPIO342
+#define DBCLK_GPIO443
+#define CLK_SARADC 44
+#define CLK_TIMER0 45
+#define CLK_TIMER1 46
+#define CLK_TIMER2 47
+#define CLK_TIMER3 48
+#define CLK_TIMER4 49
+#define CLK_TIMER5 50
+#define CLK_CAN51
+#define CLK_NPU_TSADC  52
+#define CLK_NPU_TSADCPHY   53
+#define CLK_CPU_TSADC  54
+#define CLK_CPU_TSADCPHY   55
+#define CLK_CRYPTO_CORE56
+#define CLK_CRYPTO_PKA 57
+#define MCLK_I2S0_TX_DIV   58
+#define MCLK_I2S0_TX_FRACDIV   59
+#define MCLK_I2S0_TX_MUX   60
+#define MCLK_I2S0_TX   61
+#define MCLK_I2S0_RX_DIV   62
+#define MCLK_I2S0_RX_FRACDIV   63
+#define MCLK_I2S0_RX_MUX   64
+#define MCLK_I2S0_RX

[PATCH v2 15/28] dt-bindings: clk: Add dt-binding header for RV1126

2022-08-18 Thread Jagan Teki 
Add the dt-bindings header for the Rockchip RV1126, that gets shared
between the clock controller and the clock references in the dts.

Signed-off-by: Finley Xiao 
Signed-off-by: Jagan Teki 
---
Changes for v2:
- update cru header

 .../dt-bindings/clock/rockchip,rv1126-cru.h   | 632 ++
 1 file changed, 632 insertions(+)
 create mode 100644 include/dt-bindings/clock/rockchip,rv1126-cru.h

diff --git a/include/dt-bindings/clock/rockchip,rv1126-cru.h 
b/include/dt-bindings/clock/rockchip,rv1126-cru.h
new file mode 100644
index 00..cfba8226de
--- /dev/null
+++ b/include/dt-bindings/clock/rockchip,rv1126-cru.h
@@ -0,0 +1,632 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2019 Rockchip Electronics Co. Ltd.
+ * Author: Finley Xiao 
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H
+
+/* pmucru-clocks indices */
+
+/* pll clocks */
+#define PLL_GPLL   1
+
+/* sclk (special clocks) */
+#define CLK_OSC0_DIV32K2
+#define CLK_RTC32K 3
+#define CLK_WIFI_DIV   4
+#define CLK_WIFI_OSC0  5
+#define CLK_WIFI   6
+#define CLK_PMU7
+#define SCLK_UART1_DIV 8
+#define SCLK_UART1_FRACDIV 9
+#define SCLK_UART1_MUX 10
+#define SCLK_UART1 11
+#define CLK_I2C0   12
+#define CLK_I2C2   13
+#define CLK_CAPTURE_PWM0   14
+#define CLK_PWM0   15
+#define CLK_CAPTURE_PWM1   16
+#define CLK_PWM1   17
+#define CLK_SPI0   18
+#define DBCLK_GPIO019
+#define CLK_PMUPVTM20
+#define CLK_CORE_PMUPVTM   21
+#define CLK_REF12M 22
+#define CLK_USBPHY_OTG_REF 23
+#define CLK_USBPHY_HOST_REF24
+#define CLK_REF24M 25
+#define CLK_MIPIDSIPHY_REF 26
+
+/* pclk */
+#define PCLK_PDPMU 30
+#define PCLK_PMU   31
+#define PCLK_UART1 32
+#define PCLK_I2C0  33
+#define PCLK_I2C2  34
+#define PCLK_PWM0  35
+#define PCLK_PWM1  36
+#define PCLK_SPI0  37
+#define PCLK_GPIO0 38
+#define PCLK_PMUSGRF   39
+#define PCLK_PMUGRF40
+#define PCLK_PMUCRU41
+#define PCLK_CHIPVEROTP42
+#define PCLK_PDPMU_NIU 43
+#define PCLK_PMUPVTM   44
+#define PCLK_SCRKEYGEN 45
+
+#define CLKPMU_NR_CLKS (PCLK_SCRKEYGEN + 1)
+
+/* cru-clocks indices */
+
+/* pll clocks */
+#define PLL_APLL   1
+#define PLL_DPLL   2
+#define PLL_CPLL   3
+#define PLL_HPLL   4
+
+/* sclk (special clocks) */
+#define ARMCLK 5
+#define USB480M6
+#define CLK_CORE_CPUPVTM   7
+#define CLK_CPUPVTM8
+#define CLK_SCR1   9
+#define CLK_SCR1_CORE  10
+#define CLK_SCR1_RTC   11
+#define CLK_SCR1_JTAG  12
+#define SCLK_UART0_DIV 13
+#define SCLK_UART0_FRAC14
+#define SCLK_UART0_MUX 15
+#define SCLK_UART0 16
+#define SCLK_UART2_DIV 17
+#define SCLK_UART2_FRAC18
+#define SCLK_UART2_MUX 19
+#define SCLK_UART2 20
+#define SCLK_UART3_DIV 21
+#define SCLK_UART3_FRAC22
+#define SCLK_UART3_MUX 23
+#define SCLK_UART3 24
+#define SCLK_UART4_DIV 25
+#define SCLK_UART4_FRAC26
+#define SCLK_UART4_MUX 27
+#define SCLK_UART4 28
+#define SCLK_UART5_DIV 29
+#define SCLK_UART5_FRAC30
+#define SCLK_UART5_MUX 31
+#define SCLK_UART5 32
+#define CLK_I2C1   33
+#define CLK_I2C3   34
+#define CLK_I2C4   35
+#define CLK_I2C5   36
+#define CLK_SPI1   37
+#define CLK_CAPTURE_PWM2   38
+#define CLK_PWM2   39
+#define DBCLK_GPIO140
+#define DBCLK_GPIO241
+#define DBCLK_GPIO342
+#define DBCLK_GPIO443
+#define CLK_SARADC 44
+#define CLK_TIMER0 45
+#define CLK_TIMER1 46
+#define CLK_TIMER2 47
+#define CLK_TIMER3 48
+#define CLK_TIMER4 49
+#define CLK_TIMER5 50
+#define CLK_CAN51
+#define CLK_NPU_TSADC  52
+#define CLK_NPU_TSADCPHY   53
+#define CLK_CPU_TSADC  54
+#define CLK_CPU_TSADCPHY   55
+#define CLK_CRYPTO_CORE56
+#define CLK_CRYPTO_PKA 57
+#define MCLK_I2S0_TX_DIV   58
+#define MCLK_I2S0_TX_FRACDIV   59
+#define MCLK_I2S0_TX_MUX   60
+#define MCLK_I2S0_TX   61
+#define MCLK_I2S0_RX_DIV   62
+#define MCLK_I2S0_RX_FRACDIV   63
+#define MCLK_I2S0_RX_MUX   64
+#define MCLK_I2S0_RX   65
+#define MCLK_I2S0_TX_OUT2IO66
+#define MCLK_I2S0_RX_OUT2IO67
+#define MC