[PATCH v2 5/7] riscv: dts: Add device tree for Microchip Icicle Kit

2020-10-22 Thread Padmarao Begari 
Add device tree for Microchip PolarFire SoC Icicle Kit.

Signed-off-by: Padmarao Begari 
---
 arch/riscv/dts/Makefile  |   1 +
 arch/riscv/dts/microchip-icicle-kit-a000.dts | 426 +++
 2 files changed, 427 insertions(+)
 create mode 100644 arch/riscv/dts/microchip-icicle-kit-a000.dts

diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index 3a6f96c67d..48c43bd122 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -3,6 +3,7 @@
 dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
 dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
 dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
+dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-icicle-kit-a000.dtb
 
 targets += $(dtb-y)
 
diff --git a/arch/riscv/dts/microchip-icicle-kit-a000.dts 
b/arch/riscv/dts/microchip-icicle-kit-a000.dts
new file mode 100644
index 00..7110d2a78b
--- /dev/null
+++ b/arch/riscv/dts/microchip-icicle-kit-a000.dts
@@ -0,0 +1,426 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright (c) 2020 Microchip Technology Inc */
+
+/dts-v1/;
+#include "dt-bindings/clock/microchip,pfsoc-clock.h"
+
+/* Clock frequency (in Hz) of the rtcclk */
+#define RTCCLK_FREQ100
+
+/ {
+   #address-cells = <2>;
+   #size-cells = <2>;
+   model = "Microchip PolarFire-SoC";
+   compatible = "microchip,polarfire-soc";
+
+   aliases {
+   serial0 = &uart0;
+   ethernet0 = &emac1;
+   };
+
+   chosen {
+   stdout-path = "serial0";
+   };
+
+   cpucomplex: cpus {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   timebase-frequency = ;
+   cpu0: cpu@0 {
+   clocks = <&clkcfg CLK_CPU>;
+   compatible = "sifive,e51", "sifive,rocket0", "riscv";
+   device_type = "cpu";
+   i-cache-block-size = <64>;
+   i-cache-sets = <128>;
+   i-cache-size = <16384>;
+   reg = <0>;
+   riscv,isa = "rv64imac";
+   status = "disabled";
+   operating-points = <
+   /* kHz  uV */
+   60  110
+   30   95
+   15   75
+   >;
+   cpu0intc: interrupt-controller {
+   #interrupt-cells = <1>;
+   compatible = "riscv,cpu-intc";
+   interrupt-controller;
+   };
+   };
+   cpu1: cpu@1 {
+   clocks = <&clkcfg CLK_CPU>;
+   compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+   d-cache-block-size = <64>;
+   d-cache-sets = <64>;
+   d-cache-size = <32768>;
+   d-tlb-sets = <1>;
+   d-tlb-size = <32>;
+   device_type = "cpu";
+   i-cache-block-size = <64>;
+   i-cache-sets = <64>;
+   i-cache-size = <32768>;
+   i-tlb-sets = <1>;
+   i-tlb-size = <32>;
+   mmu-type = "riscv,sv39";
+   reg = <1>;
+   riscv,isa = "rv64imafdc";
+   tlb-split;
+   status = "okay";
+   operating-points = <
+   /* kHz  uV */
+   60  110
+   30   95
+   15   75
+   >;
+   cpu1intc: interrupt-controller {
+   #interrupt-cells = <1>;
+   compatible = "riscv,cpu-intc";
+   interrupt-controller;
+   };
+   };
+   cpu2: cpu@2 {
+   clocks = <&clkcfg CLK_CPU>;
+   compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
+   d-cache-block-size = <64>;
+   d-cache-sets = <64>;
+   d-cache-size = <32768>;
+   d-tlb-sets = <1>;
+   d-tlb-size = <32>;
+   device_type = "cpu";
+   i-cache-block-size = <64>;
+   i-cache-sets = <64>;
+   i-cache-size = <32768>;
+   i-tlb-sets = <1>;
+   i-tlb-size = <32>;
+   mmu-type = "riscv,sv39";
+   reg = <2>;
+   riscv,isa = "rv64imafdc";
+   tlb-split;
+

Re: [PATCH v2 5/7] riscv: dts: Add device tree for Microchip Icicle Kit

2020-10-24 Thread Anup Patel 
On Thu, Oct 22, 2020 at 12:53 PM Padmarao Begari
 wrote:
>
> Add device tree for Microchip PolarFire SoC Icicle Kit.
>
> Signed-off-by: Padmarao Begari 
> ---
>  arch/riscv/dts/Makefile  |   1 +
>  arch/riscv/dts/microchip-icicle-kit-a000.dts | 426 +++
>  2 files changed, 427 insertions(+)
>  create mode 100644 arch/riscv/dts/microchip-icicle-kit-a000.dts
>
> diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
> index 3a6f96c67d..48c43bd122 100644
> --- a/arch/riscv/dts/Makefile
> +++ b/arch/riscv/dts/Makefile
> @@ -3,6 +3,7 @@
>  dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
>  dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
>  dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
> +dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-icicle-kit-a000.dtb
>
>  targets += $(dtb-y)
>
> diff --git a/arch/riscv/dts/microchip-icicle-kit-a000.dts 
> b/arch/riscv/dts/microchip-icicle-kit-a000.dts
> new file mode 100644
> index 00..7110d2a78b
> --- /dev/null
> +++ b/arch/riscv/dts/microchip-icicle-kit-a000.dts
> @@ -0,0 +1,426 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/* Copyright (c) 2020 Microchip Technology Inc */
> +
> +/dts-v1/;
> +#include "dt-bindings/clock/microchip,pfsoc-clock.h"
> +
> +/* Clock frequency (in Hz) of the rtcclk */
> +#define RTCCLK_FREQ100
> +
> +/ {
> +   #address-cells = <2>;
> +   #size-cells = <2>;
> +   model = "Microchip PolarFire-SoC";
> +   compatible = "microchip,polarfire-soc";
> +
> +   aliases {
> +   serial0 = &uart0;
> +   ethernet0 = &emac1;
> +   };
> +
> +   chosen {
> +   stdout-path = "serial0";
> +   };
> +
> +   cpucomplex: cpus {
> +   #address-cells = <1>;
> +   #size-cells = <0>;
> +   timebase-frequency = ;
> +   cpu0: cpu@0 {
> +   clocks = <&clkcfg CLK_CPU>;
> +   compatible = "sifive,e51", "sifive,rocket0", "riscv";
> +   device_type = "cpu";
> +   i-cache-block-size = <64>;
> +   i-cache-sets = <128>;
> +   i-cache-size = <16384>;
> +   reg = <0>;
> +   riscv,isa = "rv64imac";
> +   status = "disabled";
> +   operating-points = <
> +   /* kHz  uV */
> +   60  110
> +   30   95
> +   15   75
> +   >;
> +   cpu0intc: interrupt-controller {
> +   #interrupt-cells = <1>;
> +   compatible = "riscv,cpu-intc";
> +   interrupt-controller;
> +   };
> +   };
> +   cpu1: cpu@1 {
> +   clocks = <&clkcfg CLK_CPU>;
> +   compatible = "sifive,u54-mc", "sifive,rocket0", 
> "riscv";
> +   d-cache-block-size = <64>;
> +   d-cache-sets = <64>;
> +   d-cache-size = <32768>;
> +   d-tlb-sets = <1>;
> +   d-tlb-size = <32>;
> +   device_type = "cpu";
> +   i-cache-block-size = <64>;
> +   i-cache-sets = <64>;
> +   i-cache-size = <32768>;
> +   i-tlb-sets = <1>;
> +   i-tlb-size = <32>;
> +   mmu-type = "riscv,sv39";
> +   reg = <1>;
> +   riscv,isa = "rv64imafdc";
> +   tlb-split;
> +   status = "okay";
> +   operating-points = <
> +   /* kHz  uV */
> +   60  110
> +   30   95
> +   15   75
> +   >;
> +   cpu1intc: interrupt-controller {
> +   #interrupt-cells = <1>;
> +   compatible = "riscv,cpu-intc";
> +   interrupt-controller;
> +   };
> +   };
> +   cpu2: cpu@2 {
> +   clocks = <&clkcfg CLK_CPU>;
> +   compatible = "sifive,u54-mc", "sifive,rocket0", 
> "riscv";
> +   d-cache-block-size = <64>;
> +   d-cache-sets = <64>;
> +   d-cache-size = <32768>;
> +   d-tlb-sets = <1>;
> +   d-tlb-size = <32>;
> +   device_type = "cpu";
> +   i-cache-block-size = <64>;
> +   i-cache-sets = <64>;
> +

Re: [PATCH v2 5/7] riscv: dts: Add device tree for Microchip Icicle Kit

2020-10-26 Thread Bin Meng 
On Thu, Oct 22, 2020 at 3:23 PM Padmarao Begari
 wrote:
>
> Add device tree for Microchip PolarFire SoC Icicle Kit.
>
> Signed-off-by: Padmarao Begari 
> ---
>  arch/riscv/dts/Makefile  |   1 +
>  arch/riscv/dts/microchip-icicle-kit-a000.dts | 426 +++
>  2 files changed, 427 insertions(+)
>  create mode 100644 arch/riscv/dts/microchip-icicle-kit-a000.dts
>
> diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
> index 3a6f96c67d..48c43bd122 100644
> --- a/arch/riscv/dts/Makefile
> +++ b/arch/riscv/dts/Makefile
> @@ -3,6 +3,7 @@
>  dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
>  dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
>  dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
> +dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-icicle-kit-a000.dtb
>
>  targets += $(dtb-y)
>
> diff --git a/arch/riscv/dts/microchip-icicle-kit-a000.dts 
> b/arch/riscv/dts/microchip-icicle-kit-a000.dts
> new file mode 100644
> index 00..7110d2a78b
> --- /dev/null
> +++ b/arch/riscv/dts/microchip-icicle-kit-a000.dts
> @@ -0,0 +1,426 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/* Copyright (c) 2020 Microchip Technology Inc */
> +
> +/dts-v1/;
> +#include "dt-bindings/clock/microchip,pfsoc-clock.h"
> +
> +/* Clock frequency (in Hz) of the rtcclk */
> +#define RTCCLK_FREQ100
> +
> +/ {
> +   #address-cells = <2>;
> +   #size-cells = <2>;
> +   model = "Microchip PolarFire-SoC";
> +   compatible = "microchip,polarfire-soc";
> +
> +   aliases {
> +   serial0 = &uart0;
> +   ethernet0 = &emac1;
> +   };
> +
> +   chosen {
> +   stdout-path = "serial0";
> +   };
> +
> +   cpucomplex: cpus {
> +   #address-cells = <1>;
> +   #size-cells = <0>;
> +   timebase-frequency = ;
> +   cpu0: cpu@0 {
> +   clocks = <&clkcfg CLK_CPU>;
> +   compatible = "sifive,e51", "sifive,rocket0", "riscv";
> +   device_type = "cpu";
> +   i-cache-block-size = <64>;
> +   i-cache-sets = <128>;
> +   i-cache-size = <16384>;
> +   reg = <0>;
> +   riscv,isa = "rv64imac";
> +   status = "disabled";
> +   operating-points = <
> +   /* kHz  uV */
> +   60  110
> +   30   95
> +   15   75
> +   >;
> +   cpu0intc: interrupt-controller {
> +   #interrupt-cells = <1>;
> +   compatible = "riscv,cpu-intc";
> +   interrupt-controller;
> +   };
> +   };
> +   cpu1: cpu@1 {
> +   clocks = <&clkcfg CLK_CPU>;
> +   compatible = "sifive,u54-mc", "sifive,rocket0", 
> "riscv";
> +   d-cache-block-size = <64>;
> +   d-cache-sets = <64>;
> +   d-cache-size = <32768>;
> +   d-tlb-sets = <1>;
> +   d-tlb-size = <32>;
> +   device_type = "cpu";
> +   i-cache-block-size = <64>;
> +   i-cache-sets = <64>;
> +   i-cache-size = <32768>;
> +   i-tlb-sets = <1>;
> +   i-tlb-size = <32>;
> +   mmu-type = "riscv,sv39";
> +   reg = <1>;
> +   riscv,isa = "rv64imafdc";
> +   tlb-split;
> +   status = "okay";
> +   operating-points = <
> +   /* kHz  uV */
> +   60  110
> +   30   95
> +   15   75
> +   >;
> +   cpu1intc: interrupt-controller {
> +   #interrupt-cells = <1>;
> +   compatible = "riscv,cpu-intc";
> +   interrupt-controller;
> +   };
> +   };
> +   cpu2: cpu@2 {
> +   clocks = <&clkcfg CLK_CPU>;
> +   compatible = "sifive,u54-mc", "sifive,rocket0", 
> "riscv";
> +   d-cache-block-size = <64>;
> +   d-cache-sets = <64>;
> +   d-cache-size = <32768>;
> +   d-tlb-sets = <1>;
> +   d-tlb-size = <32>;
> +   device_type = "cpu";
> +   i-cache-block-size = <64>;
> +   i-cache-sets = <64>;
> +

Re: [PATCH v2 5/7] riscv: dts: Add device tree for Microchip Icicle Kit

2020-10-26 Thread Atish Patra 
On Mon, Oct 26, 2020 at 6:14 AM Bin Meng  wrote:
>
> On Thu, Oct 22, 2020 at 3:23 PM Padmarao Begari
>  wrote:
> >
> > Add device tree for Microchip PolarFire SoC Icicle Kit.
> >
> > Signed-off-by: Padmarao Begari 
> > ---
> >  arch/riscv/dts/Makefile  |   1 +
> >  arch/riscv/dts/microchip-icicle-kit-a000.dts | 426 +++
> >  2 files changed, 427 insertions(+)
> >  create mode 100644 arch/riscv/dts/microchip-icicle-kit-a000.dts
> >
> > diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
> > index 3a6f96c67d..48c43bd122 100644
> > --- a/arch/riscv/dts/Makefile
> > +++ b/arch/riscv/dts/Makefile
> > @@ -3,6 +3,7 @@
> >  dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
> >  dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
> >  dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
> > +dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-icicle-kit-a000.dtb
> >
> >  targets += $(dtb-y)
> >
> > diff --git a/arch/riscv/dts/microchip-icicle-kit-a000.dts 
> > b/arch/riscv/dts/microchip-icicle-kit-a000.dts
> > new file mode 100644
> > index 00..7110d2a78b
> > --- /dev/null
> > +++ b/arch/riscv/dts/microchip-icicle-kit-a000.dts
> > @@ -0,0 +1,426 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/* Copyright (c) 2020 Microchip Technology Inc */
> > +
> > +/dts-v1/;
> > +#include "dt-bindings/clock/microchip,pfsoc-clock.h"
> > +
> > +/* Clock frequency (in Hz) of the rtcclk */
> > +#define RTCCLK_FREQ100
> > +
> > +/ {
> > +   #address-cells = <2>;
> > +   #size-cells = <2>;
> > +   model = "Microchip PolarFire-SoC";
> > +   compatible = "microchip,polarfire-soc";
> > +
> > +   aliases {
> > +   serial0 = &uart0;
> > +   ethernet0 = &emac1;
> > +   };
> > +
> > +   chosen {
> > +   stdout-path = "serial0";
> > +   };
> > +
> > +   cpucomplex: cpus {
> > +   #address-cells = <1>;
> > +   #size-cells = <0>;
> > +   timebase-frequency = ;
> > +   cpu0: cpu@0 {
> > +   clocks = <&clkcfg CLK_CPU>;
> > +   compatible = "sifive,e51", "sifive,rocket0", 
> > "riscv";
> > +   device_type = "cpu";
> > +   i-cache-block-size = <64>;
> > +   i-cache-sets = <128>;
> > +   i-cache-size = <16384>;
> > +   reg = <0>;
> > +   riscv,isa = "rv64imac";
> > +   status = "disabled";
> > +   operating-points = <
> > +   /* kHz  uV */
> > +   60  110
> > +   30   95
> > +   15   75
> > +   >;
> > +   cpu0intc: interrupt-controller {
> > +   #interrupt-cells = <1>;
> > +   compatible = "riscv,cpu-intc";
> > +   interrupt-controller;
> > +   };
> > +   };
> > +   cpu1: cpu@1 {
> > +   clocks = <&clkcfg CLK_CPU>;
> > +   compatible = "sifive,u54-mc", "sifive,rocket0", 
> > "riscv";
> > +   d-cache-block-size = <64>;
> > +   d-cache-sets = <64>;
> > +   d-cache-size = <32768>;
> > +   d-tlb-sets = <1>;
> > +   d-tlb-size = <32>;
> > +   device_type = "cpu";
> > +   i-cache-block-size = <64>;
> > +   i-cache-sets = <64>;
> > +   i-cache-size = <32768>;
> > +   i-tlb-sets = <1>;
> > +   i-tlb-size = <32>;
> > +   mmu-type = "riscv,sv39";
> > +   reg = <1>;
> > +   riscv,isa = "rv64imafdc";
> > +   tlb-split;
> > +   status = "okay";
> > +   operating-points = <
> > +   /* kHz  uV */
> > +   60  110
> > +   30   95
> > +   15   75
> > +   >;
> > +   cpu1intc: interrupt-controller {
> > +   #interrupt-cells = <1>;
> > +   compatible = "riscv,cpu-intc";
> > +   interrupt-controller;
> > +   };
> > +   };
> > +   cpu2: cpu@2 {
> > +   clocks = <&clkcfg CLK_CPU>;
> > +   compatible = "sifive,u54-mc", "sifive,rocket0", 
> > "riscv";
> > +   d-cache-block-size = <64>;
> > +   d-cache-sets = <64>;
> > +

Re: [PATCH v2 5/7] riscv: dts: Add device tree for Microchip Icicle Kit

2020-10-27 Thread Padmarao Begari 
Hi Anup,

On Sun, Oct 25, 2020 at 11:20 AM Anup Patel  wrote:

> On Thu, Oct 22, 2020 at 12:53 PM Padmarao Begari
>  wrote:
> >
> > Add device tree for Microchip PolarFire SoC Icicle Kit.
> >
> > Signed-off-by: Padmarao Begari 
> > ---
> >  arch/riscv/dts/Makefile  |   1 +
> >  arch/riscv/dts/microchip-icicle-kit-a000.dts | 426 +++
> >  2 files changed, 427 insertions(+)
> >  create mode 100644 arch/riscv/dts/microchip-icicle-kit-a000.dts
> >
> > diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
> > index 3a6f96c67d..48c43bd122 100644
> > --- a/arch/riscv/dts/Makefile
> > +++ b/arch/riscv/dts/Makefile
> > @@ -3,6 +3,7 @@
> >  dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
> >  dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
> >  dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
> > +dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-icicle-kit-a000.dtb
> >
> >  targets += $(dtb-y)
> >
> > diff --git a/arch/riscv/dts/microchip-icicle-kit-a000.dts
> b/arch/riscv/dts/microchip-icicle-kit-a000.dts
> > new file mode 100644
> > index 00..7110d2a78b
> > --- /dev/null
> > +++ b/arch/riscv/dts/microchip-icicle-kit-a000.dts
> > @@ -0,0 +1,426 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/* Copyright (c) 2020 Microchip Technology Inc */
> > +
> > +/dts-v1/;
> > +#include "dt-bindings/clock/microchip,pfsoc-clock.h"
> > +
> > +/* Clock frequency (in Hz) of the rtcclk */
> > +#define RTCCLK_FREQ100
> > +
> > +/ {
> > +   #address-cells = <2>;
> > +   #size-cells = <2>;
> > +   model = "Microchip PolarFire-SoC";
> > +   compatible = "microchip,polarfire-soc";
> > +
> > +   aliases {
> > +   serial0 = &uart0;
> > +   ethernet0 = &emac1;
> > +   };
> > +
> > +   chosen {
> > +   stdout-path = "serial0";
> > +   };
> > +
> > +   cpucomplex: cpus {
> > +   #address-cells = <1>;
> > +   #size-cells = <0>;
> > +   timebase-frequency = ;
> > +   cpu0: cpu@0 {
> > +   clocks = <&clkcfg CLK_CPU>;
> > +   compatible = "sifive,e51", "sifive,rocket0",
> "riscv";
> > +   device_type = "cpu";
> > +   i-cache-block-size = <64>;
> > +   i-cache-sets = <128>;
> > +   i-cache-size = <16384>;
> > +   reg = <0>;
> > +   riscv,isa = "rv64imac";
> > +   status = "disabled";
> > +   operating-points = <
> > +   /* kHz  uV */
> > +   60  110
> > +   30   95
> > +   15   75
> > +   >;
> > +   cpu0intc: interrupt-controller {
> > +   #interrupt-cells = <1>;
> > +   compatible = "riscv,cpu-intc";
> > +   interrupt-controller;
> > +   };
> > +   };
> > +   cpu1: cpu@1 {
> > +   clocks = <&clkcfg CLK_CPU>;
> > +   compatible = "sifive,u54-mc", "sifive,rocket0",
> "riscv";
> > +   d-cache-block-size = <64>;
> > +   d-cache-sets = <64>;
> > +   d-cache-size = <32768>;
> > +   d-tlb-sets = <1>;
> > +   d-tlb-size = <32>;
> > +   device_type = "cpu";
> > +   i-cache-block-size = <64>;
> > +   i-cache-sets = <64>;
> > +   i-cache-size = <32768>;
> > +   i-tlb-sets = <1>;
> > +   i-tlb-size = <32>;
> > +   mmu-type = "riscv,sv39";
> > +   reg = <1>;
> > +   riscv,isa = "rv64imafdc";
> > +   tlb-split;
> > +   status = "okay";
> > +   operating-points = <
> > +   /* kHz  uV */
> > +   60  110
> > +   30   95
> > +   15   75
> > +   >;
> > +   cpu1intc: interrupt-controller {
> > +   #interrupt-cells = <1>;
> > +   compatible = "riscv,cpu-intc";
> > +   interrupt-controller;
> > +   };
> > +   };
> > +   cpu2: cpu@2 {
> > +   clocks = <&clkcfg CLK_CPU>;
> > +   compatible = "sifive,u54-mc", "sifive,rocket0",
> "riscv";
> > +   d-cache-block-size = <64>;
> > +   d-cache-sets = <64>;
> > +

Re: [PATCH v2 5/7] riscv: dts: Add device tree for Microchip Icicle Kit

2020-10-27 Thread Padmarao Begari 
Hi Bin,

On Mon, Oct 26, 2020 at 6:44 PM Bin Meng  wrote:

> On Thu, Oct 22, 2020 at 3:23 PM Padmarao Begari
>  wrote:
> >
> > Add device tree for Microchip PolarFire SoC Icicle Kit.
> >
> > Signed-off-by: Padmarao Begari 
> > ---
> >  arch/riscv/dts/Makefile  |   1 +
> >  arch/riscv/dts/microchip-icicle-kit-a000.dts | 426 +++
> >  2 files changed, 427 insertions(+)
> >  create mode 100644 arch/riscv/dts/microchip-icicle-kit-a000.dts
> >
> > diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
> > index 3a6f96c67d..48c43bd122 100644
> > --- a/arch/riscv/dts/Makefile
> > +++ b/arch/riscv/dts/Makefile
> > @@ -3,6 +3,7 @@
> >  dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
> >  dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
> >  dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
> > +dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-icicle-kit-a000.dtb
> >
> >  targets += $(dtb-y)
> >
> > diff --git a/arch/riscv/dts/microchip-icicle-kit-a000.dts
> b/arch/riscv/dts/microchip-icicle-kit-a000.dts
> > new file mode 100644
> > index 00..7110d2a78b
> > --- /dev/null
> > +++ b/arch/riscv/dts/microchip-icicle-kit-a000.dts
> > @@ -0,0 +1,426 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/* Copyright (c) 2020 Microchip Technology Inc */
> > +
> > +/dts-v1/;
> > +#include "dt-bindings/clock/microchip,pfsoc-clock.h"
> > +
> > +/* Clock frequency (in Hz) of the rtcclk */
> > +#define RTCCLK_FREQ100
> > +
> > +/ {
> > +   #address-cells = <2>;
> > +   #size-cells = <2>;
> > +   model = "Microchip PolarFire-SoC";
> > +   compatible = "microchip,polarfire-soc";
> > +
> > +   aliases {
> > +   serial0 = &uart0;
> > +   ethernet0 = &emac1;
> > +   };
> > +
> > +   chosen {
> > +   stdout-path = "serial0";
> > +   };
> > +
> > +   cpucomplex: cpus {
> > +   #address-cells = <1>;
> > +   #size-cells = <0>;
> > +   timebase-frequency = ;
> > +   cpu0: cpu@0 {
> > +   clocks = <&clkcfg CLK_CPU>;
> > +   compatible = "sifive,e51", "sifive,rocket0",
> "riscv";
> > +   device_type = "cpu";
> > +   i-cache-block-size = <64>;
> > +   i-cache-sets = <128>;
> > +   i-cache-size = <16384>;
> > +   reg = <0>;
> > +   riscv,isa = "rv64imac";
> > +   status = "disabled";
> > +   operating-points = <
> > +   /* kHz  uV */
> > +   60  110
> > +   30   95
> > +   15   75
> > +   >;
> > +   cpu0intc: interrupt-controller {
> > +   #interrupt-cells = <1>;
> > +   compatible = "riscv,cpu-intc";
> > +   interrupt-controller;
> > +   };
> > +   };
> > +   cpu1: cpu@1 {
> > +   clocks = <&clkcfg CLK_CPU>;
> > +   compatible = "sifive,u54-mc", "sifive,rocket0",
> "riscv";
> > +   d-cache-block-size = <64>;
> > +   d-cache-sets = <64>;
> > +   d-cache-size = <32768>;
> > +   d-tlb-sets = <1>;
> > +   d-tlb-size = <32>;
> > +   device_type = "cpu";
> > +   i-cache-block-size = <64>;
> > +   i-cache-sets = <64>;
> > +   i-cache-size = <32768>;
> > +   i-tlb-sets = <1>;
> > +   i-tlb-size = <32>;
> > +   mmu-type = "riscv,sv39";
> > +   reg = <1>;
> > +   riscv,isa = "rv64imafdc";
> > +   tlb-split;
> > +   status = "okay";
> > +   operating-points = <
> > +   /* kHz  uV */
> > +   60  110
> > +   30   95
> > +   15   75
> > +   >;
> > +   cpu1intc: interrupt-controller {
> > +   #interrupt-cells = <1>;
> > +   compatible = "riscv,cpu-intc";
> > +   interrupt-controller;
> > +   };
> > +   };
> > +   cpu2: cpu@2 {
> > +   clocks = <&clkcfg CLK_CPU>;
> > +   compatible = "sifive,u54-mc", "sifive,rocket0",
> "riscv";
> > +   d-cache-block-size = <64>;
> > +   d-cache-sets = <64>;
> > +

Re: [PATCH v2 5/7] riscv: dts: Add device tree for Microchip Icicle Kit

2020-10-27 Thread Padmarao Begari 
Hi Atish,

On Tue, Oct 27, 2020 at 6:27 AM Atish Patra  wrote:

> On Mon, Oct 26, 2020 at 6:14 AM Bin Meng  wrote:
> >
> > On Thu, Oct 22, 2020 at 3:23 PM Padmarao Begari
> >  wrote:
> > >
> > > Add device tree for Microchip PolarFire SoC Icicle Kit.
> > >
> > > Signed-off-by: Padmarao Begari 
> > > ---
> > >  arch/riscv/dts/Makefile  |   1 +
> > >  arch/riscv/dts/microchip-icicle-kit-a000.dts | 426 +++
> > >  2 files changed, 427 insertions(+)
> > >  create mode 100644 arch/riscv/dts/microchip-icicle-kit-a000.dts
> > >
> > > diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
> > > index 3a6f96c67d..48c43bd122 100644
> > > --- a/arch/riscv/dts/Makefile
> > > +++ b/arch/riscv/dts/Makefile
> > > @@ -3,6 +3,7 @@
> > >  dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
> > >  dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
> > >  dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
> > > +dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-icicle-kit-a000.dtb
> > >
> > >  targets += $(dtb-y)
> > >
> > > diff --git a/arch/riscv/dts/microchip-icicle-kit-a000.dts
> b/arch/riscv/dts/microchip-icicle-kit-a000.dts
> > > new file mode 100644
> > > index 00..7110d2a78b
> > > --- /dev/null
> > > +++ b/arch/riscv/dts/microchip-icicle-kit-a000.dts
> > > @@ -0,0 +1,426 @@
> > > +// SPDX-License-Identifier: GPL-2.0+
> > > +/* Copyright (c) 2020 Microchip Technology Inc */
> > > +
> > > +/dts-v1/;
> > > +#include "dt-bindings/clock/microchip,pfsoc-clock.h"
> > > +
> > > +/* Clock frequency (in Hz) of the rtcclk */
> > > +#define RTCCLK_FREQ100
> > > +
> > > +/ {
> > > +   #address-cells = <2>;
> > > +   #size-cells = <2>;
> > > +   model = "Microchip PolarFire-SoC";
> > > +   compatible = "microchip,polarfire-soc";
> > > +
> > > +   aliases {
> > > +   serial0 = &uart0;
> > > +   ethernet0 = &emac1;
> > > +   };
> > > +
> > > +   chosen {
> > > +   stdout-path = "serial0";
> > > +   };
> > > +
> > > +   cpucomplex: cpus {
> > > +   #address-cells = <1>;
> > > +   #size-cells = <0>;
> > > +   timebase-frequency = ;
> > > +   cpu0: cpu@0 {
> > > +   clocks = <&clkcfg CLK_CPU>;
> > > +   compatible = "sifive,e51", "sifive,rocket0",
> "riscv";
> > > +   device_type = "cpu";
> > > +   i-cache-block-size = <64>;
> > > +   i-cache-sets = <128>;
> > > +   i-cache-size = <16384>;
> > > +   reg = <0>;
> > > +   riscv,isa = "rv64imac";
> > > +   status = "disabled";
> > > +   operating-points = <
> > > +   /* kHz  uV */
> > > +   60  110
> > > +   30   95
> > > +   15   75
> > > +   >;
> > > +   cpu0intc: interrupt-controller {
> > > +   #interrupt-cells = <1>;
> > > +   compatible = "riscv,cpu-intc";
> > > +   interrupt-controller;
> > > +   };
> > > +   };
> > > +   cpu1: cpu@1 {
> > > +   clocks = <&clkcfg CLK_CPU>;
> > > +   compatible = "sifive,u54-mc",
> "sifive,rocket0", "riscv";
> > > +   d-cache-block-size = <64>;
> > > +   d-cache-sets = <64>;
> > > +   d-cache-size = <32768>;
> > > +   d-tlb-sets = <1>;
> > > +   d-tlb-size = <32>;
> > > +   device_type = "cpu";
> > > +   i-cache-block-size = <64>;
> > > +   i-cache-sets = <64>;
> > > +   i-cache-size = <32768>;
> > > +   i-tlb-sets = <1>;
> > > +   i-tlb-size = <32>;
> > > +   mmu-type = "riscv,sv39";
> > > +   reg = <1>;
> > > +   riscv,isa = "rv64imafdc";
> > > +   tlb-split;
> > > +   status = "okay";
> > > +   operating-points = <
> > > +   /* kHz  uV */
> > > +   60  110
> > > +   30   95
> > > +   15   75
> > > +   >;
> > > +   cpu1intc: interrupt-controller {
> > > +   #interrupt-cells = <1>;
> > > +   compatible = "riscv,cpu-intc";
> > > +   interrupt-controller;
> > > +   };
> > > +   };
> > > +