Re: [PATCH v2 7/7] doc: board: Add Microchip MPFS Icicle Kit doc

2020-11-04 Thread Padmarao Begari 
On Sun, Oct 25, 2020 at 12:24 PM Anup Patel  wrote:

> On Thu, Oct 22, 2020 at 1:22 PM Padmarao Begari
>  wrote:
> >
> > This doc describes the procedure to build, flash and
> > boot Linux using U-boot on Microchip MPFS Icicle Kit.
> >
> > Signed-off-by: Padmarao Begari 
> > ---
> >  doc/board/index.rst |   1 +
> >  doc/board/microchip/index.rst   |   9 +
> >  doc/board/microchip/mpfs_icicle.rst | 605 
> >  3 files changed, 615 insertions(+)
> >  create mode 100644 doc/board/microchip/index.rst
> >  create mode 100644 doc/board/microchip/mpfs_icicle.rst
> >
> > diff --git a/doc/board/index.rst b/doc/board/index.rst
> > index 63935abcd7..e50a78d752 100644
> > --- a/doc/board/index.rst
> > +++ b/doc/board/index.rst
> > @@ -15,6 +15,7 @@ Board-specific doc
> > freescale/index
> > google/index
> > intel/index
> > +   microchip/index
> > renesas/index
> > rockchip/index
> > sifive/index
> > diff --git a/doc/board/microchip/index.rst
> b/doc/board/microchip/index.rst
> > new file mode 100644
> > index 00..b09e6788af
> > --- /dev/null
> > +++ b/doc/board/microchip/index.rst
> > @@ -0,0 +1,9 @@
> > +.. SPDX-License-Identifier: GPL-2.0+
> > +
> > +Microchip
> > +==
> > +
> > +.. toctree::
> > +   :maxdepth: 2
> > +
> > +   mpfs_icicle
> > diff --git a/doc/board/microchip/mpfs_icicle.rst
> b/doc/board/microchip/mpfs_icicle.rst
> > new file mode 100644
> > index 00..a4876b02f7
> > --- /dev/null
> > +++ b/doc/board/microchip/mpfs_icicle.rst
> > @@ -0,0 +1,605 @@
> > +.. SPDX-License-Identifier: GPL-2.0+
> > +
> > +Microchip PolarFire SoC Icicle Kit
> > +==
> > +
> > +RISC-V PolarFire SoC
> > +-
> > +The PolarFire SoC is the 4+1 64-bit RISC-V SoC from Microchip.
> > +
> > +The Icicle Kit development platform is based on PolarFire SoC and
> capable
> > +of running Linux.
> > +
> > +Mainline support
> > +
> > +The support for following drivers are already enabled:
> > +
> > +1. NS16550 UART Driver.
> > +2. Microchip Clock Driver.
> > +3. Cadence MACB ethernet driver for networking support.
> > +4. Cadence MMC Driver for eMMC/SD support.
> > +
> > +Booting from eMMC using HSS
> > +---
> > +
> > +Building
> > +
> > +
> > +1. Add the RISC-V toolchain to your PATH.
> > +2. Setup ARCH & cross compilation environment variable:
> > +
> > +.. code-block:: none
> > +
> > +   export CROSS_COMPILE=
> > +
> > +3. make microchip_mpfs_icicle_defconfig
> > +4. make
> > +
> > +Flashing
> > +
> > +
> > +The current U-Boot port is supported in S-mode only and loaded from
> DRAM.
> > +
> > +A prior stage M-mode firmware/bootloader (e.g HSS with OpenSBI) is
> required to
> > +boot the u-boot.bin in S-mode.
> > +
> > +Currently, the u-boot.bin is used as a payload of the HSS firmware.
> > +
> > +You will be creating a payload from `u-boot-dtb.bin`.
> > +Copy this file to the toplevel HSS (Hart Software Services) directory.
>
> The HSS firmware has a very old OpenSBI linked to it as a library. The
> OpenSBI
> is a moving target and a lot of features/fixes keep adding to OpenSBI.
>
> To tackle this, latest HSS has a compile time option for custom boot flow
> . The
> HSS custom boot-flow allows us to:
> 1. Use OpenSBI generic platform fw_payload.bin (with u-boot.bin embedded)
> as
> HSS payload
> 2. Use U-Boot SPL (in-future) as HSS payload
>
> I am able of use latest OpenSBI generic platform and U-Boot S-mode without
> any issues, to try this:
> 1) Compile u-boot.bin with this series
> 2) Compile OpenSBI generic fw_payload.bin using:
> make PLATFORM=generic FW_PAYLOAD_PATH=/u-boot.bin
> FW_FDT_PATH=/arch/riscv/dts/microchip-icicle-kit-a000.dtb
>
> > +
> > +Creating the HSS payload
> > +
>
> Please have a separate section for steps to compile HSS software for
> both Microchip boot-flow and Custom boot-flow.
>
>
ok


> This section describe how to create HSS payload for both Microchip
> boot-flow and Custom boot-flow
>
>
ok


> > +
> > +Please refer to HSS documenation to build the HSS firmware.
> > +(Note: HSS git repo is at
> > +https://github.com/polarfire-soc/hart-software-services/blob/master
> > +/tools/hss-payload-generator/README.md)
>
> Compiling HSS is quite simple. Please provide explicit steps here itself.
>
> > +
> > +Once the payload binary is generated, it should be copied to the eMMC.
> > +
> > +FPGA design with HSS programming file
> > +-
> > +
> https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards
> >
> +/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md
> > +
> > +The HSS firmware runs from the PolarFire SoC eNVM on reset.
> > +
> > +eMMC
> > +
> > +Program eMMC with payload binary is explained in the PolarFire SoC
> documentation.
>
> The HSS always picks up next stage (i.e. HSS payload) from a
> particular GPT

Re: [PATCH v2 7/7] doc: board: Add Microchip MPFS Icicle Kit doc

2020-11-04 Thread Padmarao Begari 
On Sat, Oct 24, 2020 at 9:07 PM Jagan Teki 
wrote:

> On Thu, Oct 22, 2020 at 1:22 PM Padmarao Begari
>  wrote:
> >
> > This doc describes the procedure to build, flash and
> > boot Linux using U-boot on Microchip MPFS Icicle Kit.
> >
> > Signed-off-by: Padmarao Begari 
> > ---
> >  doc/board/index.rst |   1 +
> >  doc/board/microchip/index.rst   |   9 +
> >  doc/board/microchip/mpfs_icicle.rst | 605 
> >  3 files changed, 615 insertions(+)
> >  create mode 100644 doc/board/microchip/index.rst
> >  create mode 100644 doc/board/microchip/mpfs_icicle.rst
> >
> > diff --git a/doc/board/index.rst b/doc/board/index.rst
> > index 63935abcd7..e50a78d752 100644
> > --- a/doc/board/index.rst
> > +++ b/doc/board/index.rst
> > @@ -15,6 +15,7 @@ Board-specific doc
> > freescale/index
> > google/index
> > intel/index
> > +   microchip/index
> > renesas/index
> > rockchip/index
> > sifive/index
> > diff --git a/doc/board/microchip/index.rst
> b/doc/board/microchip/index.rst
> > new file mode 100644
> > index 00..b09e6788af
> > --- /dev/null
> > +++ b/doc/board/microchip/index.rst
> > @@ -0,0 +1,9 @@
> > +.. SPDX-License-Identifier: GPL-2.0+
> > +
> > +Microchip
> > +==
> > +
> > +.. toctree::
> > +   :maxdepth: 2
> > +
> > +   mpfs_icicle
> > diff --git a/doc/board/microchip/mpfs_icicle.rst
> b/doc/board/microchip/mpfs_icicle.rst
> > new file mode 100644
> > index 00..a4876b02f7
> > --- /dev/null
> > +++ b/doc/board/microchip/mpfs_icicle.rst
> > @@ -0,0 +1,605 @@
> > +.. SPDX-License-Identifier: GPL-2.0+
> > +
> > +Microchip PolarFire SoC Icicle Kit
> > +==
> > +
> > +RISC-V PolarFire SoC
> > +-
> > +The PolarFire SoC is the 4+1 64-bit RISC-V SoC from Microchip.
> > +
> > +The Icicle Kit development platform is based on PolarFire SoC and
> capable
> > +of running Linux.
> > +
> > +Mainline support
> > +
> > +The support for following drivers are already enabled:
> > +
> > +1. NS16550 UART Driver.
> > +2. Microchip Clock Driver.
> > +3. Cadence MACB ethernet driver for networking support.
> > +4. Cadence MMC Driver for eMMC/SD support.
> > +
> > +Booting from eMMC using HSS
> > +---
> > +
> > +Building
> > +
> > +
> > +1. Add the RISC-V toolchain to your PATH.
> > +2. Setup ARCH & cross compilation environment variable:
> > +
> > +.. code-block:: none
> > +
> > +   export CROSS_COMPILE=
> > +
> > +3. make microchip_mpfs_icicle_defconfig
> > +4. make
> > +
> > +Flashing
> > +
> > +
> > +The current U-Boot port is supported in S-mode only and loaded from
> DRAM.
> > +
> > +A prior stage M-mode firmware/bootloader (e.g HSS with OpenSBI) is
> required to
> > +boot the u-boot.bin in S-mode.
> > +
> > +Currently, the u-boot.bin is used as a payload of the HSS firmware.
> > +
> > +You will be creating a payload from `u-boot-dtb.bin`.
> > +Copy this file to the toplevel HSS (Hart Software Services) directory.
>
> It might be a strange question, but in order to support standardized
> bootflow with SPL
>
> I think the DRAM initialization is part of HSS, can we able to build
> move that DRAM init part out of HSS? If so we can have SPL that loads
> HSS. This might be a strange question but it would be a final goal in
> order to standardize bootflow like other RISC-V targets in Mainline.
>
>
U-Boot SPL is our future plan. Presently we are going with the Microchip
boot-flow and custom boot-flow.

Regards
Padmarao

> Jagan.
>

Re: [PATCH v2 7/7] doc: board: Add Microchip MPFS Icicle Kit doc

2020-10-25 Thread Anup Patel 
On Thu, Oct 22, 2020 at 1:22 PM Padmarao Begari
 wrote:
>
> This doc describes the procedure to build, flash and
> boot Linux using U-boot on Microchip MPFS Icicle Kit.
>
> Signed-off-by: Padmarao Begari 
> ---
>  doc/board/index.rst |   1 +
>  doc/board/microchip/index.rst   |   9 +
>  doc/board/microchip/mpfs_icicle.rst | 605 
>  3 files changed, 615 insertions(+)
>  create mode 100644 doc/board/microchip/index.rst
>  create mode 100644 doc/board/microchip/mpfs_icicle.rst
>
> diff --git a/doc/board/index.rst b/doc/board/index.rst
> index 63935abcd7..e50a78d752 100644
> --- a/doc/board/index.rst
> +++ b/doc/board/index.rst
> @@ -15,6 +15,7 @@ Board-specific doc
> freescale/index
> google/index
> intel/index
> +   microchip/index
> renesas/index
> rockchip/index
> sifive/index
> diff --git a/doc/board/microchip/index.rst b/doc/board/microchip/index.rst
> new file mode 100644
> index 00..b09e6788af
> --- /dev/null
> +++ b/doc/board/microchip/index.rst
> @@ -0,0 +1,9 @@
> +.. SPDX-License-Identifier: GPL-2.0+
> +
> +Microchip
> +==
> +
> +.. toctree::
> +   :maxdepth: 2
> +
> +   mpfs_icicle
> diff --git a/doc/board/microchip/mpfs_icicle.rst 
> b/doc/board/microchip/mpfs_icicle.rst
> new file mode 100644
> index 00..a4876b02f7
> --- /dev/null
> +++ b/doc/board/microchip/mpfs_icicle.rst
> @@ -0,0 +1,605 @@
> +.. SPDX-License-Identifier: GPL-2.0+
> +
> +Microchip PolarFire SoC Icicle Kit
> +==
> +
> +RISC-V PolarFire SoC
> +-
> +The PolarFire SoC is the 4+1 64-bit RISC-V SoC from Microchip.
> +
> +The Icicle Kit development platform is based on PolarFire SoC and capable
> +of running Linux.
> +
> +Mainline support
> +
> +The support for following drivers are already enabled:
> +
> +1. NS16550 UART Driver.
> +2. Microchip Clock Driver.
> +3. Cadence MACB ethernet driver for networking support.
> +4. Cadence MMC Driver for eMMC/SD support.
> +
> +Booting from eMMC using HSS
> +---
> +
> +Building
> +
> +
> +1. Add the RISC-V toolchain to your PATH.
> +2. Setup ARCH & cross compilation environment variable:
> +
> +.. code-block:: none
> +
> +   export CROSS_COMPILE=
> +
> +3. make microchip_mpfs_icicle_defconfig
> +4. make
> +
> +Flashing
> +
> +
> +The current U-Boot port is supported in S-mode only and loaded from DRAM.
> +
> +A prior stage M-mode firmware/bootloader (e.g HSS with OpenSBI) is required 
> to
> +boot the u-boot.bin in S-mode.
> +
> +Currently, the u-boot.bin is used as a payload of the HSS firmware.
> +
> +You will be creating a payload from `u-boot-dtb.bin`.
> +Copy this file to the toplevel HSS (Hart Software Services) directory.

The HSS firmware has a very old OpenSBI linked to it as a library. The OpenSBI
is a moving target and a lot of features/fixes keep adding to OpenSBI.

To tackle this, latest HSS has a compile time option for custom boot flow . The
HSS custom boot-flow allows us to:
1. Use OpenSBI generic platform fw_payload.bin (with u-boot.bin embedded) as
HSS payload
2. Use U-Boot SPL (in-future) as HSS payload

I am able of use latest OpenSBI generic platform and U-Boot S-mode without
any issues, to try this:
1) Compile u-boot.bin with this series
2) Compile OpenSBI generic fw_payload.bin using:
make PLATFORM=generic FW_PAYLOAD_PATH=/u-boot.bin
FW_FDT_PATH=/arch/riscv/dts/microchip-icicle-kit-a000.dtb

> +
> +Creating the HSS payload
> +

Please have a separate section for steps to compile HSS software for
both Microchip boot-flow and Custom boot-flow.

This section describe how to create HSS payload for both Microchip
boot-flow and Custom boot-flow

> +
> +Please refer to HSS documenation to build the HSS firmware.
> +(Note: HSS git repo is at
> +https://github.com/polarfire-soc/hart-software-services/blob/master
> +/tools/hss-payload-generator/README.md)

Compiling HSS is quite simple. Please provide explicit steps here itself.

> +
> +Once the payload binary is generated, it should be copied to the eMMC.
> +
> +FPGA design with HSS programming file
> +-
> +https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards
> +/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md
> +
> +The HSS firmware runs from the PolarFire SoC eNVM on reset.
> +
> +eMMC
> +
> +Program eMMC with payload binary is explained in the PolarFire SoC 
> documentation.

The HSS always picks up next stage (i.e. HSS payload) from a
particular GPT partition
with specific GUID type. Please describe these details over here. The
below link does
not describe it.

> +
> +(Note: PolarFire SoC Documentation git repo is at
> +https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards
> +/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md#eMMC
> +
> +Once the payload

Re: [PATCH v2 7/7] doc: board: Add Microchip MPFS Icicle Kit doc

2020-10-24 Thread Jagan Teki 
On Thu, Oct 22, 2020 at 1:22 PM Padmarao Begari
 wrote:
>
> This doc describes the procedure to build, flash and
> boot Linux using U-boot on Microchip MPFS Icicle Kit.
>
> Signed-off-by: Padmarao Begari 
> ---
>  doc/board/index.rst |   1 +
>  doc/board/microchip/index.rst   |   9 +
>  doc/board/microchip/mpfs_icicle.rst | 605 
>  3 files changed, 615 insertions(+)
>  create mode 100644 doc/board/microchip/index.rst
>  create mode 100644 doc/board/microchip/mpfs_icicle.rst
>
> diff --git a/doc/board/index.rst b/doc/board/index.rst
> index 63935abcd7..e50a78d752 100644
> --- a/doc/board/index.rst
> +++ b/doc/board/index.rst
> @@ -15,6 +15,7 @@ Board-specific doc
> freescale/index
> google/index
> intel/index
> +   microchip/index
> renesas/index
> rockchip/index
> sifive/index
> diff --git a/doc/board/microchip/index.rst b/doc/board/microchip/index.rst
> new file mode 100644
> index 00..b09e6788af
> --- /dev/null
> +++ b/doc/board/microchip/index.rst
> @@ -0,0 +1,9 @@
> +.. SPDX-License-Identifier: GPL-2.0+
> +
> +Microchip
> +==
> +
> +.. toctree::
> +   :maxdepth: 2
> +
> +   mpfs_icicle
> diff --git a/doc/board/microchip/mpfs_icicle.rst 
> b/doc/board/microchip/mpfs_icicle.rst
> new file mode 100644
> index 00..a4876b02f7
> --- /dev/null
> +++ b/doc/board/microchip/mpfs_icicle.rst
> @@ -0,0 +1,605 @@
> +.. SPDX-License-Identifier: GPL-2.0+
> +
> +Microchip PolarFire SoC Icicle Kit
> +==
> +
> +RISC-V PolarFire SoC
> +-
> +The PolarFire SoC is the 4+1 64-bit RISC-V SoC from Microchip.
> +
> +The Icicle Kit development platform is based on PolarFire SoC and capable
> +of running Linux.
> +
> +Mainline support
> +
> +The support for following drivers are already enabled:
> +
> +1. NS16550 UART Driver.
> +2. Microchip Clock Driver.
> +3. Cadence MACB ethernet driver for networking support.
> +4. Cadence MMC Driver for eMMC/SD support.
> +
> +Booting from eMMC using HSS
> +---
> +
> +Building
> +
> +
> +1. Add the RISC-V toolchain to your PATH.
> +2. Setup ARCH & cross compilation environment variable:
> +
> +.. code-block:: none
> +
> +   export CROSS_COMPILE=
> +
> +3. make microchip_mpfs_icicle_defconfig
> +4. make
> +
> +Flashing
> +
> +
> +The current U-Boot port is supported in S-mode only and loaded from DRAM.
> +
> +A prior stage M-mode firmware/bootloader (e.g HSS with OpenSBI) is required 
> to
> +boot the u-boot.bin in S-mode.
> +
> +Currently, the u-boot.bin is used as a payload of the HSS firmware.
> +
> +You will be creating a payload from `u-boot-dtb.bin`.
> +Copy this file to the toplevel HSS (Hart Software Services) directory.

It might be a strange question, but in order to support standardized
bootflow with SPL

I think the DRAM initialization is part of HSS, can we able to build
move that DRAM init part out of HSS? If so we can have SPL that loads
HSS. This might be a strange question but it would be a final goal in
order to standardize bootflow like other RISC-V targets in Mainline.

Jagan.

[PATCH v2 7/7] doc: board: Add Microchip MPFS Icicle Kit doc

2020-10-22 Thread Padmarao Begari 
This doc describes the procedure to build, flash and
boot Linux using U-boot on Microchip MPFS Icicle Kit.

Signed-off-by: Padmarao Begari 
---
 doc/board/index.rst |   1 +
 doc/board/microchip/index.rst   |   9 +
 doc/board/microchip/mpfs_icicle.rst | 605 
 3 files changed, 615 insertions(+)
 create mode 100644 doc/board/microchip/index.rst
 create mode 100644 doc/board/microchip/mpfs_icicle.rst

diff --git a/doc/board/index.rst b/doc/board/index.rst
index 63935abcd7..e50a78d752 100644
--- a/doc/board/index.rst
+++ b/doc/board/index.rst
@@ -15,6 +15,7 @@ Board-specific doc
freescale/index
google/index
intel/index
+   microchip/index
renesas/index
rockchip/index
sifive/index
diff --git a/doc/board/microchip/index.rst b/doc/board/microchip/index.rst
new file mode 100644
index 00..b09e6788af
--- /dev/null
+++ b/doc/board/microchip/index.rst
@@ -0,0 +1,9 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Microchip
+==
+
+.. toctree::
+   :maxdepth: 2
+
+   mpfs_icicle
diff --git a/doc/board/microchip/mpfs_icicle.rst 
b/doc/board/microchip/mpfs_icicle.rst
new file mode 100644
index 00..a4876b02f7
--- /dev/null
+++ b/doc/board/microchip/mpfs_icicle.rst
@@ -0,0 +1,605 @@
+.. SPDX-License-Identifier: GPL-2.0+
+
+Microchip PolarFire SoC Icicle Kit
+==
+
+RISC-V PolarFire SoC
+-
+The PolarFire SoC is the 4+1 64-bit RISC-V SoC from Microchip.
+
+The Icicle Kit development platform is based on PolarFire SoC and capable
+of running Linux.
+
+Mainline support
+
+The support for following drivers are already enabled:
+
+1. NS16550 UART Driver.
+2. Microchip Clock Driver.
+3. Cadence MACB ethernet driver for networking support.
+4. Cadence MMC Driver for eMMC/SD support.
+
+Booting from eMMC using HSS
+---
+
+Building
+
+
+1. Add the RISC-V toolchain to your PATH.
+2. Setup ARCH & cross compilation environment variable:
+
+.. code-block:: none
+
+   export CROSS_COMPILE=
+
+3. make microchip_mpfs_icicle_defconfig
+4. make
+
+Flashing
+
+
+The current U-Boot port is supported in S-mode only and loaded from DRAM.
+
+A prior stage M-mode firmware/bootloader (e.g HSS with OpenSBI) is required to
+boot the u-boot.bin in S-mode.
+
+Currently, the u-boot.bin is used as a payload of the HSS firmware.
+
+You will be creating a payload from `u-boot-dtb.bin`.
+Copy this file to the toplevel HSS (Hart Software Services) directory.
+
+Creating the HSS payload
+
+
+Please refer to HSS documenation to build the HSS firmware.
+(Note: HSS git repo is at
+https://github.com/polarfire-soc/hart-software-services/blob/master
+/tools/hss-payload-generator/README.md)
+
+Once the payload binary is generated, it should be copied to the eMMC.
+
+FPGA design with HSS programming file
+-
+https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards
+/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md
+
+The HSS firmware runs from the PolarFire SoC eNVM on reset.
+
+eMMC
+
+Program eMMC with payload binary is explained in the PolarFire SoC 
documentation.
+
+(Note: PolarFire SoC Documentation git repo is at
+https://github.com/polarfire-soc/polarfire-soc-documentation/blob/master/boards
+/mpfs-icicle-kit-es/updating-icicle-kit/updating-icicle-kit-design-and-linux.md#eMMC
+
+Once the payload image is copied to the eMMC, press CTRL+C in the HSS command
+line interface, then type 'boot' and enter to boot the newly copied image.
+
+.. code-block:: none
+
+sudo dd if= of=/dev/sdX bs=512
+
+Booting
+---
+you should see the U-Boot prompt on UART0.
+
+Sample boot log from MPFS Icicle Kit
+---
+
+.. code-block:: none
+
+   U-Boot 2020.10-00822-gb561436cc0-dirty (Oct 22 2020 - 11:21:24 +0530)
+
+   CPU:   rv64imafdc
+   Model: Microchip PolarFire-SoC
+   DRAM:  1 GiB
+   MMC:   sdhc@20008000: 0
+   In:serial@2010
+   Out:   serial@2010
+   Err:   serial@2010
+   Net:   eth0: ethernet@20112000
+   Hit any key to stop autoboot:  0
+
+Now you can configure your networking, tftp server and use tftp boot method to
+load uImage(with initramfs).
+
+.. code-block:: none
+
+   RISC-V # setenv kernel_addr_r 0x8020
+   RISC-V # setenv fdt_addr_r 0x8220
+
+   RISC-V # setenv ipaddr 192.168.1.5
+   RISC-V # setenv netmask 255.255.255.0
+   RISC-V # setenv serverip 192.168.1.3
+   RISC-V # setenv gateway 192.168.1.1
+
+   RISC-V # tftpboot ${kernel_addr_r} uImage
+   ethernet@20112000: PHY present at 9
+   ethernet@20112000: Starting autonegotiation...
+   ethernet@20112000: Autonegotiation complete
+   ethernet@20112000: link up, 1000Mbps full-duplex (lpa: 0x7800)
+   Using ethernet@20112000 device
+   TFTP from server 192.168.1.3; our IP address is 192.168.1.5
+   Filename 'uImage'.
+   Load address: