Re: [PATCH v3 04/12] arm: dts: rockchip: sync rk322x.dtsi from Linux
Hi Johan,
On 2022/3/4 07:52, Johan Jonker wrote:
Sync rk322x.dtsi from Linux version 5.17.
Signed-off-by: Johan Jonker
---
Changed V2:
update
rename usb20_otg label
---
arch/arm/dts/rk3229-evb.dts | 2 +-
arch/arm/dts/rk322x.dtsi| 846 +---
2 files changed, 695 insertions(+), 153 deletions(-)
diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts
index 66a3ba23..d2681d1a 100644
--- a/arch/arm/dts/rk3229-evb.dts
+++ b/arch/arm/dts/rk3229-evb.dts
@@ -69,6 +69,6 @@
status = "okay";
};
-&usb20_otg {
+&usb_otg {
status = "okay";
};
diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi
index 3245da3c..8eed9e3a 100644
--- a/arch/arm/dts/rk322x.dtsi
+++ b/arch/arm/dts/rk322x.dtsi
@@ -1,7 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
- */
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include
#include
@@ -9,6 +6,7 @@
#include
#include
#include
+#include
/ {
#address-cells = <1>;
@@ -20,8 +18,7 @@
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
- mmc0 = &emmc;
- mmc1 = &sdmmc;
I think this part will need to move to -u-boot.dtsi for U-Boot will use
this to decide the boot order,
and U-Boot use emmc as mmc0 and sdmmc as mmc1 before kernel decide to
add alias for mmc module.
Thanks,
- Kever
+ spi0 = &spi0;
};
cpus {
@@ -33,13 +30,11 @@
compatible = "arm,cortex-a7";
reg = <0xf00>;
resets = <&cru SRST_CORE0>;
- operating-points = <
- /* KHzuV */
-816000 100
- >;
+ operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>; /* min followed by max */
clock-latency = <4>;
clocks = <&cru ARMCLK>;
+ enable-method = "psci";
};
cpu1: cpu@f01 {
@@ -47,6 +42,9 @@
compatible = "arm,cortex-a7";
reg = <0xf01>;
resets = <&cru SRST_CORE1>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>; /* min followed by max */
+ enable-method = "psci";
};
cpu2: cpu@f02 {
@@ -54,6 +52,9 @@
compatible = "arm,cortex-a7";
reg = <0xf02>;
resets = <&cru SRST_CORE2>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>; /* min followed by max */
+ enable-method = "psci";
};
cpu3: cpu@f03 {
@@ -61,23 +62,37 @@
compatible = "arm,cortex-a7";
reg = <0xf03>;
resets = <&cru SRST_CORE3>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>; /* min followed by max */
+ enable-method = "psci";
};
};
- amba {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
+ cpu0_opp_table: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
- pdma: pdma@110f {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x110f 0x4000>;
- interrupts = ,
-;
- #dma-cells = <1>;
- clocks = <&cru ACLK_DMAC>;
- clock-names = "apb_pclk";
+ opp-40800 {
+ opp-hz = /bits/ 64 <40800>;
+ opp-microvolt = <95>;
+ clock-latency-ns = <4>;
+ opp-suspend;
+ };
+ opp-6 {
+ opp-hz = /bits/ 64 <6>;
+ opp-microvolt = <975000>;
+ };
+ opp-81600 {
+ opp-hz = /bits/ 64 <81600>;
+ opp-microvolt = <100>;
+ };
+ opp-100800 {
+ opp-hz = /bits/ 64 <100800>;
+ opp-microvolt = <1175000>;
+ };
+ opp-12 {
+ opp-hz = /bits/ 64 <12>;
+ opp-microvolt = <1275000>;
};
};
@@ -90,6 +105,11 @@
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3
[PATCH v3 04/12] arm: dts: rockchip: sync rk322x.dtsi from Linux
Sync rk322x.dtsi from Linux version 5.17.
Signed-off-by: Johan Jonker
---
Changed V2:
update
rename usb20_otg label
---
arch/arm/dts/rk3229-evb.dts | 2 +-
arch/arm/dts/rk322x.dtsi| 846 +---
2 files changed, 695 insertions(+), 153 deletions(-)
diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts
index 66a3ba23..d2681d1a 100644
--- a/arch/arm/dts/rk3229-evb.dts
+++ b/arch/arm/dts/rk3229-evb.dts
@@ -69,6 +69,6 @@
status = "okay";
};
-&usb20_otg {
+&usb_otg {
status = "okay";
};
diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi
index 3245da3c..8eed9e3a 100644
--- a/arch/arm/dts/rk322x.dtsi
+++ b/arch/arm/dts/rk322x.dtsi
@@ -1,7 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
- */
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
#include
#include
@@ -9,6 +6,7 @@
#include
#include
#include
+#include
/ {
#address-cells = <1>;
@@ -20,8 +18,7 @@
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
- mmc0 = &emmc;
- mmc1 = &sdmmc;
+ spi0 = &spi0;
};
cpus {
@@ -33,13 +30,11 @@
compatible = "arm,cortex-a7";
reg = <0xf00>;
resets = <&cru SRST_CORE0>;
- operating-points = <
- /* KHzuV */
-816000 100
- >;
+ operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>; /* min followed by max */
clock-latency = <4>;
clocks = <&cru ARMCLK>;
+ enable-method = "psci";
};
cpu1: cpu@f01 {
@@ -47,6 +42,9 @@
compatible = "arm,cortex-a7";
reg = <0xf01>;
resets = <&cru SRST_CORE1>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>; /* min followed by max */
+ enable-method = "psci";
};
cpu2: cpu@f02 {
@@ -54,6 +52,9 @@
compatible = "arm,cortex-a7";
reg = <0xf02>;
resets = <&cru SRST_CORE2>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>; /* min followed by max */
+ enable-method = "psci";
};
cpu3: cpu@f03 {
@@ -61,23 +62,37 @@
compatible = "arm,cortex-a7";
reg = <0xf03>;
resets = <&cru SRST_CORE3>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>; /* min followed by max */
+ enable-method = "psci";
};
};
- amba {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
+ cpu0_opp_table: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
- pdma: pdma@110f {
- compatible = "arm,pl330", "arm,primecell";
- reg = <0x110f 0x4000>;
- interrupts = ,
-;
- #dma-cells = <1>;
- clocks = <&cru ACLK_DMAC>;
- clock-names = "apb_pclk";
+ opp-40800 {
+ opp-hz = /bits/ 64 <40800>;
+ opp-microvolt = <95>;
+ clock-latency-ns = <4>;
+ opp-suspend;
+ };
+ opp-6 {
+ opp-hz = /bits/ 64 <6>;
+ opp-microvolt = <975000>;
+ };
+ opp-81600 {
+ opp-hz = /bits/ 64 <81600>;
+ opp-microvolt = <100>;
+ };
+ opp-100800 {
+ opp-hz = /bits/ 64 <100800>;
+ opp-microvolt = <1175000>;
+ };
+ opp-12 {
+ opp-hz = /bits/ 64 <12>;
+ opp-microvolt = <1275000>;
};
};
@@ -90,6 +105,11 @@
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
+ psci {
+ compatible = "arm,psci-1.0", "arm,psci-0.2";
+ method = "smc";
+ };
+
timer {
compatible = "arm,armv7-timer";
arm,cpu-registers-not-fw-configured;
