Re: [PATCH v3 11/19] imx: kontron-sl-mx8mm: Remove 100mt DDR setpoint
On Mon, Oct 24, 2022 at 4:54 AM Frieder Schrempf wrote: > > Hi Tim, > > On 21.10.22 21:24, Tim Harvey wrote: > > On Wed, Aug 24, 2022 at 7:01 AM Frieder Schrempf wrote: > >> > >> From: Frieder Schrempf > >> > >> The new stable configuration is missing the 100mt setpoint, remove > >> it before updating the config to make sure the changes are separated > >> cleanly. > >> > >> Signed-off-by: Frieder Schrempf > >> Reviewed-by: Fabio Estevam > >> --- > > > > Frieder, > > > > I just noticed this patch and was curious what it was about. > > > > What do you mean by 'the new stable configuration is missing the 100mt > > setpoint'? Does this refer to something NXP has changed in their DDR > > config tools? > > At some point we started using 4GB LPDDR4 chips from Nanya on our SoMs > while before we only had Micron chips. For some unknown reason (NXP > couldn't explain it either), the only configuration that works for all > used chips (Micron and Nanya) is only stable if the lowest of the three > frequency setpoints is removed. > > Unfortunately I have no idea how this behavior could be explained. > Frieder, Ok - thanks for the explanation. I'm looking for ways to reduce the SPL impact of DRAM configs as I have 4 of them for imx8mm-venice that are keeping me from adding SDP support due to SPL size. I wonder if binman and linker labels could be used to load dram configs. Best Regards, Tim
Re: [PATCH v3 11/19] imx: kontron-sl-mx8mm: Remove 100mt DDR setpoint
Hi Tim, On 21.10.22 21:24, Tim Harvey wrote: > On Wed, Aug 24, 2022 at 7:01 AM Frieder Schrempf wrote: >> >> From: Frieder Schrempf >> >> The new stable configuration is missing the 100mt setpoint, remove >> it before updating the config to make sure the changes are separated >> cleanly. >> >> Signed-off-by: Frieder Schrempf >> Reviewed-by: Fabio Estevam >> --- > > Frieder, > > I just noticed this patch and was curious what it was about. > > What do you mean by 'the new stable configuration is missing the 100mt > setpoint'? Does this refer to something NXP has changed in their DDR > config tools? At some point we started using 4GB LPDDR4 chips from Nanya on our SoMs while before we only had Micron chips. For some unknown reason (NXP couldn't explain it either), the only configuration that works for all used chips (Micron and Nanya) is only stable if the lowest of the three frequency setpoints is removed. Unfortunately I have no idea how this behavior could be explained. Best regards Frieder
Re: [PATCH v3 11/19] imx: kontron-sl-mx8mm: Remove 100mt DDR setpoint
On Wed, Aug 24, 2022 at 7:01 AM Frieder Schrempf wrote: > > From: Frieder Schrempf > > The new stable configuration is missing the 100mt setpoint, remove > it before updating the config to make sure the changes are separated > cleanly. > > Signed-off-by: Frieder Schrempf > Reviewed-by: Fabio Estevam > --- Frieder, I just noticed this patch and was curious what it was about. What do you mean by 'the new stable configuration is missing the 100mt setpoint'? Does this refer to something NXP has changed in their DDR config tools? Best Regards, Tim
[PATCH v3 11/19] imx: kontron-sl-mx8mm: Remove 100mt DDR setpoint
> From: Frieder Schrempf > The new stable configuration is missing the 100mt setpoint, remove > it before updating the config to make sure the changes are separated > cleanly. > Signed-off-by: Frieder Schrempf > Reviewed-by: Fabio Estevam Applied to u-boot-imx, master, thanks ! Best regards, Stefano Babic -- = DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de =
[PATCH v3 11/19] imx: kontron-sl-mx8mm: Remove 100mt DDR setpoint
From: Frieder Schrempf
The new stable configuration is missing the 100mt setpoint, remove
it before updating the config to make sure the changes are separated
cleanly.
Signed-off-by: Frieder Schrempf
Reviewed-by: Fabio Estevam
---
Changes in v3:
* none
Changes in v2:
* none
---
arch/arm/dts/imx8mm-kontron-n801x-som.dtsi | 4 --
board/kontron/sl-mx8mm/lpddr4_timing.c | 49 +-
board/kontron/sl-mx8mm/spl.c | 2 -
3 files changed, 1 insertion(+), 54 deletions(-)
diff --git a/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi
b/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi
index 3b66e560927..39c0ce19ef1 100644
--- a/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi
+++ b/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi
@@ -46,10 +46,6 @@
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
- opp-25M {
- opp-hz = /bits/ 64 <2500>;
- };
-
opp-100M {
opp-hz = /bits/ 64 <1>;
};
diff --git a/board/kontron/sl-mx8mm/lpddr4_timing.c
b/board/kontron/sl-mx8mm/lpddr4_timing.c
index a8dcaafb180..cdde6ac0dc0 100644
--- a/board/kontron/sl-mx8mm/lpddr4_timing.c
+++ b/board/kontron/sl-mx8mm/lpddr4_timing.c
@@ -1121,46 +1121,6 @@ struct dram_cfg_param ddr_fsp1_cfg[] = {
{ 0xd, 0x1 },
};
-/* P2 message block paremeter for training firmware */
-struct dram_cfg_param ddr_fsp2_cfg[] = {
- { 0xd, 0x0 },
- { 0x54002, 0x102 },
- { 0x54003, 0x64 },
- { 0x54004, 0x2 },
- { 0x54005, 0x2228 },
- { 0x54006, 0x11 },
- { 0x54008, 0x121f },
- { 0x54009, 0xc8 },
- { 0x5400b, 0x2 },
- { 0x5400d, 0x100 },
- { 0x54012, 0x310 },
- { 0x54019, 0x84 },
- { 0x5401a, 0x31 },
- { 0x5401b, 0x4d66 },
- { 0x5401c, 0x4d00 },
- { 0x5401e, 0x16 },
- { 0x5401f, 0x84 },
- { 0x54020, 0x31 },
- { 0x54021, 0x4d66 },
- { 0x54022, 0x4d00 },
- { 0x54024, 0x16 },
- { 0x5402b, 0x1000 },
- { 0x5402c, 0x3 },
- { 0x54032, 0x8400 },
- { 0x54033, 0x3100 },
- { 0x54034, 0x6600 },
- { 0x54035, 0x4d },
- { 0x54036, 0x4d },
- { 0x54037, 0x1600 },
- { 0x54038, 0x8400 },
- { 0x54039, 0x3100 },
- { 0x5403a, 0x6600 },
- { 0x5403b, 0x4d },
- { 0x5403c, 0x4d },
- { 0x5403d, 0x1600 },
- { 0xd, 0x1 },
-};
-
/* P0 2D message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0xd, 0x0 },
@@ -1812,13 +1772,6 @@ struct dram_fsp_msg ddr_dram_fsp_msg[] = {
.fsp_cfg = ddr_fsp1_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
},
- {
- /* P2 100mts 1D */
- .drate = 100,
- .fw_type = FW_1D_IMAGE,
- .fsp_cfg = ddr_fsp2_cfg,
- .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
-},
{
/* P0 3000mts 2D */
.drate = 3000,
@@ -1840,5 +1793,5 @@ struct dram_timing_info dram_timing = {
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
.ddrphy_pie = ddr_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
- .fsp_table = { 3000, 400, 100, },
+ .fsp_table = { 3000, 400, },
};
diff --git a/board/kontron/sl-mx8mm/spl.c b/board/kontron/sl-mx8mm/spl.c
index 2a562f4ac97..447da13984e 100644
--- a/board/kontron/sl-mx8mm/spl.c
+++ b/board/kontron/sl-mx8mm/spl.c
@@ -95,8 +95,6 @@ static void spl_dram_init(void)
dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x1;
dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x110;
dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x1;
- dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x110;
- dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x1;
if (!ddr_init(&dram_timing)) {
if (check_ram_available(SZ_2G))
--
2.37.2
