Re: [PATCH v3 2/4] x86: Update coreboot serial table struct

2020-02-02 Thread Bin Meng
On Fri, Dec 20, 2019 at 8:58 AM Simon Glass  wrote:
>
> Since mid 2016, coreboot has additional fields in the serial struct that
> it passes down to U-Boot. Add these so we are in sync.
>
> Signed-off-by: Simon Glass 
> Reviewed-by: Bin Meng 
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/include/asm/coreboot_tables.h | 19 +++
>  1 file changed, 19 insertions(+)
>

applied to u-boot-x86, thanks!


[PATCH v3 2/4] x86: Update coreboot serial table struct

2019-12-19 Thread Simon Glass
Since mid 2016, coreboot has additional fields in the serial struct that
it passes down to U-Boot. Add these so we are in sync.

Signed-off-by: Simon Glass 
Reviewed-by: Bin Meng 
---

Changes in v3: None
Changes in v2: None

 arch/x86/include/asm/coreboot_tables.h | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/arch/x86/include/asm/coreboot_tables.h 
b/arch/x86/include/asm/coreboot_tables.h
index 2c54e24e02..61de0077d7 100644
--- a/arch/x86/include/asm/coreboot_tables.h
+++ b/arch/x86/include/asm/coreboot_tables.h
@@ -97,6 +97,25 @@ struct cb_serial {
u32 type;
u32 baseaddr;
u32 baud;
+   u32 regwidth;
+
+   /*
+* Crystal or input frequency to the chip containing the UART.
+* Provide the board specific details to allow the payload to
+* initialize the chip containing the UART and make independent
+* decisions as to which dividers to select and their values
+* to eventually arrive at the desired console baud-rate.
+*/
+   u32 input_hertz;
+
+   /*
+* UART PCI address: bus, device, function
+* 1 << 31 - Valid bit, PCI UART in use
+* Bus << 20
+* Device << 15
+* Function << 12
+*/
+   u32 uart_pci_addr;
 };
 
 #define CB_TAG_CONSOLE 0x0010
-- 
2.24.1.735.g03f4e72817-goog