Re: [PATCH v3 5/6] net: phy: nxp-tja11xx: Add NXP TJA11xx PHY driver
On Thu, Feb 17, 2022 at 4:36 PM Ariel D'Alessandro
wrote:
>
> From: Michael Trimarchi
>
> Add driver for the NXP TJA1100 and TJA1101 PHYs. These PHYs are special
> BroadRReach 100BaseT1 PHYs used in automotive.
>
> Signed-off-by: Michael Trimarchi
> Signed-off-by: Ariel D'Alessandro
> ---
> drivers/net/phy/Kconfig | 5 +
> drivers/net/phy/Makefile | 1 +
> drivers/net/phy/nxp-tja11xx.c | 277 ++
> drivers/net/phy/phy.c | 3 +
> include/phy.h | 1 +
> 5 files changed, 287 insertions(+)
> create mode 100644 drivers/net/phy/nxp-tja11xx.c
>
> diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
> index 4f8d33ce8fd..8de6130113c 100644
> --- a/drivers/net/phy/Kconfig
> +++ b/drivers/net/phy/Kconfig
> @@ -211,6 +211,11 @@ config PHY_NXP_C45_TJA11XX
> Enable support for NXP C45 TJA11XX PHYs.
> Currently supports only the TJA1103 PHY.
>
> +config PHY_NXP_TJA11XX
> + bool "NXP TJA11XX Ethernet PHYs support"
> + help
> + Currently supports the NXP TJA1100 and TJA1101 PHY.
> +
> config PHY_REALTEK
> bool "Realtek Ethernet PHYs support"
>
> diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
> index 77f7f606215..7cfbab0b5c8 100644
> --- a/drivers/net/phy/Makefile
> +++ b/drivers/net/phy/Makefile
> @@ -24,6 +24,7 @@ obj-$(CONFIG_PHY_MICREL_KSZ90X1) += micrel_ksz90x1.o
> obj-$(CONFIG_PHY_MESON_GXL) += meson-gxl.o
> obj-$(CONFIG_PHY_NATSEMI) += natsemi.o
> obj-$(CONFIG_PHY_NXP_C45_TJA11XX) += nxp-c45-tja11xx.o
> +obj-$(CONFIG_PHY_NXP_TJA11XX) += nxp-tja11xx.o
> obj-$(CONFIG_PHY_REALTEK) += realtek.o
> obj-$(CONFIG_PHY_SMSC) += smsc.o
> obj-$(CONFIG_PHY_TERANETICS) += teranetics.o
> diff --git a/drivers/net/phy/nxp-tja11xx.c b/drivers/net/phy/nxp-tja11xx.c
> new file mode 100644
> index 000..30dec5e605b
> --- /dev/null
> +++ b/drivers/net/phy/nxp-tja11xx.c
> @@ -0,0 +1,277 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* NXP TJA1100 BroadRReach PHY driver
> + *
> + * Copyright (C) 2022 Michael Trimarchi
> + * Copyright (C) 2022 Ariel D'Alessandro
> + * Copyright (C) 2018 Marek Vasut
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#define PHY_ID_MASK0xfff0
> +#define PHY_ID_TJA1100 0x0180dc40
> +#define PHY_ID_TJA1101 0x0180dd00
> +
> +#define MII_ECTRL 17
> +#define MII_ECTRL_LINK_CONTROL BIT(15)
> +#define MII_ECTRL_POWER_MODE_MASK GENMASK(14, 11)
> +#define MII_ECTRL_POWER_MODE_NO_CHANGE (0x0 << 11)
> +#define MII_ECTRL_POWER_MODE_NORMAL(0x3 << 11)
> +#define MII_ECTRL_POWER_MODE_STANDBY (0xc << 11)
> +#define MII_ECTRL_CABLE_TEST BIT(5)
> +#define MII_ECTRL_CONFIG_ENBIT(2)
> +#define MII_ECTRL_WAKE_REQUEST BIT(0)
> +
> +#define MII_CFG1 18
> +#define MII_CFG1_MASTER_SLAVE BIT(15)
> +#define MII_CFG1_AUTO_OP BIT(14)
> +#define MII_CFG1_SLEEP_CONFIRM BIT(6)
> +#define MII_CFG1_LED_MODE_MASK GENMASK(5, 4)
> +#define MII_CFG1_LED_MODE_LINKUP 0
> +#define MII_CFG1_LED_ENABLEBIT(3)
> +
> +#define MII_CFG2 19
> +#define MII_CFG2_SLEEP_REQUEST_TO GENMASK(1, 0)
> +#define MII_CFG2_SLEEP_REQUEST_TO_16MS 0x3
> +
> +#define MII_INTSRC 21
> +#define MII_INTSRC_LINK_FAIL BIT(10)
> +#define MII_INTSRC_LINK_UP BIT(9)
> +#define MII_INTSRC_MASK(MII_INTSRC_LINK_FAIL | \
> +MII_INTSRC_LINK_UP)
> +#define MII_INTSRC_UV_ERR BIT(3)
> +#define MII_INTSRC_TEMP_ERRBIT(1)
> +
> +#define MII_INTEN 22
> +#define MII_INTEN_LINK_FAILBIT(10)
> +#define MII_INTEN_LINK_UP BIT(9)
> +#define MII_INTEN_UV_ERR BIT(3)
> +#define MII_INTEN_TEMP_ERR BIT(1)
> +
> +#define MII_COMMSTAT 23
> +#define MII_COMMSTAT_LINK_UP BIT(15)
> +#define MII_COMMSTAT_SQI_STATE GENMASK(7, 5)
> +#define MII_COMMSTAT_SQI_MAX 7
> +
> +#define MII_GENSTAT24
> +#define MII_GENSTAT_PLL_LOCKED BIT(14)
> +
> +#define MII_EXTSTAT25
> +#define MII_EXTSTAT_SHORT_DETECT BIT(8)
> +#define MII_EXTSTAT_OPEN_DETECTBIT(7)
> +#define MII_EXTSTAT_POLARITY_DETECTBIT(6)
> +
> +#define MII_COMMCFG27
> +#define MII_COMMCFG_AUTO_OPBIT(15)
> +
> +static inline int tja11xx_set_bits(struct phy_device *phydev, u32 regnum,
> + u16 val)
> +{
> + return phy_set_bits_mmd(phydev, MDIO_DEVAD_NONE, regnum, val);
> +}
> +
> +static inline int tja11xx_clear_bits(struct phy_device *phydev, u32 regnum,
> +u16 val)
> +{
> + return phy_clear_bits_mmd(phydev, MDIO
[PATCH v3 5/6] net: phy: nxp-tja11xx: Add NXP TJA11xx PHY driver
From: Michael Trimarchi
Add driver for the NXP TJA1100 and TJA1101 PHYs. These PHYs are special
BroadRReach 100BaseT1 PHYs used in automotive.
Signed-off-by: Michael Trimarchi
Signed-off-by: Ariel D'Alessandro
---
drivers/net/phy/Kconfig | 5 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/nxp-tja11xx.c | 277 ++
drivers/net/phy/phy.c | 3 +
include/phy.h | 1 +
5 files changed, 287 insertions(+)
create mode 100644 drivers/net/phy/nxp-tja11xx.c
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 4f8d33ce8fd..8de6130113c 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -211,6 +211,11 @@ config PHY_NXP_C45_TJA11XX
Enable support for NXP C45 TJA11XX PHYs.
Currently supports only the TJA1103 PHY.
+config PHY_NXP_TJA11XX
+ bool "NXP TJA11XX Ethernet PHYs support"
+ help
+ Currently supports the NXP TJA1100 and TJA1101 PHY.
+
config PHY_REALTEK
bool "Realtek Ethernet PHYs support"
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 77f7f606215..7cfbab0b5c8 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -24,6 +24,7 @@ obj-$(CONFIG_PHY_MICREL_KSZ90X1) += micrel_ksz90x1.o
obj-$(CONFIG_PHY_MESON_GXL) += meson-gxl.o
obj-$(CONFIG_PHY_NATSEMI) += natsemi.o
obj-$(CONFIG_PHY_NXP_C45_TJA11XX) += nxp-c45-tja11xx.o
+obj-$(CONFIG_PHY_NXP_TJA11XX) += nxp-tja11xx.o
obj-$(CONFIG_PHY_REALTEK) += realtek.o
obj-$(CONFIG_PHY_SMSC) += smsc.o
obj-$(CONFIG_PHY_TERANETICS) += teranetics.o
diff --git a/drivers/net/phy/nxp-tja11xx.c b/drivers/net/phy/nxp-tja11xx.c
new file mode 100644
index 000..30dec5e605b
--- /dev/null
+++ b/drivers/net/phy/nxp-tja11xx.c
@@ -0,0 +1,277 @@
+// SPDX-License-Identifier: GPL-2.0
+/* NXP TJA1100 BroadRReach PHY driver
+ *
+ * Copyright (C) 2022 Michael Trimarchi
+ * Copyright (C) 2022 Ariel D'Alessandro
+ * Copyright (C) 2018 Marek Vasut
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define PHY_ID_MASK0xfff0
+#define PHY_ID_TJA1100 0x0180dc40
+#define PHY_ID_TJA1101 0x0180dd00
+
+#define MII_ECTRL 17
+#define MII_ECTRL_LINK_CONTROL BIT(15)
+#define MII_ECTRL_POWER_MODE_MASK GENMASK(14, 11)
+#define MII_ECTRL_POWER_MODE_NO_CHANGE (0x0 << 11)
+#define MII_ECTRL_POWER_MODE_NORMAL(0x3 << 11)
+#define MII_ECTRL_POWER_MODE_STANDBY (0xc << 11)
+#define MII_ECTRL_CABLE_TEST BIT(5)
+#define MII_ECTRL_CONFIG_ENBIT(2)
+#define MII_ECTRL_WAKE_REQUEST BIT(0)
+
+#define MII_CFG1 18
+#define MII_CFG1_MASTER_SLAVE BIT(15)
+#define MII_CFG1_AUTO_OP BIT(14)
+#define MII_CFG1_SLEEP_CONFIRM BIT(6)
+#define MII_CFG1_LED_MODE_MASK GENMASK(5, 4)
+#define MII_CFG1_LED_MODE_LINKUP 0
+#define MII_CFG1_LED_ENABLEBIT(3)
+
+#define MII_CFG2 19
+#define MII_CFG2_SLEEP_REQUEST_TO GENMASK(1, 0)
+#define MII_CFG2_SLEEP_REQUEST_TO_16MS 0x3
+
+#define MII_INTSRC 21
+#define MII_INTSRC_LINK_FAIL BIT(10)
+#define MII_INTSRC_LINK_UP BIT(9)
+#define MII_INTSRC_MASK(MII_INTSRC_LINK_FAIL | \
+MII_INTSRC_LINK_UP)
+#define MII_INTSRC_UV_ERR BIT(3)
+#define MII_INTSRC_TEMP_ERRBIT(1)
+
+#define MII_INTEN 22
+#define MII_INTEN_LINK_FAILBIT(10)
+#define MII_INTEN_LINK_UP BIT(9)
+#define MII_INTEN_UV_ERR BIT(3)
+#define MII_INTEN_TEMP_ERR BIT(1)
+
+#define MII_COMMSTAT 23
+#define MII_COMMSTAT_LINK_UP BIT(15)
+#define MII_COMMSTAT_SQI_STATE GENMASK(7, 5)
+#define MII_COMMSTAT_SQI_MAX 7
+
+#define MII_GENSTAT24
+#define MII_GENSTAT_PLL_LOCKED BIT(14)
+
+#define MII_EXTSTAT25
+#define MII_EXTSTAT_SHORT_DETECT BIT(8)
+#define MII_EXTSTAT_OPEN_DETECTBIT(7)
+#define MII_EXTSTAT_POLARITY_DETECTBIT(6)
+
+#define MII_COMMCFG27
+#define MII_COMMCFG_AUTO_OPBIT(15)
+
+static inline int tja11xx_set_bits(struct phy_device *phydev, u32 regnum,
+ u16 val)
+{
+ return phy_set_bits_mmd(phydev, MDIO_DEVAD_NONE, regnum, val);
+}
+
+static inline int tja11xx_clear_bits(struct phy_device *phydev, u32 regnum,
+u16 val)
+{
+ return phy_clear_bits_mmd(phydev, MDIO_DEVAD_NONE, regnum, val);
+}
+
+static inline int tja11xx_read(struct phy_device *phydev, int regnum)
+{
+ return phy_read(phydev, MDIO_DEVAD_NONE, regnum);
+}
+
+static inline int tja11xx_modify(struct phy_device *phydev, int regnum,
+u16 mask, u16 set)
+{
+ return ph
