Re: [PATCH v4 01/10] arm64: dts: rockchip: Add rk3588 GPU node

2024-06-06 Thread Kever Yang 



On 2024/5/29 01:03, Jianfeng Liu wrote:

From: Boris Brezillon 

Add Mali GPU Node to the RK3588 SoC DT including GPU clock
operating points

Signed-off-by: Boris Brezillon 
Signed-off-by: Sebastian Reichel 
Link: 
https://lore.kernel.org/r/20240326165232.73585-3-sebastian.reic...@collabora.com
Signed-off-by: Heiko Stuebner 

[ upstream commit: 6fca4edb93d335f29f81e484936f38a5eed6a9b1 ]

(cherry picked from commit 3cd15354ea0c8668812bc0b3a4136606c10803e9)
Signed-off-by: Jianfeng Liu 

Reviewed-by: Kever Yang 

Thanks,
- Kever

---

(no changes since v1)

  dts/upstream/src/arm64/rockchip/rk3588s.dtsi | 56 
  1 file changed, 56 insertions(+)

diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi 
b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
index 87b83c87bd5..89d40cff635 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
@@ -501,6 +501,62 @@
status = "disabled";
};
  
+	gpu: gpu@fb00 {

+   compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
+   reg = <0x0 0xfb00 0x0 0x20>;
+   #cooling-cells = <2>;
+   assigned-clocks = <_clk SCMI_CLK_GPU>;
+   assigned-clock-rates = <2>;
+   clocks = < CLK_GPU>, < CLK_GPU_COREGROUP>,
+< CLK_GPU_STACKS>;
+   clock-names = "core", "coregroup", "stacks";
+   dynamic-power-coefficient = <2982>;
+   interrupts = ,
+,
+;
+   interrupt-names = "job", "mmu", "gpu";
+   operating-points-v2 = <_opp_table>;
+   power-domains = < RK3588_PD_GPU>;
+   status = "disabled";
+
+   gpu_opp_table: opp-table {
+   compatible = "operating-points-v2";
+
+   opp-3 {
+   opp-hz = /bits/ 64 <3>;
+   opp-microvolt = <675000 675000 85>;
+   };
+   opp-4 {
+   opp-hz = /bits/ 64 <4>;
+   opp-microvolt = <675000 675000 85>;
+   };
+   opp-5 {
+   opp-hz = /bits/ 64 <5>;
+   opp-microvolt = <675000 675000 85>;
+   };
+   opp-6 {
+   opp-hz = /bits/ 64 <6>;
+   opp-microvolt = <675000 675000 85>;
+   };
+   opp-7 {
+   opp-hz = /bits/ 64 <7>;
+   opp-microvolt = <70 70 85>;
+   };
+   opp-8 {
+   opp-hz = /bits/ 64 <8>;
+   opp-microvolt = <75 75 85>;
+   };
+   opp-9 {
+   opp-hz = /bits/ 64 <9>;
+   opp-microvolt = <80 80 85>;
+   };
+   opp-10 {
+   opp-hz = /bits/ 64 <10>;
+   opp-microvolt = <85 85 85>;
+   };
+   };
+   };
+
pmu1grf: syscon@fd58a000 {
compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
reg = <0x0 0xfd58a000 0x0 0x1>;

[PATCH v4 01/10] arm64: dts: rockchip: Add rk3588 GPU node

2024-05-28 Thread Jianfeng Liu 
From: Boris Brezillon 

Add Mali GPU Node to the RK3588 SoC DT including GPU clock
operating points

Signed-off-by: Boris Brezillon 
Signed-off-by: Sebastian Reichel 
Link: 
https://lore.kernel.org/r/20240326165232.73585-3-sebastian.reic...@collabora.com
Signed-off-by: Heiko Stuebner 

[ upstream commit: 6fca4edb93d335f29f81e484936f38a5eed6a9b1 ]

(cherry picked from commit 3cd15354ea0c8668812bc0b3a4136606c10803e9)
Signed-off-by: Jianfeng Liu 
---

(no changes since v1)

 dts/upstream/src/arm64/rockchip/rk3588s.dtsi | 56 
 1 file changed, 56 insertions(+)

diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi 
b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
index 87b83c87bd5..89d40cff635 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
@@ -501,6 +501,62 @@
status = "disabled";
};
 
+   gpu: gpu@fb00 {
+   compatible = "rockchip,rk3588-mali", "arm,mali-valhall-csf";
+   reg = <0x0 0xfb00 0x0 0x20>;
+   #cooling-cells = <2>;
+   assigned-clocks = <_clk SCMI_CLK_GPU>;
+   assigned-clock-rates = <2>;
+   clocks = < CLK_GPU>, < CLK_GPU_COREGROUP>,
+< CLK_GPU_STACKS>;
+   clock-names = "core", "coregroup", "stacks";
+   dynamic-power-coefficient = <2982>;
+   interrupts = ,
+,
+;
+   interrupt-names = "job", "mmu", "gpu";
+   operating-points-v2 = <_opp_table>;
+   power-domains = < RK3588_PD_GPU>;
+   status = "disabled";
+
+   gpu_opp_table: opp-table {
+   compatible = "operating-points-v2";
+
+   opp-3 {
+   opp-hz = /bits/ 64 <3>;
+   opp-microvolt = <675000 675000 85>;
+   };
+   opp-4 {
+   opp-hz = /bits/ 64 <4>;
+   opp-microvolt = <675000 675000 85>;
+   };
+   opp-5 {
+   opp-hz = /bits/ 64 <5>;
+   opp-microvolt = <675000 675000 85>;
+   };
+   opp-6 {
+   opp-hz = /bits/ 64 <6>;
+   opp-microvolt = <675000 675000 85>;
+   };
+   opp-7 {
+   opp-hz = /bits/ 64 <7>;
+   opp-microvolt = <70 70 85>;
+   };
+   opp-8 {
+   opp-hz = /bits/ 64 <8>;
+   opp-microvolt = <75 75 85>;
+   };
+   opp-9 {
+   opp-hz = /bits/ 64 <9>;
+   opp-microvolt = <80 80 85>;
+   };
+   opp-10 {
+   opp-hz = /bits/ 64 <10>;
+   opp-microvolt = <85 85 85>;
+   };
+   };
+   };
+
pmu1grf: syscon@fd58a000 {
compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
reg = <0x0 0xfd58a000 0x0 0x1>;
-- 
2.34.1