Re: [PATCH v4 05/10] arm64: dts: rockchip: add USBDP phys on rk3588

2024-06-06 Thread Kever Yang 



On 2024/5/29 01:04, Jianfeng Liu wrote:

From: Sebastian Reichel 

Add both USB3-DisplayPort PHYs to RK3588 SoC DT.

Signed-off-by: Sebastian Reichel 
Link: 
https://lore.kernel.org/r/20240408225109.128953-7-sebastian.reic...@collabora.com
Signed-off-by: Heiko Stuebner 

[ upstream commit: e18e5e8188f2671abf63abe7db5f21555705130f ]

(cherry picked from commit 5110caca9865718616cf7093ed4a9a1bc54780db)
Signed-off-by: Jianfeng Liu 

Reviewed-by: Kever Yang 

Thanks,
- Kever

---

(no changes since v1)

  dts/upstream/src/arm64/rockchip/rk3588.dtsi  | 52 
  dts/upstream/src/arm64/rockchip/rk3588s.dtsi | 63 
  2 files changed, 115 insertions(+)

diff --git a/dts/upstream/src/arm64/rockchip/rk3588.dtsi 
b/dts/upstream/src/arm64/rockchip/rk3588.dtsi
index 5519c1430cb..4fdd047c9eb 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588.dtsi
@@ -17,6 +17,36 @@
reg = <0x0 0xfd5c 0x0 0x100>;
};
  
+	usbdpphy1_grf: syscon@fd5cc000 {

+   compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
+   reg = <0x0 0xfd5cc000 0x0 0x4000>;
+   };
+
+   usb2phy1_grf: syscon@fd5d4000 {
+   compatible = "rockchip,rk3588-usb2phy-grf", "syscon", 
"simple-mfd";
+   reg = <0x0 0xfd5d4000 0x0 0x4000>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   u2phy1: usb2phy@4000 {
+   compatible = "rockchip,rk3588-usb2phy";
+   reg = <0x4000 0x10>;
+   #clock-cells = <0>;
+   clocks = < CLK_USB2PHY_HDPTXRXPHY_REF>;
+   clock-names = "phyclk";
+   clock-output-names = "usb480m_phy1";
+   interrupts = ;
+   resets = < SRST_OTGPHY_U3_1>, < 
SRST_P_USB2PHY_U3_1_GRF0>;
+   reset-names = "phy", "apb";
+   status = "disabled";
+
+   u2phy1_otg: otg-port {
+   #phy-cells = <0>;
+   status = "disabled";
+   };
+   };
+   };
+
i2s8_8ch: i2s@fddc8000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfddc8000 0x0 0x1000>;
@@ -310,6 +340,28 @@
};
};
  
+	usbdp_phy1: phy@fed9 {

+   compatible = "rockchip,rk3588-usbdp-phy";
+   reg = <0x0 0xfed9 0x0 0x1>;
+   #phy-cells = <1>;
+   clocks = < CLK_USBDPPHY_MIPIDCPPHY_REF>,
+< CLK_USBDP_PHY1_IMMORTAL>,
+< PCLK_USBDPPHY1>,
+<>;
+   clock-names = "refclk", "immortal", "pclk", "utmi";
+   resets = < SRST_USBDP_COMBO_PHY1_INIT>,
+< SRST_USBDP_COMBO_PHY1_CMN>,
+< SRST_USBDP_COMBO_PHY1_LANE>,
+< SRST_USBDP_COMBO_PHY1_PCS>,
+< SRST_P_USBDPPHY1>;
+   reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
+   rockchip,u2phy-grf = <_grf>;
+   rockchip,usb-grf = <_grf>;
+   rockchip,usbdpphy-grf = <_grf>;
+   rockchip,vo-grf = <_grf>;
+   status = "disabled";
+   };
+
combphy1_ps: phy@fee1 {
compatible = "rockchip,rk3588-naneng-combphy";
reg = <0x0 0xfee1 0x0 0x100>;
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi 
b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
index 58d12969b7e..9063c0bb0f0 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
@@ -572,12 +572,23 @@
reg = <0x0 0xfd5a4000 0x0 0x2000>;
};
  
+	vo0_grf: syscon@fd5a6000 {

+   compatible = "rockchip,rk3588-vo-grf", "syscon";
+   reg = <0x0 0xfd5a6000 0x0 0x2000>;
+   clocks = < PCLK_VO0GRF>;
+   };
+
vo1_grf: syscon@fd5a8000 {
compatible = "rockchip,rk3588-vo-grf", "syscon";
reg = <0x0 0xfd5a8000 0x0 0x100>;
clocks = < PCLK_VO1GRF>;
};
  
+	usb_grf: syscon@fd5ac000 {

+   compatible = "rockchip,rk3588-usb-grf", "syscon";
+   reg = <0x0 0xfd5ac000 0x0 0x4000>;
+   };
+
php_grf: syscon@fd5b {
compatible = "rockchip,rk3588-php-grf", "syscon";
reg = <0x0 0xfd5b 0x0 0x1000>;
@@ -593,6 +604,36 @@
reg = <0x0 0xfd5c4000 0x0 0x100>;
};
  
+	usbdpphy0_grf: syscon@fd5c8000 {

+   compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
+   reg = <0x0 0xfd5c8000 0x0 0x4000>;
+   };
+
+   usb2phy0_grf: syscon@fd5d {
+   compatible = "rockchip,rk3588-usb2phy-grf", "syscon",

[PATCH v4 05/10] arm64: dts: rockchip: add USBDP phys on rk3588

2024-05-28 Thread Jianfeng Liu 
From: Sebastian Reichel 

Add both USB3-DisplayPort PHYs to RK3588 SoC DT.

Signed-off-by: Sebastian Reichel 
Link: 
https://lore.kernel.org/r/20240408225109.128953-7-sebastian.reic...@collabora.com
Signed-off-by: Heiko Stuebner 

[ upstream commit: e18e5e8188f2671abf63abe7db5f21555705130f ]

(cherry picked from commit 5110caca9865718616cf7093ed4a9a1bc54780db)
Signed-off-by: Jianfeng Liu 
---

(no changes since v1)

 dts/upstream/src/arm64/rockchip/rk3588.dtsi  | 52 
 dts/upstream/src/arm64/rockchip/rk3588s.dtsi | 63 
 2 files changed, 115 insertions(+)

diff --git a/dts/upstream/src/arm64/rockchip/rk3588.dtsi 
b/dts/upstream/src/arm64/rockchip/rk3588.dtsi
index 5519c1430cb..4fdd047c9eb 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588.dtsi
@@ -17,6 +17,36 @@
reg = <0x0 0xfd5c 0x0 0x100>;
};
 
+   usbdpphy1_grf: syscon@fd5cc000 {
+   compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
+   reg = <0x0 0xfd5cc000 0x0 0x4000>;
+   };
+
+   usb2phy1_grf: syscon@fd5d4000 {
+   compatible = "rockchip,rk3588-usb2phy-grf", "syscon", 
"simple-mfd";
+   reg = <0x0 0xfd5d4000 0x0 0x4000>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+
+   u2phy1: usb2phy@4000 {
+   compatible = "rockchip,rk3588-usb2phy";
+   reg = <0x4000 0x10>;
+   #clock-cells = <0>;
+   clocks = < CLK_USB2PHY_HDPTXRXPHY_REF>;
+   clock-names = "phyclk";
+   clock-output-names = "usb480m_phy1";
+   interrupts = ;
+   resets = < SRST_OTGPHY_U3_1>, < 
SRST_P_USB2PHY_U3_1_GRF0>;
+   reset-names = "phy", "apb";
+   status = "disabled";
+
+   u2phy1_otg: otg-port {
+   #phy-cells = <0>;
+   status = "disabled";
+   };
+   };
+   };
+
i2s8_8ch: i2s@fddc8000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfddc8000 0x0 0x1000>;
@@ -310,6 +340,28 @@
};
};
 
+   usbdp_phy1: phy@fed9 {
+   compatible = "rockchip,rk3588-usbdp-phy";
+   reg = <0x0 0xfed9 0x0 0x1>;
+   #phy-cells = <1>;
+   clocks = < CLK_USBDPPHY_MIPIDCPPHY_REF>,
+< CLK_USBDP_PHY1_IMMORTAL>,
+< PCLK_USBDPPHY1>,
+<>;
+   clock-names = "refclk", "immortal", "pclk", "utmi";
+   resets = < SRST_USBDP_COMBO_PHY1_INIT>,
+< SRST_USBDP_COMBO_PHY1_CMN>,
+< SRST_USBDP_COMBO_PHY1_LANE>,
+< SRST_USBDP_COMBO_PHY1_PCS>,
+< SRST_P_USBDPPHY1>;
+   reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
+   rockchip,u2phy-grf = <_grf>;
+   rockchip,usb-grf = <_grf>;
+   rockchip,usbdpphy-grf = <_grf>;
+   rockchip,vo-grf = <_grf>;
+   status = "disabled";
+   };
+
combphy1_ps: phy@fee1 {
compatible = "rockchip,rk3588-naneng-combphy";
reg = <0x0 0xfee1 0x0 0x100>;
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi 
b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
index 58d12969b7e..9063c0bb0f0 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
@@ -572,12 +572,23 @@
reg = <0x0 0xfd5a4000 0x0 0x2000>;
};
 
+   vo0_grf: syscon@fd5a6000 {
+   compatible = "rockchip,rk3588-vo-grf", "syscon";
+   reg = <0x0 0xfd5a6000 0x0 0x2000>;
+   clocks = < PCLK_VO0GRF>;
+   };
+
vo1_grf: syscon@fd5a8000 {
compatible = "rockchip,rk3588-vo-grf", "syscon";
reg = <0x0 0xfd5a8000 0x0 0x100>;
clocks = < PCLK_VO1GRF>;
};
 
+   usb_grf: syscon@fd5ac000 {
+   compatible = "rockchip,rk3588-usb-grf", "syscon";
+   reg = <0x0 0xfd5ac000 0x0 0x4000>;
+   };
+
php_grf: syscon@fd5b {
compatible = "rockchip,rk3588-php-grf", "syscon";
reg = <0x0 0xfd5b 0x0 0x1000>;
@@ -593,6 +604,36 @@
reg = <0x0 0xfd5c4000 0x0 0x100>;
};
 
+   usbdpphy0_grf: syscon@fd5c8000 {
+   compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
+   reg = <0x0 0xfd5c8000 0x0 0x4000>;
+   };
+
+   usb2phy0_grf: syscon@fd5d {
+   compatible = "rockchip,rk3588-usb2phy-grf", "syscon", 
"simple-mfd";
+   reg = <0x0 0xfd5d 0x0 0x4000>;
+