Re: [PATCH v4 06/10] arm64: dts: rockchip: add USB3 DRD controllers on rk3588

2024-06-06 Thread Kever Yang 



On 2024/5/29 01:04, Jianfeng Liu wrote:

From: Sebastian Reichel 

Add both USB3 dual-role controllers to the RK3588 devicetree.

Signed-off-by: Sebastian Reichel 
Link: 
https://lore.kernel.org/r/20240408225109.128953-8-sebastian.reic...@collabora.com
Signed-off-by: Heiko Stuebner 

[ upstream commit: 33f393a2a990e16f56931ca708295f31d2b44415 ]

(cherry picked from commit c7ed588e14f7dd04a92fb55f12680f94c7b14edf)
Signed-off-by: Jianfeng Liu 

Reviewed-by: Kever Yang 

Thanks,
- Kever

---

(no changes since v1)

  dts/upstream/src/arm64/rockchip/rk3588.dtsi  | 20 ++
  dts/upstream/src/arm64/rockchip/rk3588s.dtsi | 22 
  2 files changed, 42 insertions(+)

diff --git a/dts/upstream/src/arm64/rockchip/rk3588.dtsi 
b/dts/upstream/src/arm64/rockchip/rk3588.dtsi
index 4fdd047c9eb..5984016b5f9 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588.dtsi
@@ -7,6 +7,26 @@
  #include "rk3588-pinctrl.dtsi"
  
  / {

+   usb_host1_xhci: usb@fc40 {
+   compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
+   reg = <0x0 0xfc40 0x0 0x40>;
+   interrupts = ;
+   clocks = < REF_CLK_USB3OTG1>, < SUSPEND_CLK_USB3OTG1>,
+< ACLK_USB3OTG1>;
+   clock-names = "ref_clk", "suspend_clk", "bus_clk";
+   dr_mode = "otg";
+   phys = <_otg>, <_phy1 PHY_TYPE_USB3>;
+   phy-names = "usb2-phy", "usb3-phy";
+   phy_type = "utmi_wide";
+   power-domains = < RK3588_PD_USB>;
+   resets = < SRST_A_USB3OTG1>;
+   snps,dis_enblslpm_quirk;
+   snps,dis-u2-freeclk-exists-quirk;
+   snps,dis-del-phy-power-chg-quirk;
+   snps,dis-tx-ipgap-linecheck-quirk;
+   status = "disabled";
+   };
+
pcie30_phy_grf: syscon@fd5b8000 {
compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
reg = <0x0 0xfd5b8000 0x0 0x1>;
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi 
b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
index 9063c0bb0f0..b0a59ec5183 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
@@ -492,6 +492,28 @@
};
};
  
+	usb_host0_xhci: usb@fc00 {

+   compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
+   reg = <0x0 0xfc00 0x0 0x40>;
+   interrupts = ;
+   clocks = < REF_CLK_USB3OTG0>, < SUSPEND_CLK_USB3OTG0>,
+< ACLK_USB3OTG0>;
+   clock-names = "ref_clk", "suspend_clk", "bus_clk";
+   dr_mode = "otg";
+   phys = <_otg>, <_phy0 PHY_TYPE_USB3>;
+   phy-names = "usb2-phy", "usb3-phy";
+   phy_type = "utmi_wide";
+   power-domains = < RK3588_PD_USB>;
+   resets = < SRST_A_USB3OTG0>;
+   snps,dis_enblslpm_quirk;
+   snps,dis-u1-entry-quirk;
+   snps,dis-u2-entry-quirk;
+   snps,dis-u2-freeclk-exists-quirk;
+   snps,dis-del-phy-power-chg-quirk;
+   snps,dis-tx-ipgap-linecheck-quirk;
+   status = "disabled";
+   };
+
usb_host0_ehci: usb@fc80 {
compatible = "rockchip,rk3588-ehci", "generic-ehci";
reg = <0x0 0xfc80 0x0 0x4>;

[PATCH v4 06/10] arm64: dts: rockchip: add USB3 DRD controllers on rk3588

2024-05-28 Thread Jianfeng Liu 
From: Sebastian Reichel 

Add both USB3 dual-role controllers to the RK3588 devicetree.

Signed-off-by: Sebastian Reichel 
Link: 
https://lore.kernel.org/r/20240408225109.128953-8-sebastian.reic...@collabora.com
Signed-off-by: Heiko Stuebner 

[ upstream commit: 33f393a2a990e16f56931ca708295f31d2b44415 ]

(cherry picked from commit c7ed588e14f7dd04a92fb55f12680f94c7b14edf)
Signed-off-by: Jianfeng Liu 
---

(no changes since v1)

 dts/upstream/src/arm64/rockchip/rk3588.dtsi  | 20 ++
 dts/upstream/src/arm64/rockchip/rk3588s.dtsi | 22 
 2 files changed, 42 insertions(+)

diff --git a/dts/upstream/src/arm64/rockchip/rk3588.dtsi 
b/dts/upstream/src/arm64/rockchip/rk3588.dtsi
index 4fdd047c9eb..5984016b5f9 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588.dtsi
@@ -7,6 +7,26 @@
 #include "rk3588-pinctrl.dtsi"
 
 / {
+   usb_host1_xhci: usb@fc40 {
+   compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
+   reg = <0x0 0xfc40 0x0 0x40>;
+   interrupts = ;
+   clocks = < REF_CLK_USB3OTG1>, < SUSPEND_CLK_USB3OTG1>,
+< ACLK_USB3OTG1>;
+   clock-names = "ref_clk", "suspend_clk", "bus_clk";
+   dr_mode = "otg";
+   phys = <_otg>, <_phy1 PHY_TYPE_USB3>;
+   phy-names = "usb2-phy", "usb3-phy";
+   phy_type = "utmi_wide";
+   power-domains = < RK3588_PD_USB>;
+   resets = < SRST_A_USB3OTG1>;
+   snps,dis_enblslpm_quirk;
+   snps,dis-u2-freeclk-exists-quirk;
+   snps,dis-del-phy-power-chg-quirk;
+   snps,dis-tx-ipgap-linecheck-quirk;
+   status = "disabled";
+   };
+
pcie30_phy_grf: syscon@fd5b8000 {
compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
reg = <0x0 0xfd5b8000 0x0 0x1>;
diff --git a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi 
b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
index 9063c0bb0f0..b0a59ec5183 100644
--- a/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
+++ b/dts/upstream/src/arm64/rockchip/rk3588s.dtsi
@@ -492,6 +492,28 @@
};
};
 
+   usb_host0_xhci: usb@fc00 {
+   compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
+   reg = <0x0 0xfc00 0x0 0x40>;
+   interrupts = ;
+   clocks = < REF_CLK_USB3OTG0>, < SUSPEND_CLK_USB3OTG0>,
+< ACLK_USB3OTG0>;
+   clock-names = "ref_clk", "suspend_clk", "bus_clk";
+   dr_mode = "otg";
+   phys = <_otg>, <_phy0 PHY_TYPE_USB3>;
+   phy-names = "usb2-phy", "usb3-phy";
+   phy_type = "utmi_wide";
+   power-domains = < RK3588_PD_USB>;
+   resets = < SRST_A_USB3OTG0>;
+   snps,dis_enblslpm_quirk;
+   snps,dis-u1-entry-quirk;
+   snps,dis-u2-entry-quirk;
+   snps,dis-u2-freeclk-exists-quirk;
+   snps,dis-del-phy-power-chg-quirk;
+   snps,dis-tx-ipgap-linecheck-quirk;
+   status = "disabled";
+   };
+
usb_host0_ehci: usb@fc80 {
compatible = "rockchip,rk3588-ehci", "generic-ehci";
reg = <0x0 0xfc80 0x0 0x4>;
-- 
2.34.1