Re: [PATCH v4 12/17] riscv: Add a bypass clock for K210
Hi Sean > On 2/18/20 1:35 AM, Rick Chen wrote: > > Hi Sean > > > > This patch is relative about clock driver. > > It shall be named as clk instead of riscv > > Thanks > > Rick > > Should the other clock patches adding k210 clock support be prefixed > "clk:" as well? Sure, patch 11 and 13 as well Thanks Rick > > --Sean
Re: [PATCH v4 12/17] riscv: Add a bypass clock for K210
On 2/18/20 1:35 AM, Rick Chen wrote: > Hi Sean > > This patch is relative about clock driver. > It shall be named as clk instead of riscv > Thanks > Rick Should the other clock patches adding k210 clock support be prefixed "clk:" as well? --Sean
Re: [PATCH v4 12/17] riscv: Add a bypass clock for K210
Hi Sean
This patch is relative about clock driver.
It shall be named as clk instead of riscv
Thanks
Rick
> This is a small driver to do a software bypass of a clock if hardware
> bypass is not working. I have tried to write this in a generic fashion, so
> that it could be potentially broken out of the kendryte code at some future
> date. For the K210, it is used to have aclk bypass pll0 and use in0 instead
> so that the CPU keeps on working.
>
> Signed-off-by: Sean Anderson
> ---
>
> Changes in v4:
> - New
>
> drivers/clk/kendryte/Makefile | 2 +-
> drivers/clk/kendryte/bypass.c | 268 ++
> include/kendryte/bypass.h | 28
> 3 files changed, 297 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/kendryte/bypass.c
> create mode 100644 include/kendryte/bypass.h
>
> diff --git a/drivers/clk/kendryte/Makefile b/drivers/clk/kendryte/Makefile
> index c56d93ea1c..47f682fce3 100644
> --- a/drivers/clk/kendryte/Makefile
> +++ b/drivers/clk/kendryte/Makefile
> @@ -1 +1 @@
> -obj-y += pll.o
> +obj-y += bypass.o pll.o
> diff --git a/drivers/clk/kendryte/bypass.c b/drivers/clk/kendryte/bypass.c
> new file mode 100644
> index 00..5276591bfd
> --- /dev/null
> +++ b/drivers/clk/kendryte/bypass.c
> @@ -0,0 +1,268 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2020 Sean Anderson
> + */
> +
> +#include
> +
> +#include
> +#include
> +#include
> +#define LOG_CATEGORY UCLASS_CLK
> +#include
> +#include
> +
> +#define CLK_K210_BYPASS "k210_clk_bypass"
> +
> +/*
> + * This is a small driver to do a software bypass of a clock if hardware
> bypass
> + * is not working. I have tried to write this in a generic fashion, so that
> it
> + * could be potentially broken out of the kendryte code at some future date.
> + *
> + * Say you have the following clock configuration
> + *
> + * +---+ +---+
> + * |osc| |pll|
> + * +---+ +---+
> + * ^
> + */|
> + * / |
> + * / |
> + * / |
> + */|
> + * +---+ +---+
> + * |clk| |clk|
> + * +---+ +---+
> + *
> + * But the pll does not have a bypass, so when you configure the pll, the
> + * configuration needs to change to look like
> + *
> + * +---+ +---+
> + * |osc| |pll|
> + * +---+ +---+
> + * ^
> + * |\
> + * | \
> + * | \
> + * | \
> + * |\
> + * +---+ +---+
> + * |clk| |clk|
> + * +---+ +---+
> + *
> + * To set this up, create a bypass clock with bypassee=pll and alt=osc. When
> + * creating the child clocks, set their parent to the bypass clock. After
> + * creating all the children, call k210_bypass_setchildren().
> + */
> +
> +static int k210_bypass_dobypass(struct k210_bypass *bypass)
> +{
> + int ret, i;
> +
> + /*
> +* If we already have saved parents, then the children are already
> +* bypassed
> +*/
> + if (bypass->child_count && bypass->saved_parents[0])
> + return 0;
> +
> + for (i = 0; i < bypass->child_count; i++) {
> + struct clk *child = bypass->children[i];
> + struct clk *parent = clk_get_parent(child);
> +
> + if (IS_ERR(parent)) {
> + for (; i; i--)
> + bypass->saved_parents[i] = NULL;
> + return PTR_ERR(parent);
> + }
> + bypass->saved_parents[i] = parent;
> + }
> +
> + for (i = 0; i < bypass->child_count; i++) {
> + struct clk *child = bypass->children[i];
> +
> + ret = clk_set_parent(child, bypass->alt);
> + if (ret) {
> + for (; i; i--)
> + clk_set_parent(bypass->children[i],
> + bypass->saved_parents[i]);
> + for (i = 0; i < bypass->child_count; i++)
> + bypass->saved_parents[i] = NULL;
> + return ret;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static int k210_bypass_unbypass(struct k210_bypass *bypass)
> +{
> + int err, ret, i;
> +
> + if (!bypass->child_count && !bypass->saved_parents[0]) {
> + log_warning("Cannot unbypass children; dobypass not called
> first\n");
> + return 0;
> + }
> +
> + ret = 0;
> + for (i = 0; i < bypass->child_count; i++) {
> + err = clk_set_parent(bypass->children[i],
> +bypass->saved_parents[i]);
> + if (err)
> + ret = err;
> + bypass->saved_parents[i] = NULL;
> + }
> + return ret;
> +}
> +
> +static ulong k210_bypass_get_rate(struct clk *clk)
> +{
> + struct k210_bypass *bypass = to_k210_bypass(clk);
> + const struct clk_ops *ops = bypass->bypassee_ops;
> +
> + if (ops->get_rate)
> + return ops->get_rate(bypass->bypassee);
> + else
> +
[PATCH v4 12/17] riscv: Add a bypass clock for K210
This is a small driver to do a software bypass of a clock if hardware
bypass is not working. I have tried to write this in a generic fashion, so
that it could be potentially broken out of the kendryte code at some future
date. For the K210, it is used to have aclk bypass pll0 and use in0 instead
so that the CPU keeps on working.
Signed-off-by: Sean Anderson
---
Changes in v4:
- New
drivers/clk/kendryte/Makefile | 2 +-
drivers/clk/kendryte/bypass.c | 268 ++
include/kendryte/bypass.h | 28
3 files changed, 297 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/kendryte/bypass.c
create mode 100644 include/kendryte/bypass.h
diff --git a/drivers/clk/kendryte/Makefile b/drivers/clk/kendryte/Makefile
index c56d93ea1c..47f682fce3 100644
--- a/drivers/clk/kendryte/Makefile
+++ b/drivers/clk/kendryte/Makefile
@@ -1 +1 @@
-obj-y += pll.o
+obj-y += bypass.o pll.o
diff --git a/drivers/clk/kendryte/bypass.c b/drivers/clk/kendryte/bypass.c
new file mode 100644
index 00..5276591bfd
--- /dev/null
+++ b/drivers/clk/kendryte/bypass.c
@@ -0,0 +1,268 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Sean Anderson
+ */
+
+#include
+
+#include
+#include
+#include
+#define LOG_CATEGORY UCLASS_CLK
+#include
+#include
+
+#define CLK_K210_BYPASS "k210_clk_bypass"
+
+/*
+ * This is a small driver to do a software bypass of a clock if hardware bypass
+ * is not working. I have tried to write this in a generic fashion, so that it
+ * could be potentially broken out of the kendryte code at some future date.
+ *
+ * Say you have the following clock configuration
+ *
+ * +---+ +---+
+ * |osc| |pll|
+ * +---+ +---+
+ * ^
+ */|
+ * / |
+ * / |
+ * / |
+ */|
+ * +---+ +---+
+ * |clk| |clk|
+ * +---+ +---+
+ *
+ * But the pll does not have a bypass, so when you configure the pll, the
+ * configuration needs to change to look like
+ *
+ * +---+ +---+
+ * |osc| |pll|
+ * +---+ +---+
+ * ^
+ * |\
+ * | \
+ * | \
+ * | \
+ * |\
+ * +---+ +---+
+ * |clk| |clk|
+ * +---+ +---+
+ *
+ * To set this up, create a bypass clock with bypassee=pll and alt=osc. When
+ * creating the child clocks, set their parent to the bypass clock. After
+ * creating all the children, call k210_bypass_setchildren().
+ */
+
+static int k210_bypass_dobypass(struct k210_bypass *bypass)
+{
+ int ret, i;
+
+ /*
+* If we already have saved parents, then the children are already
+* bypassed
+*/
+ if (bypass->child_count && bypass->saved_parents[0])
+ return 0;
+
+ for (i = 0; i < bypass->child_count; i++) {
+ struct clk *child = bypass->children[i];
+ struct clk *parent = clk_get_parent(child);
+
+ if (IS_ERR(parent)) {
+ for (; i; i--)
+ bypass->saved_parents[i] = NULL;
+ return PTR_ERR(parent);
+ }
+ bypass->saved_parents[i] = parent;
+ }
+
+ for (i = 0; i < bypass->child_count; i++) {
+ struct clk *child = bypass->children[i];
+
+ ret = clk_set_parent(child, bypass->alt);
+ if (ret) {
+ for (; i; i--)
+ clk_set_parent(bypass->children[i],
+ bypass->saved_parents[i]);
+ for (i = 0; i < bypass->child_count; i++)
+ bypass->saved_parents[i] = NULL;
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int k210_bypass_unbypass(struct k210_bypass *bypass)
+{
+ int err, ret, i;
+
+ if (!bypass->child_count && !bypass->saved_parents[0]) {
+ log_warning("Cannot unbypass children; dobypass not called
first\n");
+ return 0;
+ }
+
+ ret = 0;
+ for (i = 0; i < bypass->child_count; i++) {
+ err = clk_set_parent(bypass->children[i],
+bypass->saved_parents[i]);
+ if (err)
+ ret = err;
+ bypass->saved_parents[i] = NULL;
+ }
+ return ret;
+}
+
+static ulong k210_bypass_get_rate(struct clk *clk)
+{
+ struct k210_bypass *bypass = to_k210_bypass(clk);
+ const struct clk_ops *ops = bypass->bypassee_ops;
+
+ if (ops->get_rate)
+ return ops->get_rate(bypass->bypassee);
+ else
+ return clk_get_parent_rate(bypass->bypassee);
+}
+
+static ulong k210_bypass_set_rate(struct clk *clk, unsigned long rate)
+{
+ int ret;
+ struct k210_bypass *bypass = to_k210_bypass(clk);
+ const struct clk_ops *ops = bypass->bypassee_ops;
+
+ /* Don't bother bypassing if we aren't going to set the rate */
+ if (!ops->set_rate)
+ return k210_bypass_get_rate(clk);
+
