Re: [PATCH v4 2/8] arm: mach-k3: common: Reserve video memory from end of the RAM

[Nikhil Jain]

Hi Devarsh,

On 25/11/23 21:56, Devarsh Thakkar wrote:
> Setup video memory before page table reservation using
> "spl_reserve_video_from_ram_top" which ensures framebuffer memory gets
> reserved from the end of RAM.
>
> This is done to enable the next stage to directly skip the
> pre-reserved area from previous stage right from the end of RAM without
> having to make any gaps/holes to accommodate those regions which was the
> case before as previous stage reserved region not from the end of RAM.
>
> Use gd->ram_top instead of local ram_top and update gd->reloc_addr after
> each reservation to ensure further regions are reserved properly.
>
> Signed-off-by: Devarsh Thakkar 

Reviewed-by: Nikhil M Jain 

Regards,
Nikhil
> ---
> V2:
>  - Make a generic function "spl_reserve_video" under
>common/spl which can be re-used by other platforms too
>for reserving video memory from spl.
>
> V3:
>  - Change spl_reserve_video to spl_reserve_video_from_ram_top
>which enforce framebuffer reservation from end of RAM
>  - Use gd->ram_top instead of local ram_top and update
>gd->reloc_addr after each reservation
>  - Print error message on framebuffer reservation
>
> V4:
>  - Split this into a separate patch
> ---
>  arch/arm/mach-k3/common.c | 17 -
>  1 file changed, 12 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
> index fd400e7e3d..42ceeb5296 100644
> --- a/arch/arm/mach-k3/common.c
> +++ b/arch/arm/mach-k3/common.c
> @@ -524,19 +524,26 @@ void remove_fwl_configs(struct fwl_data *fwl_data, 
> size_t fwl_data_size)
>  void spl_enable_cache(void)
>  {
>  #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
> - phys_addr_t ram_top = CFG_SYS_SDRAM_BASE;
> + gd->ram_top = CFG_SYS_SDRAM_BASE;
> + int ret = 0;
>  
>   dram_init();
>  
>   /* reserve TLB table */
>   gd->arch.tlb_size = PGTABLE_SIZE;
>  
> - ram_top += get_effective_memsize();
> + gd->ram_top += get_effective_memsize();
>   /* keep ram_top in the 32-bit address space */
> - if (ram_top >= 0x1)
> - ram_top = (phys_addr_t) 0x1;
> + if (gd->ram_top >= 0x1)
> + gd->ram_top = (phys_addr_t)0x1;
>  
> - gd->arch.tlb_addr = ram_top - gd->arch.tlb_size;
> + gd->relocaddr = gd->ram_top;
> +
> + ret = spl_reserve_video_from_ram_top();
> + if (ret)
> + panic("Failed to reserve framebuffer memory (%d)\n", ret);
> +
> + gd->arch.tlb_addr = gd->relocaddr - gd->arch.tlb_size;
>   gd->arch.tlb_addr &= ~(0x1 - 1);
>   debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
> gd->arch.tlb_addr + gd->arch.tlb_size);

[PATCH v4 2/8] arm: mach-k3: common: Reserve video memory from end of the RAM

[Devarsh Thakkar]

Setup video memory before page table reservation using
"spl_reserve_video_from_ram_top" which ensures framebuffer memory gets
reserved from the end of RAM.

This is done to enable the next stage to directly skip the
pre-reserved area from previous stage right from the end of RAM without
having to make any gaps/holes to accommodate those regions which was the
case before as previous stage reserved region not from the end of RAM.

Use gd->ram_top instead of local ram_top and update gd->reloc_addr after
each reservation to ensure further regions are reserved properly.

Signed-off-by: Devarsh Thakkar 
---
V2:
 - Make a generic function "spl_reserve_video" under
   common/spl which can be re-used by other platforms too
   for reserving video memory from spl.

V3:
 - Change spl_reserve_video to spl_reserve_video_from_ram_top
   which enforce framebuffer reservation from end of RAM
 - Use gd->ram_top instead of local ram_top and update
   gd->reloc_addr after each reservation
 - Print error message on framebuffer reservation

V4:
 - Split this into a separate patch
---
 arch/arm/mach-k3/common.c | 17 -
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index fd400e7e3d..42ceeb5296 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -524,19 +524,26 @@ void remove_fwl_configs(struct fwl_data *fwl_data, size_t 
fwl_data_size)
 void spl_enable_cache(void)
 {
 #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
-   phys_addr_t ram_top = CFG_SYS_SDRAM_BASE;
+   gd->ram_top = CFG_SYS_SDRAM_BASE;
+   int ret = 0;
 
dram_init();
 
/* reserve TLB table */
gd->arch.tlb_size = PGTABLE_SIZE;
 
-   ram_top += get_effective_memsize();
+   gd->ram_top += get_effective_memsize();
/* keep ram_top in the 32-bit address space */
-   if (ram_top >= 0x1)
-   ram_top = (phys_addr_t) 0x1;
+   if (gd->ram_top >= 0x1)
+   gd->ram_top = (phys_addr_t)0x1;
 
-   gd->arch.tlb_addr = ram_top - gd->arch.tlb_size;
+   gd->relocaddr = gd->ram_top;
+
+   ret = spl_reserve_video_from_ram_top();
+   if (ret)
+   panic("Failed to reserve framebuffer memory (%d)\n", ret);
+
+   gd->arch.tlb_addr = gd->relocaddr - gd->arch.tlb_size;
gd->arch.tlb_addr &= ~(0x1 - 1);
debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
  gd->arch.tlb_addr + gd->arch.tlb_size);
-- 
2.34.1