[PATCH v5 06/10] ARM: dts: add devicetree for Renesas RZ/N1 SoC
This is taken directly from Linux kernel 6.3
(commit 457391b0380335d5e9a5babdec90ac53928b23b4)
Signed-off-by: Ralph Siemsen
Reviewed-by: Marek Vasut
---
Changes in v6:
- updated comment to reflact linux 6.3, and add commit hash.
(the files themselves have not changed)
Changes in v5:
- r9a06g032.dtsi now identical to linux 6.3-rc7 version
Changes in v3:
- add syscon phandle to ddrctl
- simplify UART compatible strings
arch/arm/dts/r9a06g032.dtsi | 477 ++
include/dt-bindings/clock/r9a06g032-sysctrl.h | 149 ++
2 files changed, 626 insertions(+)
create mode 100644 arch/arm/dts/r9a06g032.dtsi
create mode 100644 include/dt-bindings/clock/r9a06g032-sysctrl.h
diff --git a/arch/arm/dts/r9a06g032.dtsi b/arch/arm/dts/r9a06g032.dtsi
new file mode 100644
index 00..0fa565a1c3
--- /dev/null
+++ b/arch/arm/dts/r9a06g032.dtsi
@@ -0,0 +1,477 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ */
+
+#include
+#include
+
+/ {
+ compatible = "renesas,r9a06g032";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0>;
+ clocks = < R9A06G032_CLK_A7MP>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <1>;
+ clocks = < R9A06G032_CLK_A7MP>;
+ enable-method = "renesas,r9a06g032-smp";
+ cpu-release-addr = <0 0x4000c204>;
+ };
+ };
+
+ ext_jtag_clk: extjtagclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ ext_mclk: extmclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <4000>;
+ };
+
+ ext_rgmii_ref: extrgmiiref {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ ext_rtc_clk: extrtcclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <>;
+ ranges;
+
+ rtc0: rtc@40006000 {
+ compatible = "renesas,r9a06g032-rtc",
"renesas,rzn1-rtc";
+ reg = <0x40006000 0x1000>;
+ interrupts = ,
+,
+;
+ interrupt-names = "alarm", "timer", "pps";
+ clocks = < R9A06G032_HCLK_RTC>;
+ clock-names = "hclk";
+ power-domains = <>;
+ status = "disabled";
+ };
+
+ wdt0: watchdog@40008000 {
+ compatible = "renesas,r9a06g032-wdt",
"renesas,rzn1-wdt";
+ reg = <0x40008000 0x1000>;
+ interrupts = ;
+ clocks = < R9A06G032_CLK_WATCHDOG>;
+ status = "disabled";
+ };
+
+ wdt1: watchdog@40009000 {
+ compatible = "renesas,r9a06g032-wdt",
"renesas,rzn1-wdt";
+ reg = <0x40009000 0x1000>;
+ interrupts = ;
+ clocks = < R9A06G032_CLK_WATCHDOG>;
+ status = "disabled";
+ };
+
+ sysctrl: system-controller@4000c000 {
+ compatible = "renesas,r9a06g032-sysctrl";
+ reg = <0x4000c000 0x1000>;
+ status = "okay";
+ #clock-cells = <1>;
+ #power-domain-cells = <0>;
+
+ clocks = <_mclk>, <_rtc_clk>,
+ <_jtag_clk>, <_rgmii_ref>;
+ clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ dmamux: dma-router@a0 {
+ compatible = "renesas,rzn1-dmamux";
+ reg = <0xa0 4>;
+ #dma-cells = <6>;
+ dma-requests = <32>;
+ dma-masters = < >;
+ };
+ };
+
+
Re: [PATCH v5 06/10] ARM: dts: add devicetree for Renesas RZ/N1 SoC
On 4/24/23 03:15, Ralph Siemsen wrote: This is taken directly from Linux kernel 6.3-rc7. You can now use final 6.3 since it was released . A commit ID of that 6.3 (source commit in Linux) in the commit message is a good practice. Signed-off-by: Ralph Siemsen Reviewed-by: Marek Vasut
[PATCH v5 06/10] ARM: dts: add devicetree for Renesas RZ/N1 SoC
This is taken directly from Linux kernel 6.3-rc7.
Signed-off-by: Ralph Siemsen
---
Changes in v5:
- r9a06g032.dtsi now identical to linux 6.3-rc7 version
Changes in v3:
- add syscon phandle to ddrctl
- simplify UART compatible strings
arch/arm/dts/r9a06g032.dtsi | 477 ++
include/dt-bindings/clock/r9a06g032-sysctrl.h | 149 ++
2 files changed, 626 insertions(+)
create mode 100644 arch/arm/dts/r9a06g032.dtsi
create mode 100644 include/dt-bindings/clock/r9a06g032-sysctrl.h
diff --git a/arch/arm/dts/r9a06g032.dtsi b/arch/arm/dts/r9a06g032.dtsi
new file mode 100644
index 00..0fa565a1c3
--- /dev/null
+++ b/arch/arm/dts/r9a06g032.dtsi
@@ -0,0 +1,477 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ */
+
+#include
+#include
+
+/ {
+ compatible = "renesas,r9a06g032";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0>;
+ clocks = < R9A06G032_CLK_A7MP>;
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <1>;
+ clocks = < R9A06G032_CLK_A7MP>;
+ enable-method = "renesas,r9a06g032-smp";
+ cpu-release-addr = <0 0x4000c204>;
+ };
+ };
+
+ ext_jtag_clk: extjtagclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ ext_mclk: extmclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <4000>;
+ };
+
+ ext_rgmii_ref: extrgmiiref {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ ext_rtc_clk: extrtcclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <>;
+ ranges;
+
+ rtc0: rtc@40006000 {
+ compatible = "renesas,r9a06g032-rtc",
"renesas,rzn1-rtc";
+ reg = <0x40006000 0x1000>;
+ interrupts = ,
+,
+;
+ interrupt-names = "alarm", "timer", "pps";
+ clocks = < R9A06G032_HCLK_RTC>;
+ clock-names = "hclk";
+ power-domains = <>;
+ status = "disabled";
+ };
+
+ wdt0: watchdog@40008000 {
+ compatible = "renesas,r9a06g032-wdt",
"renesas,rzn1-wdt";
+ reg = <0x40008000 0x1000>;
+ interrupts = ;
+ clocks = < R9A06G032_CLK_WATCHDOG>;
+ status = "disabled";
+ };
+
+ wdt1: watchdog@40009000 {
+ compatible = "renesas,r9a06g032-wdt",
"renesas,rzn1-wdt";
+ reg = <0x40009000 0x1000>;
+ interrupts = ;
+ clocks = < R9A06G032_CLK_WATCHDOG>;
+ status = "disabled";
+ };
+
+ sysctrl: system-controller@4000c000 {
+ compatible = "renesas,r9a06g032-sysctrl";
+ reg = <0x4000c000 0x1000>;
+ status = "okay";
+ #clock-cells = <1>;
+ #power-domain-cells = <0>;
+
+ clocks = <_mclk>, <_rtc_clk>,
+ <_jtag_clk>, <_rgmii_ref>;
+ clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ dmamux: dma-router@a0 {
+ compatible = "renesas,rzn1-dmamux";
+ reg = <0xa0 4>;
+ #dma-cells = <6>;
+ dma-requests = <32>;
+ dma-masters = < >;
+ };
+ };
+
+ udc: usb@4001e000 {
+ compatible = "renesas,r9a06g032-usbf",
"renesas,rzn1-usbf";
+ reg = <0x4001e000 0x2000>;
+ interrupts =
