Re: [PATCH v6] pinctrl: nuvoton: Add NPCM8xx pinctrl driver

2022-05-27 Thread Stanley Chu 
Hi Sean,

Thanks for the review, it will be revised in the next version.

--
Stanley

On Fri, May 27, 2022 at 12:06 PM Sean Anderson  wrote:
>
> On 5/3/22 1:33 AM, Stanley Chu wrote:
> > Add Nuvoton BMC NPCM845 Pinmux and Pinconf support.
> >
> > Signed-off-by: Stanley Chu 
> > ---
> > v6:
> >   - sync pin name with Linux driver
> >   - add support for gpi35/gpi36/gpio183~189
> > v5:
> >   - lower-case hex consistently
> >   - use uint type for pin list in the group_config struct
> > v4:
> >   - correct the pin flags, add slew rate control suuport for rgmii pins
> > v3:
> >   - separate group names and function names in different tables
> > to allow for adding additional functions
> > v2:
> >   - drop the WDnRCRB/CORSTCB register access, it is not for
> > GPIO modules reset control
> > ---
> >   drivers/pinctrl/Kconfig   |1 +
> >   drivers/pinctrl/Makefile  |1 +
> >   drivers/pinctrl/nuvoton/Kconfig   |   12 +
> >   drivers/pinctrl/nuvoton/Makefile  |1 +
> >   drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 1225 +
> >   5 files changed, 1240 insertions(+)
> >   create mode 100644 drivers/pinctrl/nuvoton/Kconfig
> >   create mode 100644 drivers/pinctrl/nuvoton/Makefile
> >   create mode 100644 drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
> >
> > diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
> > index 13033198f9..e14e885c3e 100644
> > --- a/drivers/pinctrl/Kconfig
> > +++ b/drivers/pinctrl/Kconfig
> > @@ -339,6 +339,7 @@ source "drivers/pinctrl/mscc/Kconfig"
> >   source "drivers/pinctrl/mtmips/Kconfig"
> >   source "drivers/pinctrl/mvebu/Kconfig"
> >   source "drivers/pinctrl/nexell/Kconfig"
> > +source "drivers/pinctrl/nuvoton/Kconfig"
> >   source "drivers/pinctrl/nxp/Kconfig"
> >   source "drivers/pinctrl/renesas/Kconfig"
> >   source "drivers/pinctrl/rockchip/Kconfig"
> > diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
> > index 9b4978253b..aa31f31c16 100644
> > --- a/drivers/pinctrl/Makefile
> > +++ b/drivers/pinctrl/Makefile
> > @@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_ASPEED) += aspeed/
> >   obj-$(CONFIG_ARCH_ATH79) += ath79/
> >   obj-$(CONFIG_PINCTRL_INTEL) += intel/
> >   obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
> > +obj-$(CONFIG_ARCH_NPCM) += nuvoton/
> >   obj-$(CONFIG_ARCH_RMOBILE) += renesas/
> >   obj-$(CONFIG_PINCTRL_SANDBOX)   += pinctrl-sandbox.o
> >   obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/
> > diff --git a/drivers/pinctrl/nuvoton/Kconfig 
> > b/drivers/pinctrl/nuvoton/Kconfig
> > new file mode 100644
> > index 00..519539d6ae
> > --- /dev/null
> > +++ b/drivers/pinctrl/nuvoton/Kconfig
> > @@ -0,0 +1,12 @@
> > +config PINCTRL_NPCM8XX
> > + bool "Pinctrl driver for Nuvoton NPCM8XX"
> > + depends on DM && PINCTRL_GENERIC && ARCH_NPCM8XX
> > + help
> > +   Support pin muxing and pin configuration on
> > +   Nuvoton NPCM8XX SoC.
> > +
> > +   The NPCM8XX contains 256 GPIO pins. Most of them are
> > +   multiplexed with other system functions. These pins can
> > +   be configured as either GPIO pin or alternate function.
> > +   It also supports basic configurations such as pull up/down,
> > +   drive-strength, and slew rate control for some of the pins.
> > diff --git a/drivers/pinctrl/nuvoton/Makefile 
> > b/drivers/pinctrl/nuvoton/Makefile
> > new file mode 100644
> > index 00..a6dfdf3672
> > --- /dev/null
> > +++ b/drivers/pinctrl/nuvoton/Makefile
> > @@ -0,0 +1 @@
> > +obj-$(CONFIG_PINCTRL_NPCM8XX)+= pinctrl-npcm8xx.o
> > diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c 
> > b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
> > new file mode 100644
> > index 00..cc49310506
> > --- /dev/null
> > +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
> > @@ -0,0 +1,1225 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (c) 2022 Nuvoton Technology Corp.
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +/* GCR register offsets */
> > +#define WD0RCR   0x38
> > +#define WD1RCR   0x3c
> > +#define WD2RCR   0x40
> > +#define SWRSTC1  0x44
> > +#define SWRSTC2  0x48
> > +#define SWRSTC3  0x4c
> > +#define SWRSTC4  0x50
> > +#define CORSTC   0x5c
> > +#define FLOCKR1  0x74
> > +#define INTCR4   0xc0
> > +#define I2CSEGSEL0xe0
> > +#define MFSEL1   0x260
> > +#define MFSEL2   0x264
> > +#define MFSEL3   0x268
> > +#define MFSEL4   0x26c
> > +#define MFSEL5   0x270
> > +#define MFSEL6   0x274
> > +#define MFSEL7   0x278
> > +
> > +/* GPIO register offsets */
> > +#define GPIO_POL 0x08 /* Polarity */
> > +#define GPIO_DOUT0x0c /* Data OUT */
> > +#define GPIO_OTYP0x14 /* Output Type

Re: [PATCH v6] pinctrl: nuvoton: Add NPCM8xx pinctrl driver

2022-05-26 Thread Sean Anderson 

On 5/3/22 1:33 AM, Stanley Chu wrote:

Add Nuvoton BMC NPCM845 Pinmux and Pinconf support.

Signed-off-by: Stanley Chu 
---
v6:
  - sync pin name with Linux driver
  - add support for gpi35/gpi36/gpio183~189
v5:
  - lower-case hex consistently
  - use uint type for pin list in the group_config struct
v4:
  - correct the pin flags, add slew rate control suuport for rgmii pins
v3:
  - separate group names and function names in different tables
to allow for adding additional functions
v2:
  - drop the WDnRCRB/CORSTCB register access, it is not for
GPIO modules reset control
---
  drivers/pinctrl/Kconfig   |1 +
  drivers/pinctrl/Makefile  |1 +
  drivers/pinctrl/nuvoton/Kconfig   |   12 +
  drivers/pinctrl/nuvoton/Makefile  |1 +
  drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 1225 +
  5 files changed, 1240 insertions(+)
  create mode 100644 drivers/pinctrl/nuvoton/Kconfig
  create mode 100644 drivers/pinctrl/nuvoton/Makefile
  create mode 100644 drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 13033198f9..e14e885c3e 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -339,6 +339,7 @@ source "drivers/pinctrl/mscc/Kconfig"
  source "drivers/pinctrl/mtmips/Kconfig"
  source "drivers/pinctrl/mvebu/Kconfig"
  source "drivers/pinctrl/nexell/Kconfig"
+source "drivers/pinctrl/nuvoton/Kconfig"
  source "drivers/pinctrl/nxp/Kconfig"
  source "drivers/pinctrl/renesas/Kconfig"
  source "drivers/pinctrl/rockchip/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 9b4978253b..aa31f31c16 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_ASPEED) += aspeed/
  obj-$(CONFIG_ARCH_ATH79) += ath79/
  obj-$(CONFIG_PINCTRL_INTEL) += intel/
  obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
+obj-$(CONFIG_ARCH_NPCM) += nuvoton/
  obj-$(CONFIG_ARCH_RMOBILE) += renesas/
  obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o
  obj-$(CONFIG_PINCTRL_SUNXI)   += sunxi/
diff --git a/drivers/pinctrl/nuvoton/Kconfig b/drivers/pinctrl/nuvoton/Kconfig
new file mode 100644
index 00..519539d6ae
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/Kconfig
@@ -0,0 +1,12 @@
+config PINCTRL_NPCM8XX
+   bool "Pinctrl driver for Nuvoton NPCM8XX"
+   depends on DM && PINCTRL_GENERIC && ARCH_NPCM8XX
+   help
+ Support pin muxing and pin configuration on
+ Nuvoton NPCM8XX SoC.
+
+ The NPCM8XX contains 256 GPIO pins. Most of them are
+ multiplexed with other system functions. These pins can
+ be configured as either GPIO pin or alternate function.
+ It also supports basic configurations such as pull up/down,
+ drive-strength, and slew rate control for some of the pins.
diff --git a/drivers/pinctrl/nuvoton/Makefile b/drivers/pinctrl/nuvoton/Makefile
new file mode 100644
index 00..a6dfdf3672
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_PINCTRL_NPCM8XX)  += pinctrl-npcm8xx.o
diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c 
b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
new file mode 100644
index 00..cc49310506
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
@@ -0,0 +1,1225 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Nuvoton Technology Corp.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* GCR register offsets */
+#define WD0RCR 0x38
+#define WD1RCR 0x3c
+#define WD2RCR 0x40
+#define SWRSTC10x44
+#define SWRSTC20x48
+#define SWRSTC30x4c
+#define SWRSTC40x50
+#define CORSTC 0x5c
+#define FLOCKR10x74
+#define INTCR4 0xc0
+#define I2CSEGSEL  0xe0
+#define MFSEL1 0x260
+#define MFSEL2 0x264
+#define MFSEL3 0x268
+#define MFSEL4 0x26c
+#define MFSEL5 0x270
+#define MFSEL6 0x274
+#define MFSEL7 0x278
+
+/* GPIO register offsets */
+#define GPIO_POL   0x08 /* Polarity */
+#define GPIO_DOUT  0x0c /* Data OUT */
+#define GPIO_OTYP  0x14 /* Output Type */
+#define GPIO_PU0x1c /* Pull-up */
+#define GPIO_PD0x20 /* Pull-down */
+#define GPIO_DBNC  0x24 /* Debounce */
+#define GPIO_EVEN  0x40 /* Event Enable */
+#define GPIO_EVST  0x4c /* Event Status */
+#define GPIO_IEM   0x58 /* Input Enable */
+#define GPIO_OSRC  0x5c /* Output Slew-Rate Control */
+#define GPIO_ODSC  0x60 /* Output Drive Strength Control */
+#define GPIO_OES   0x70 /* Output Enable Set */
+#define GPIO_OEC   0x74 /* Output Enable Clear */
+
+#define NPCM8XX_GPIO_PER_BANK  32
+#define GPIOX_OFFSET   16
+
+/* The lists contain alternate GPIO pins of the function */
+/* Serial Interfaces */
+static

[PATCH v6] pinctrl: nuvoton: Add NPCM8xx pinctrl driver

2022-05-02 Thread Stanley Chu 
Add Nuvoton BMC NPCM845 Pinmux and Pinconf support.

Signed-off-by: Stanley Chu 
---
v6:
 - sync pin name with Linux driver
 - add support for gpi35/gpi36/gpio183~189
v5:
 - lower-case hex consistently
 - use uint type for pin list in the group_config struct
v4:
 - correct the pin flags, add slew rate control suuport for rgmii pins
v3:
 - separate group names and function names in different tables
   to allow for adding additional functions
v2:
 - drop the WDnRCRB/CORSTCB register access, it is not for
   GPIO modules reset control
---
 drivers/pinctrl/Kconfig   |1 +
 drivers/pinctrl/Makefile  |1 +
 drivers/pinctrl/nuvoton/Kconfig   |   12 +
 drivers/pinctrl/nuvoton/Makefile  |1 +
 drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c | 1225 +
 5 files changed, 1240 insertions(+)
 create mode 100644 drivers/pinctrl/nuvoton/Kconfig
 create mode 100644 drivers/pinctrl/nuvoton/Makefile
 create mode 100644 drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 13033198f9..e14e885c3e 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -339,6 +339,7 @@ source "drivers/pinctrl/mscc/Kconfig"
 source "drivers/pinctrl/mtmips/Kconfig"
 source "drivers/pinctrl/mvebu/Kconfig"
 source "drivers/pinctrl/nexell/Kconfig"
+source "drivers/pinctrl/nuvoton/Kconfig"
 source "drivers/pinctrl/nxp/Kconfig"
 source "drivers/pinctrl/renesas/Kconfig"
 source "drivers/pinctrl/rockchip/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 9b4978253b..aa31f31c16 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_ARCH_ASPEED) += aspeed/
 obj-$(CONFIG_ARCH_ATH79) += ath79/
 obj-$(CONFIG_PINCTRL_INTEL) += intel/
 obj-$(CONFIG_ARCH_MTMIPS) += mtmips/
+obj-$(CONFIG_ARCH_NPCM) += nuvoton/
 obj-$(CONFIG_ARCH_RMOBILE) += renesas/
 obj-$(CONFIG_PINCTRL_SANDBOX)  += pinctrl-sandbox.o
 obj-$(CONFIG_PINCTRL_SUNXI)+= sunxi/
diff --git a/drivers/pinctrl/nuvoton/Kconfig b/drivers/pinctrl/nuvoton/Kconfig
new file mode 100644
index 00..519539d6ae
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/Kconfig
@@ -0,0 +1,12 @@
+config PINCTRL_NPCM8XX
+   bool "Pinctrl driver for Nuvoton NPCM8XX"
+   depends on DM && PINCTRL_GENERIC && ARCH_NPCM8XX
+   help
+ Support pin muxing and pin configuration on
+ Nuvoton NPCM8XX SoC.
+
+ The NPCM8XX contains 256 GPIO pins. Most of them are
+ multiplexed with other system functions. These pins can
+ be configured as either GPIO pin or alternate function.
+ It also supports basic configurations such as pull up/down,
+ drive-strength, and slew rate control for some of the pins.
diff --git a/drivers/pinctrl/nuvoton/Makefile b/drivers/pinctrl/nuvoton/Makefile
new file mode 100644
index 00..a6dfdf3672
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_PINCTRL_NPCM8XX)  += pinctrl-npcm8xx.o
diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c 
b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
new file mode 100644
index 00..cc49310506
--- /dev/null
+++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c
@@ -0,0 +1,1225 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Nuvoton Technology Corp.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* GCR register offsets */
+#define WD0RCR 0x38
+#define WD1RCR 0x3c
+#define WD2RCR 0x40
+#define SWRSTC10x44
+#define SWRSTC20x48
+#define SWRSTC30x4c
+#define SWRSTC40x50
+#define CORSTC 0x5c
+#define FLOCKR10x74
+#define INTCR4 0xc0
+#define I2CSEGSEL  0xe0
+#define MFSEL1 0x260
+#define MFSEL2 0x264
+#define MFSEL3 0x268
+#define MFSEL4 0x26c
+#define MFSEL5 0x270
+#define MFSEL6 0x274
+#define MFSEL7 0x278
+
+/* GPIO register offsets */
+#define GPIO_POL   0x08 /* Polarity */
+#define GPIO_DOUT  0x0c /* Data OUT */
+#define GPIO_OTYP  0x14 /* Output Type */
+#define GPIO_PU0x1c /* Pull-up */
+#define GPIO_PD0x20 /* Pull-down */
+#define GPIO_DBNC  0x24 /* Debounce */
+#define GPIO_EVEN  0x40 /* Event Enable */
+#define GPIO_EVST  0x4c /* Event Status */
+#define GPIO_IEM   0x58 /* Input Enable */
+#define GPIO_OSRC  0x5c /* Output Slew-Rate Control */
+#define GPIO_ODSC  0x60 /* Output Drive Strength Control */
+#define GPIO_OES   0x70 /* Output Enable Set */
+#define GPIO_OEC   0x74 /* Output Enable Clear */
+
+#define NPCM8XX_GPIO_PER_BANK  32
+#define GPIOX_OFFSET   16
+
+/* The lists contain alternate GPIO pins of the function */
+/* Serial Interfaces */
+static const uint hsi1a_pins[] = { 43, 63 };
+static const uint hsi1b_pins[] =