The Primary-to-Sideband bus (P2SB) is used to access various peripherals
through memory-mapped I/O in a large chunk of PCI space. The space is
segmented into different channels and peripherals are accessed by
device-specific means within those channels. Devices should be added in
the device tree as subnodes of the p2sb.
This adds a uclass and enables it for sandbox.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
Changes in v6: None
Changes in v5:
- Add a way to obtain the port ID for a device
- Don't enable p2sb on sandbox in this patch
Changes in v4:
- Adjust condition for binding children
Changes in v3: None
Changes in v2: None
drivers/misc/Kconfig | 33 ++
drivers/misc/Makefile | 1 +
drivers/misc/p2sb-uclass.c | 216 +
include/dm/uclass-id.h | 1 +
include/p2sb.h | 135 +++
5 files changed, 386 insertions(+)
create mode 100644 drivers/misc/p2sb-uclass.c
create mode 100644 include/p2sb.h
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 82bb093c56..71643af9c2 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -226,6 +226,39 @@ config NUVOTON_NCT6102D
disable the legacy UART, the watchdog or other devices
in the Nuvoton Super IO chips on X86 platforms.
+config P2SB
+ bool "Intel Primary-to-Sideband Bus"
+ depends on X86 || SANDBOX
+ help
+ This enables support for the Intel Primary-to-Sideband bus,
+ abbreviated to P2SB. The P2SB is used to access various peripherals
+ such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
+ space. The space is segmented into different channels and peripherals
+ are accessed by device-specific means within those channels. Devices
+ should be added in the device tree as subnodes of the P2SB. A
+ Peripheral Channel Register? (PCR) API is provided to access those
+ devices - see pcr_readl(), etc.
+
+config SPL_P2SB
+ bool "Intel Primary-to-Sideband Bus in SPL"
+ depends on SPL && (X86 || SANDBOX)
+ help
+ The Primary-to-Sideband bus is used to access various peripherals
+ through memory-mapped I/O in a large chunk of PCI space. The space is
+ segmented into different channels and peripherals are accessed by
+ device-specific means within those channels. Devices should be added
+ in the device tree as subnodes of the p2sb.
+
+config TPL_P2SB
+ bool "Intel Primary-to-Sideband Bus in TPL"
+ depends on TPL && (X86 || SANDBOX)
+ help
+ The Primary-to-Sideband bus is used to access various peripherals
+ through memory-mapped I/O in a large chunk of PCI space. The space is
+ segmented into different channels and peripherals are accessed by
+ device-specific means within those channels. Devices should be added
+ in the device tree as subnodes of the p2sb.
+
config PWRSEQ
bool "Enable power-sequencing drivers"
depends on DM
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 55976d6be5..78b598b367 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -49,6 +49,7 @@ obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o
obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o
obj-$(CONFIG_NS87308) += ns87308.o
obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o
+obj-$(CONFIG_P2SB) += p2sb-uclass.o
obj-$(CONFIG_PCA9551_LED) += pca9551_led.o
obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o
obj-$(CONFIG_QFW) += qfw.o
diff --git a/drivers/misc/p2sb-uclass.c b/drivers/misc/p2sb-uclass.c
new file mode 100644
index 00..a198700b5f
--- /dev/null
+++ b/drivers/misc/p2sb-uclass.c
@@ -0,0 +1,216 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Uclass for Primary-to-sideband bus, used to access various peripherals
+ *
+ * Copyright 2019 Google LLC
+ * Written by Simon Glass
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define PCR_COMMON_IOSF_1_01
+
+static void *_pcr_reg_address(struct udevice *dev, uint offset)
+{
+ struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev);
+ struct udevice *p2sb = dev_get_parent(dev);
+ struct p2sb_uc_priv *upriv = dev_get_uclass_priv(p2sb);
+ uintptr_t reg_addr;
+
+ /* Create an address based off of port id and offset */
+ reg_addr = upriv->mmio_base;
+ reg_addr += pplat->pid << PCR_PORTID_SHIFT;
+ reg_addr += offset;
+
+ return map_sysmem(reg_addr, 4);
+}
+
+/*
+ * The mapping of addresses via the SBREG_BAR assumes the IOSF-SB
+ * agents are using 32-bit aligned accesses for their configuration
+ * registers. For IOSF versions greater than 1_0, IOSF-SB
+ * agents can use any access (8/16/32 bit aligned) for their
+ * configuration registers
+ */
+static inline void check_pcr_offset_align(uint offset, uint size)
+{
+ const size_t align = PCR_COMMON_IOSF_1_0 ?
