This is taken directly from Linux kernel 6.3
(commit 457391b0380335d5e9a5babdec90ac53928b23b4)

Signed-off-by: Ralph Siemsen <ralph.siem...@linaro.org>
Reviewed-by: Marek Vasut <marek.vasut+rene...@mailbox.org>
---

(no changes since v6)

Changes in v6:
- updated comment to reflact linux 6.3, and add commit hash.
  (the files themselves have not changed)

Changes in v5:
- r9a06g032.dtsi now identical to linux 6.3-rc7 version

Changes in v3:
- add syscon phandle to ddrctl
- simplify UART compatible strings

 arch/arm/dts/r9a06g032.dtsi                   | 477 ++++++++++++++++++
 include/dt-bindings/clock/r9a06g032-sysctrl.h | 149 ++++++
 2 files changed, 626 insertions(+)
 create mode 100644 arch/arm/dts/r9a06g032.dtsi
 create mode 100644 include/dt-bindings/clock/r9a06g032-sysctrl.h

diff --git a/arch/arm/dts/r9a06g032.dtsi b/arch/arm/dts/r9a06g032.dtsi
new file mode 100644
index 0000000000..0fa565a1c3
--- /dev/null
+++ b/arch/arm/dts/r9a06g032.dtsi
@@ -0,0 +1,477 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032)
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r9a06g032-sysctrl.h>
+
+/ {
+       compatible = "renesas,r9a06g032";
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a7";
+                       reg = <0>;
+                       clocks = <&sysctrl R9A06G032_CLK_A7MP>;
+               };
+
+               cpu@1 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a7";
+                       reg = <1>;
+                       clocks = <&sysctrl R9A06G032_CLK_A7MP>;
+                       enable-method = "renesas,r9a06g032-smp";
+                       cpu-release-addr = <0 0x4000c204>;
+               };
+       };
+
+       ext_jtag_clk: extjtagclk {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+               clock-frequency = <0>;
+       };
+
+       ext_mclk: extmclk {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+               clock-frequency = <40000000>;
+       };
+
+       ext_rgmii_ref: extrgmiiref {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+               clock-frequency = <0>;
+       };
+
+       ext_rtc_clk: extrtcclk {
+               #clock-cells = <0>;
+               compatible = "fixed-clock";
+               clock-frequency = <0>;
+       };
+
+       soc {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               interrupt-parent = <&gic>;
+               ranges;
+
+               rtc0: rtc@40006000 {
+                       compatible = "renesas,r9a06g032-rtc", 
"renesas,rzn1-rtc";
+                       reg = <0x40006000 0x1000>;
+                       interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>,
+                                    <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "alarm", "timer", "pps";
+                       clocks = <&sysctrl R9A06G032_HCLK_RTC>;
+                       clock-names = "hclk";
+                       power-domains = <&sysctrl>;
+                       status = "disabled";
+               };
+
+               wdt0: watchdog@40008000 {
+                       compatible = "renesas,r9a06g032-wdt", 
"renesas,rzn1-wdt";
+                       reg = <0x40008000 0x1000>;
+                       interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
+                       clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
+                       status = "disabled";
+               };
+
+               wdt1: watchdog@40009000 {
+                       compatible = "renesas,r9a06g032-wdt", 
"renesas,rzn1-wdt";
+                       reg = <0x40009000 0x1000>;
+                       interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>;
+                       clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>;
+                       status = "disabled";
+               };
+
+               sysctrl: system-controller@4000c000 {
+                       compatible = "renesas,r9a06g032-sysctrl";
+                       reg = <0x4000c000 0x1000>;
+                       status = "okay";
+                       #clock-cells = <1>;
+                       #power-domain-cells = <0>;
+
+                       clocks = <&ext_mclk>, <&ext_rtc_clk>,
+                                       <&ext_jtag_clk>, <&ext_rgmii_ref>;
+                       clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       dmamux: dma-router@a0 {
+                               compatible = "renesas,rzn1-dmamux";
+                               reg = <0xa0 4>;
+                               #dma-cells = <6>;
+                               dma-requests = <32>;
+                               dma-masters = <&dma0 &dma1>;
+                       };
+               };
+
+               udc: usb@4001e000 {
+                       compatible = "renesas,r9a06g032-usbf", 
"renesas,rzn1-usbf";
+                       reg = <0x4001e000 0x2000>;
+                       interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&sysctrl R9A06G032_HCLK_USBF>,
+                                <&sysctrl R9A06G032_HCLK_USBPM>;
+                       clock-names = "hclkf", "hclkpm";
+                       power-domains = <&sysctrl>;
+                       status = "disabled";
+               };
+
+               pci_usb: pci@40030000 {
+                       compatible = "renesas,pci-r9a06g032", 
"renesas,pci-rzn1";
+                       device_type = "pci";
+                       clocks = <&sysctrl R9A06G032_HCLK_USBH>,
+                                <&sysctrl R9A06G032_HCLK_USBPM>,
+                                <&sysctrl R9A06G032_CLK_PCI_USB>;
+                       clock-names = "hclkh", "hclkpm", "pciclk";
+                       power-domains = <&sysctrl>;
+                       reg = <0x40030000 0xc00>,
+                             <0x40020000 0x1100>;
+                       interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+                       status = "disabled";
+
+                       bus-range = <0 0>;
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+                       #interrupt-cells = <1>;
+                       ranges = <0x02000000 0 0x40020000 0x40020000 0 
0x00010000>;
+                       /* Should map all possible DDR as inbound ranges, but
+                        * the IP only supports a 256MB, 512MB, or 1GB window.
+                        * flags, PCI addr (64-bit), CPU addr, PCI size (64-bit)
+                        */
+                       dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 
0x40000000>;
+                       interrupt-map-mask = <0xf800 0 0 0x7>;
+                       interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 
IRQ_TYPE_LEVEL_HIGH
+                                        0x0800 0 0 1 &gic GIC_SPI 79 
IRQ_TYPE_LEVEL_HIGH
+                                        0x1000 0 0 2 &gic GIC_SPI 79 
IRQ_TYPE_LEVEL_HIGH>;
+
+                       usb@1,0 {
+                               reg = <0x800 0 0 0 0>;
+                               phys = <&usbphy>;
+                               phy-names = "usb";
+                       };
+
+                       usb@2,0 {
+                               reg = <0x1000 0 0 0 0>;
+                               phys = <&usbphy>;
+                               phy-names = "usb";
+                       };
+               };
+
+               uart0: serial@40060000 {
+                       compatible = "renesas,r9a06g032-uart", 
"renesas,rzn1-uart", "snps,dw-apb-uart";
+                       reg = <0x40060000 0x400>;
+                       interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl 
R9A06G032_HCLK_UART0>;
+                       clock-names = "baudclk", "apb_pclk";
+                       status = "disabled";
+               };
+
+               uart1: serial@40061000 {
+                       compatible = "renesas,r9a06g032-uart", 
"renesas,rzn1-uart", "snps,dw-apb-uart";
+                       reg = <0x40061000 0x400>;
+                       interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       clocks = <&sysctrl R9A06G032_CLK_UART1>, <&sysctrl 
R9A06G032_HCLK_UART1>;
+                       clock-names = "baudclk", "apb_pclk";
+                       status = "disabled";
+               };
+
+               uart2: serial@40062000 {
+                       compatible = "renesas,r9a06g032-uart", 
"renesas,rzn1-uart", "snps,dw-apb-uart";
+                       reg = <0x40062000 0x400>;
+                       interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       clocks = <&sysctrl R9A06G032_CLK_UART2>, <&sysctrl 
R9A06G032_HCLK_UART2>;
+                       clock-names = "baudclk", "apb_pclk";
+                       status = "disabled";
+               };
+
+               uart3: serial@50000000 {
+                       compatible = "renesas,r9a06g032-uart", 
"renesas,rzn1-uart";
+                       reg = <0x50000000 0x400>;
+                       interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl 
R9A06G032_HCLK_UART3>;
+                       clock-names = "baudclk", "apb_pclk";
+                       dmas = <&dmamux 0 0 0 0 0 1>, <&dmamux 1 0 0 0 1 1>;
+                       dma-names = "rx", "tx";
+                       status = "disabled";
+               };
+
+               uart4: serial@50001000 {
+                       compatible = "renesas,r9a06g032-uart", 
"renesas,rzn1-uart";
+                       reg = <0x50001000 0x400>;
+                       interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl 
R9A06G032_HCLK_UART4>;
+                       clock-names = "baudclk", "apb_pclk";
+                       dmas = <&dmamux 2 0 0 0 2 1>, <&dmamux 3 0 0 0 3 1>;
+                       dma-names = "rx", "tx";
+                       status = "disabled";
+               };
+
+               uart5: serial@50002000 {
+                       compatible = "renesas,r9a06g032-uart", 
"renesas,rzn1-uart";
+                       reg = <0x50002000 0x400>;
+                       interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl 
R9A06G032_HCLK_UART5>;
+                       clock-names = "baudclk", "apb_pclk";
+                       dmas = <&dmamux 4 0 0 0 4 1>, <&dmamux 5 0 0 0 5 1>;
+                       dma-names = "rx", "tx";
+                       status = "disabled";
+               };
+
+               uart6: serial@50003000 {
+                       compatible = "renesas,r9a06g032-uart", 
"renesas,rzn1-uart";
+                       reg = <0x50003000 0x400>;
+                       interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl 
R9A06G032_HCLK_UART6>;
+                       clock-names = "baudclk", "apb_pclk";
+                       dmas = <&dmamux 6 0 0 0 6 1>, <&dmamux 7 0 0 0 7 1>;
+                       dma-names = "rx", "tx";
+                       status = "disabled";
+               };
+
+               uart7: serial@50004000 {
+                       compatible = "renesas,r9a06g032-uart", 
"renesas,rzn1-uart";
+                       reg = <0x50004000 0x400>;
+                       interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+                       reg-shift = <2>;
+                       reg-io-width = <4>;
+                       clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl 
R9A06G032_HCLK_UART7>;
+                       clock-names = "baudclk", "apb_pclk";
+                       dmas = <&dmamux 4 0 0 0 20 1>, <&dmamux 5 0 0 0 21 1>;
+                       dma-names = "rx", "tx";
+                       status = "disabled";
+               };
+
+               pinctrl: pinctrl@40067000 {
+                       compatible = "renesas,r9a06g032-pinctrl", 
"renesas,rzn1-pinctrl";
+                       reg = <0x40067000 0x1000>, <0x51000000 0x480>;
+                       clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>;
+                       clock-names = "bus";
+                       status = "okay";
+               };
+
+               nand_controller: nand-controller@40102000 {
+                       compatible = "renesas,r9a06g032-nandc", 
"renesas,rzn1-nandc";
+                       reg = <0x40102000 0x2000>;
+                       interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl 
R9A06G032_CLK_NAND>;
+                       clock-names = "hclk", "eclk";
+                       power-domains = <&sysctrl>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       status = "disabled";
+               };
+
+               dma0: dma-controller@40104000 {
+                       compatible = "renesas,r9a06g032-dma", 
"renesas,rzn1-dma";
+                       reg = <0x40104000 0x1000>;
+                       interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-names = "hclk";
+                       clocks = <&sysctrl R9A06G032_HCLK_DMA0>;
+                       dma-channels = <8>;
+                       dma-requests = <16>;
+                       dma-masters = <1>;
+                       #dma-cells = <3>;
+                       block_size = <0xfff>;
+                       data-width = <8>;
+               };
+
+               dma1: dma-controller@40105000 {
+                       compatible = "renesas,r9a06g032-dma", 
"renesas,rzn1-dma";
+                       reg = <0x40105000 0x1000>;
+                       interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-names = "hclk";
+                       clocks = <&sysctrl R9A06G032_HCLK_DMA1>;
+                       dma-channels = <8>;
+                       dma-requests = <16>;
+                       dma-masters = <1>;
+                       #dma-cells = <3>;
+                       block_size = <0xfff>;
+                       data-width = <8>;
+               };
+
+               gmac2: ethernet@44002000 {
+                       compatible = "renesas,r9a06g032-gmac", 
"renesas,rzn1-gmac", "snps,dwmac";
+                       reg = <0x44002000 0x2000>;
+                       interrupt-parent = <&gic>;
+                       interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
+                       clocks = <&sysctrl R9A06G032_HCLK_GMAC1>;
+                       clock-names = "stmmaceth";
+                       power-domains = <&sysctrl>;
+                       snps,multicast-filter-bins = <256>;
+                       snps,perfect-filter-entries = <128>;
+                       tx-fifo-depth = <2048>;
+                       rx-fifo-depth = <4096>;
+                       status = "disabled";
+               };
+
+               eth_miic: eth-miic@44030000 {
+                       compatible = "renesas,r9a06g032-miic", 
"renesas,rzn1-miic";
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <0x44030000 0x10000>;
+                       clocks = <&sysctrl R9A06G032_CLK_MII_REF>,
+                                <&sysctrl R9A06G032_CLK_RGMII_REF>,
+                                <&sysctrl R9A06G032_CLK_RMII_REF>,
+                                <&sysctrl R9A06G032_HCLK_SWITCH_RG>;
+                       clock-names = "mii_ref", "rgmii_ref", "rmii_ref", 
"hclk";
+                       power-domains = <&sysctrl>;
+                       status = "disabled";
+
+                       mii_conv1: mii-conv@1 {
+                               reg = <1>;
+                               status = "disabled";
+                       };
+
+                       mii_conv2: mii-conv@2 {
+                               reg = <2>;
+                               status = "disabled";
+                       };
+
+                       mii_conv3: mii-conv@3 {
+                               reg = <3>;
+                               status = "disabled";
+                       };
+
+                       mii_conv4: mii-conv@4 {
+                               reg = <4>;
+                               status = "disabled";
+                       };
+
+                       mii_conv5: mii-conv@5 {
+                               reg = <5>;
+                               status = "disabled";
+                       };
+               };
+
+               switch: switch@44050000 {
+                       compatible = "renesas,r9a06g032-a5psw", 
"renesas,rzn1-a5psw";
+                       reg = <0x44050000 0x10000>;
+                       clocks = <&sysctrl R9A06G032_HCLK_SWITCH>,
+                                <&sysctrl R9A06G032_CLK_SWITCH>;
+                       clock-names = "hclk", "clk";
+                       power-domains = <&sysctrl>;
+                       status = "disabled";
+
+                       ethernet-ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               switch_port0: port@0 {
+                                       reg = <0>;
+                                       pcs-handle = <&mii_conv5>;
+                                       status = "disabled";
+                               };
+
+                               switch_port1: port@1 {
+                                       reg = <1>;
+                                       pcs-handle = <&mii_conv4>;
+                                       status = "disabled";
+                               };
+
+                               switch_port2: port@2 {
+                                       reg = <2>;
+                                       pcs-handle = <&mii_conv3>;
+                                       status = "disabled";
+                               };
+
+                               switch_port3: port@3 {
+                                       reg = <3>;
+                                       pcs-handle = <&mii_conv2>;
+                                       status = "disabled";
+                               };
+
+                               switch_port4: port@4 {
+                                       reg = <4>;
+                                       ethernet = <&gmac2>;
+                                       label = "cpu";
+                                       phy-mode = "internal";
+                                       status = "disabled";
+                                       fixed-link {
+                                               speed = <1000>;
+                                               full-duplex;
+                                       };
+                               };
+                       };
+               };
+
+               gic: interrupt-controller@44101000 {
+                       compatible = "arm,gic-400", "arm,cortex-a7-gic";
+                       interrupt-controller;
+                       #interrupt-cells = <3>;
+                       reg = <0x44101000 0x1000>, /* Distributer */
+                             <0x44102000 0x2000>, /* CPU interface */
+                             <0x44104000 0x2000>, /* Virt interface control */
+                             <0x44106000 0x2000>; /* Virt CPU interface */
+                       interrupts =
+                               <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | 
IRQ_TYPE_LEVEL_HIGH)>;
+               };
+
+               can0: can@52104000 {
+                       compatible = 
"renesas,r9a06g032-sja1000","renesas,rzn1-sja1000";
+                       reg = <0x52104000 0x800>;
+                       reg-io-width = <4>;
+                       interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&sysctrl R9A06G032_HCLK_CAN0>;
+                       power-domains = <&sysctrl>;
+                       status = "disabled";
+               };
+
+               can1: can@52105000 {
+                       compatible = "renesas,r9a06g032-sja1000", 
"renesas,rzn1-sja1000";
+                       reg = <0x52105000 0x800>;
+                       reg-io-width = <4>;
+                       interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&sysctrl R9A06G032_HCLK_CAN1>;
+                       power-domains = <&sysctrl>;
+                       status = "disabled";
+               };
+       };
+
+       timer {
+               compatible = "arm,armv7-timer";
+               interrupt-parent = <&gic>;
+               arm,cpu-registers-not-fw-configured;
+               always-on;
+               interrupts =
+                       <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 
IRQ_TYPE_LEVEL_LOW)>,
+                       <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 
IRQ_TYPE_LEVEL_LOW)>,
+                       <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 
IRQ_TYPE_LEVEL_LOW)>,
+                       <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 
IRQ_TYPE_LEVEL_LOW)>;
+       };
+
+       usbphy: usb-phy {
+               #phy-cells = <0>;
+               compatible = "usb-nop-xceiv";
+               status = "disabled";
+       };
+};
diff --git a/include/dt-bindings/clock/r9a06g032-sysctrl.h 
b/include/dt-bindings/clock/r9a06g032-sysctrl.h
new file mode 100644
index 0000000000..d9d7b8b4f4
--- /dev/null
+++ b/include/dt-bindings/clock/r9a06g032-sysctrl.h
@@ -0,0 +1,149 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * R9A06G032 sysctrl IDs
+ *
+ * Copyright (C) 2018 Renesas Electronics Europe Limited
+ *
+ * Michel Pollet <michel.pol...@bp.renesas.com>, <buser...@gmail.com>
+ */
+
+#ifndef __DT_BINDINGS_R9A06G032_SYSCTRL_H__
+#define __DT_BINDINGS_R9A06G032_SYSCTRL_H__
+
+#define R9A06G032_CLK_PLL_USB          1
+#define R9A06G032_CLK_48               1       /* AKA CLK_PLL_USB */
+#define R9A06G032_MSEBIS_CLK           3       /* AKA CLKOUT_D16 */
+#define R9A06G032_MSEBIM_CLK           3       /* AKA CLKOUT_D16 */
+#define R9A06G032_CLK_DDRPHY_PLLCLK    5       /* AKA CLKOUT_D1OR2 */
+#define R9A06G032_CLK50                        6       /* AKA CLKOUT_D20 */
+#define R9A06G032_CLK25                        7       /* AKA CLKOUT_D40 */
+#define R9A06G032_CLK125               9       /* AKA CLKOUT_D8 */
+#define R9A06G032_CLK_P5_PG1           17      /* AKA DIV_P5_PG */
+#define R9A06G032_CLK_REF_SYNC         21      /* AKA DIV_REF_SYNC */
+#define R9A06G032_CLK_25_PG4           26
+#define R9A06G032_CLK_25_PG5           27
+#define R9A06G032_CLK_25_PG6           28
+#define R9A06G032_CLK_25_PG7           29
+#define R9A06G032_CLK_25_PG8           30
+#define R9A06G032_CLK_ADC              31
+#define R9A06G032_CLK_ECAT100          32
+#define R9A06G032_CLK_HSR100           33
+#define R9A06G032_CLK_I2C0             34
+#define R9A06G032_CLK_I2C1             35
+#define R9A06G032_CLK_MII_REF          36
+#define R9A06G032_CLK_NAND             37
+#define R9A06G032_CLK_NOUSBP2_PG6      38
+#define R9A06G032_CLK_P1_PG2           39
+#define R9A06G032_CLK_P1_PG3           40
+#define R9A06G032_CLK_P1_PG4           41
+#define R9A06G032_CLK_P4_PG3           42
+#define R9A06G032_CLK_P4_PG4           43
+#define R9A06G032_CLK_P6_PG1           44
+#define R9A06G032_CLK_P6_PG2           45
+#define R9A06G032_CLK_P6_PG3           46
+#define R9A06G032_CLK_P6_PG4           47
+#define R9A06G032_CLK_PCI_USB          48
+#define R9A06G032_CLK_QSPI0            49
+#define R9A06G032_CLK_QSPI1            50
+#define R9A06G032_CLK_RGMII_REF                51
+#define R9A06G032_CLK_RMII_REF         52
+#define R9A06G032_CLK_SDIO0            53
+#define R9A06G032_CLK_SDIO1            54
+#define R9A06G032_CLK_SERCOS100                55
+#define R9A06G032_CLK_SLCD             56
+#define R9A06G032_CLK_SPI0             57
+#define R9A06G032_CLK_SPI1             58
+#define R9A06G032_CLK_SPI2             59
+#define R9A06G032_CLK_SPI3             60
+#define R9A06G032_CLK_SPI4             61
+#define R9A06G032_CLK_SPI5             62
+#define R9A06G032_CLK_SWITCH           63
+#define R9A06G032_HCLK_ECAT125         65
+#define R9A06G032_HCLK_PINCONFIG       66
+#define R9A06G032_HCLK_SERCOS          67
+#define R9A06G032_HCLK_SGPIO2          68
+#define R9A06G032_HCLK_SGPIO3          69
+#define R9A06G032_HCLK_SGPIO4          70
+#define R9A06G032_HCLK_TIMER0          71
+#define R9A06G032_HCLK_TIMER1          72
+#define R9A06G032_HCLK_USBF            73
+#define R9A06G032_HCLK_USBH            74
+#define R9A06G032_HCLK_USBPM           75
+#define R9A06G032_CLK_48_PG_F          76
+#define R9A06G032_CLK_48_PG4           77
+#define R9A06G032_CLK_DDRPHY_PCLK      81      /* AKA CLK_REF_SYNC_D4 */
+#define R9A06G032_CLK_FW               81      /* AKA CLK_REF_SYNC_D4 */
+#define R9A06G032_CLK_CRYPTO           81      /* AKA CLK_REF_SYNC_D4 */
+#define R9A06G032_CLK_WATCHDOG         82      /* AKA CLK_REF_SYNC_D8 */
+#define R9A06G032_CLK_A7MP             84      /* AKA DIV_CA7 */
+#define R9A06G032_HCLK_CAN0            85
+#define R9A06G032_HCLK_CAN1            86
+#define R9A06G032_HCLK_DELTASIGMA      87
+#define R9A06G032_HCLK_PWMPTO          88
+#define R9A06G032_HCLK_RSV             89
+#define R9A06G032_HCLK_SGPIO0          90
+#define R9A06G032_HCLK_SGPIO1          91
+#define R9A06G032_RTOS_MDC             92
+#define R9A06G032_CLK_CM3              93
+#define R9A06G032_CLK_DDRC             94
+#define R9A06G032_CLK_ECAT25           95
+#define R9A06G032_CLK_HSR50            96
+#define R9A06G032_CLK_HW_RTOS          97
+#define R9A06G032_CLK_SERCOS50         98
+#define R9A06G032_HCLK_ADC             99
+#define R9A06G032_HCLK_CM3             100
+#define R9A06G032_HCLK_CRYPTO_EIP150   101
+#define R9A06G032_HCLK_CRYPTO_EIP93    102
+#define R9A06G032_HCLK_DDRC            103
+#define R9A06G032_HCLK_DMA0            104
+#define R9A06G032_HCLK_DMA1            105
+#define R9A06G032_HCLK_GMAC0           106
+#define R9A06G032_HCLK_GMAC1           107
+#define R9A06G032_HCLK_GPIO0           108
+#define R9A06G032_HCLK_GPIO1           109
+#define R9A06G032_HCLK_GPIO2           110
+#define R9A06G032_HCLK_HSR             111
+#define R9A06G032_HCLK_I2C0            112
+#define R9A06G032_HCLK_I2C1            113
+#define R9A06G032_HCLK_LCD             114
+#define R9A06G032_HCLK_MSEBI_M         115
+#define R9A06G032_HCLK_MSEBI_S         116
+#define R9A06G032_HCLK_NAND            117
+#define R9A06G032_HCLK_PG_I            118
+#define R9A06G032_HCLK_PG19            119
+#define R9A06G032_HCLK_PG20            120
+#define R9A06G032_HCLK_PG3             121
+#define R9A06G032_HCLK_PG4             122
+#define R9A06G032_HCLK_QSPI0           123
+#define R9A06G032_HCLK_QSPI1           124
+#define R9A06G032_HCLK_ROM             125
+#define R9A06G032_HCLK_RTC             126
+#define R9A06G032_HCLK_SDIO0           127
+#define R9A06G032_HCLK_SDIO1           128
+#define R9A06G032_HCLK_SEMAP           129
+#define R9A06G032_HCLK_SPI0            130
+#define R9A06G032_HCLK_SPI1            131
+#define R9A06G032_HCLK_SPI2            132
+#define R9A06G032_HCLK_SPI3            133
+#define R9A06G032_HCLK_SPI4            134
+#define R9A06G032_HCLK_SPI5            135
+#define R9A06G032_HCLK_SWITCH          136
+#define R9A06G032_HCLK_SWITCH_RG       137
+#define R9A06G032_HCLK_UART0           138
+#define R9A06G032_HCLK_UART1           139
+#define R9A06G032_HCLK_UART2           140
+#define R9A06G032_HCLK_UART3           141
+#define R9A06G032_HCLK_UART4           142
+#define R9A06G032_HCLK_UART5           143
+#define R9A06G032_HCLK_UART6           144
+#define R9A06G032_HCLK_UART7           145
+#define R9A06G032_CLK_UART0            146
+#define R9A06G032_CLK_UART1            147
+#define R9A06G032_CLK_UART2            148
+#define R9A06G032_CLK_UART3            149
+#define R9A06G032_CLK_UART4            150
+#define R9A06G032_CLK_UART5            151
+#define R9A06G032_CLK_UART6            152
+#define R9A06G032_CLK_UART7            153
+
+#endif /* __DT_BINDINGS_R9A06G032_SYSCTRL_H__ */
-- 
2.25.1

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