Re: [PULL] u-boot-riscv/next
On Thu, Sep 12, 2024 at 02:39:24PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit 78d898eec080b02059c8dc09318b8761044fea85: > > Merge patch series "phycore-am62/4: Add more boot sources" (2024-09-10 > 14:56:12 -0600) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git next > > for you to fetch changes up to 2db018d2ca5ebd7acc717f0b1959ee67fcd2b0a1: > > configs: ibex-ast2700: Enable DRAM and timer driver (2024-09-11 20:35:04 > +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/22315 Applied to u-boot/next, thanks! -- Tom signature.asc Description: PGP signature
[PULL] u-boot-riscv/next
Hi Tom, The following changes since commit 78d898eec080b02059c8dc09318b8761044fea85: Merge patch series "phycore-am62/4: Add more boot sources" (2024-09-10 14:56:12 -0600) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git next for you to fetch changes up to 2db018d2ca5ebd7acc717f0b1959ee67fcd2b0a1: configs: ibex-ast2700: Enable DRAM and timer driver (2024-09-11 20:35:04 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/22315 - Aspeed: Add AST2700 board (Ibex RISC-V core) support - Add timer, dram controller, network support - Sophgo: Add clock controller support for Milk-V Duo Chia-Wei Wang (8): riscv: Make A ISA extension selectable riscv: Make stack size shift configurable riscv: u-boot-spl.lds: Remove _image_binary_end alignment riscv: Add AST2700 SoC initial platform support timer: Add AST2700 IBEX timer support board: ibex_ast2700: Add FMC header support ram: ast2700: Add DRAM controller initialization configs: ibex-ast2700: Enable DRAM and timer driver Jacky Chou (5): net: ftgmac100: Fixed the cache coherency issues of rx memory net: ftgmac100: Fixed NC-SI PHY device cannot get net: ftgmac100: Modify desc. size to cache line net: ftgmac100: Add Aspeed AST2700 support driver: net: Add Aspeed AST2700 MDIO support Kongyang Liu (4): dt-bindings: clk: import header for clock controller of sophgo CV1800B clk: sophgo: cv1800b: Add clock controller driver for cv1800b SoC configs: milkv_duo: Enable clock controller riscv: dts: sophgo: Replace device clocks with real clocks. arch/riscv/Kconfig | 12 +- arch/riscv/cpu/ast2700/Kconfig |6 + arch/riscv/cpu/ast2700/Makefile|1 + arch/riscv/cpu/ast2700/cpu.c | 23 + arch/riscv/cpu/u-boot-spl.lds |2 - arch/riscv/dts/Makefile|1 + arch/riscv/dts/ast2700-ibex.dts| 22 + arch/riscv/dts/ast2700-u-boot.dtsi | 40 + arch/riscv/dts/ast2700.dtsi| 76 + arch/riscv/dts/cv18xx.dtsi | 40 +- arch/riscv/include/asm/arch-ast2700/fmc_hdr.h | 52 + arch/riscv/include/asm/arch-ast2700/scu.h | 145 + arch/riscv/include/asm/arch-ast2700/sdram.h| 137 + arch/riscv/include/asm/arch-ast2700/sli.h | 82 + board/aspeed/ibex_ast2700/Kconfig | 21 + board/aspeed/ibex_ast2700/MAINTAINERS |7 + board/aspeed/ibex_ast2700/Makefile |3 + board/aspeed/ibex_ast2700/fmc_hdr.c| 64 + board/aspeed/ibex_ast2700/ibex_ast2700.c | 85 + board/aspeed/ibex_ast2700/sli.c| 72 + configs/ibex-ast2700_defconfig | 94 + configs/milkv_duo_defconfig|3 +- doc/board/aspeed/ibex-ast2700.rst | 26 + doc/board/aspeed/index.rst |9 + doc/board/index.rst|1 + drivers/clk/Kconfig|1 + drivers/clk/Makefile |1 + drivers/clk/sophgo/Kconfig | 14 + drivers/clk/sophgo/Makefile|6 + drivers/clk/sophgo/clk-common.h| 74 + drivers/clk/sophgo/clk-cv1800b.c | 754 +++ drivers/clk/sophgo/clk-cv1800b.h | 123 + drivers/clk/sophgo/clk-ip.c| 594 ++ drivers/clk/sophgo/clk-ip.h| 288 + drivers/clk/sophgo/clk-pll.c | 275 + drivers/clk/sophgo/clk-pll.h | 74 + drivers/net/aspeed_mdio.c |1 + drivers/net/ftgmac100.c| 89 +- drivers/net/ftgmac100.h| 17 +- drivers/ram/Makefile |2 +- drivers/ram/aspeed/Kconfig | 27 +- drivers/ram/aspeed/Makefile|1 + .../dwc_ddrphy_phyinit_ddr4-3200-nodimm-train2D.c | 2700 .../dwc_ddrphy_phyinit_ddr5-3200-nodimm-train2D.c | 6930 drivers/ram/aspeed/sdram_ast2700.c | 1036 +++ drivers/timer/Kconfig |6 + drivers/timer/Makefile |1 + drivers/timer/ast_ibex_timer.c | 45 + include/configs/ibex_ast2700.h | 12 + include/dt-bindings/clock/sophgo,cv1800.h | 176 + 50 files changed, 14220 insertions(+), 51 deletions(-) cr
Re: [GIT PULL] u-boot-riscv/next
On Thu, Dec 28, 2023 at 01:38:11PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit 4b151562bb8e54160adedbc6a1c0c749c00a2f84: > > bootmeth: pass size to efi_binary_run() (2023-12-22 10:36:50 -0500) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git next > > for you to fetch changes up to 9924d44dbcd47bd3664fa9f1f9f24044d83eaebf: > > andes: ae350: Enable MISC_INIT_R for ae350 platform (2023-12-27 17:29:11 > +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/19106 Applied to u-boot/next, thanks! -- Tom signature.asc Description: PGP signature
[GIT PULL] u-boot-riscv/next
Hi Tom, The following changes since commit 4b151562bb8e54160adedbc6a1c0c749c00a2f84: bootmeth: pass size to efi_binary_run() (2023-12-22 10:36:50 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git next for you to fetch changes up to 9924d44dbcd47bd3664fa9f1f9f24044d83eaebf: andes: ae350: Enable MISC_INIT_R for ae350 platform (2023-12-27 17:29:11 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/19106 - Andes: Enable Andes CPU memboost and ECC feature by default - Sifive: Add private L2 cache driver Leo Yu-Chi Liang (6): andes: csr.h: Clean up CSR definition andes: ae350: Implement cache switch via Kconfig andes: cpu: Enable memboost feature andes: cpu: Enable cache and TLB ECC support andes: ae350: Save cpu name to env andes: ae350: Enable MISC_INIT_R for ae350 platform Michal Simek (1): riscv: Extend board compatible string with "qemu,mbv" Zong Li (2): cache: add sifive private L2 cache driver riscv: cache: support cache enable in SPL stage arch/riscv/cpu/andesv5/cpu.c| 33 ++--- arch/riscv/dts/xilinx-mbv32.dts | 2 +- arch/riscv/include/asm/arch-andes/csr.h | 29 +- arch/riscv/include/asm/csr.h| 1 + arch/riscv/lib/sifive_cache.c | 21 board/AndesTech/ae350/ae350.c | 26 ++- configs/ae350_rv32_defconfig| 5 ++-- configs/ae350_rv32_spl_defconfig| 5 ++-- configs/ae350_rv32_spl_xip_defconfig| 5 ++-- configs/ae350_rv32_xip_defconfig| 5 ++-- configs/ae350_rv64_defconfig| 5 ++-- configs/ae350_rv64_spl_defconfig| 5 ++-- configs/ae350_rv64_spl_xip_defconfig| 5 ++-- configs/ae350_rv64_xip_defconfig| 5 ++-- drivers/cache/Kconfig | 7 ++ drivers/cache/Makefile | 1 + drivers/cache/cache-sifive-pl2.c| 44 + 17 files changed, 165 insertions(+), 39 deletions(-) create mode 100644 drivers/cache/cache-sifive-pl2.c Best regards, Leo
Re: [GIT PULL] u-boot-riscv/next
On Mon, Dec 18, 2023 at 07:44:15PM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit fdefb4e194c65777fa11479119adaa71651f41d4: > > Merge tag 'efi-next-20231217' of > https://source.denx.de/u-boot/custodians/u-boot-efi into next (2023-12-17 > 09:11:06 -0500) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git next > > for you to fetch changes up to 44a792c99498f5a9d3526019779d66585978c491: > > riscv: sifive: unmatched: migrate to text environment (2023-12-18 11:09:01 > +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18996 Applied to u-boot/next, thanks! -- Tom signature.asc Description: PGP signature
[GIT PULL] u-boot-riscv/next
Hi Tom, The following changes since commit fdefb4e194c65777fa11479119adaa71651f41d4: Merge tag 'efi-next-20231217' of https://source.denx.de/u-boot/custodians/u-boot-efi into next (2023-12-17 09:11:06 -0500) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git next for you to fetch changes up to 44a792c99498f5a9d3526019779d66585978c491: riscv: sifive: unmatched: migrate to text environment (2023-12-18 11:09:01 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/18996 - VisionFive2: Enable CONFIG_SYSRESET - StarFive: Modify starfive timer driver - AMD/Xilinx: Add MicroBlaze V support - Unmatched: Migrate to text environment Jaehoon Chung (2): riscv: dts: jh7110: Add a gpio-restart node configs: visionfive2: Enable CONFIG_SYSRESET config Kuan Lim Lee (1): timer: starfive: Add Starfive timer support Michal Simek (1): riscv: Add support for AMD/Xilinx MicroBlaze V Yong-Xuan Wang (1): riscv: sifive: unmatched: migrate to text environment arch/riscv/Kconfig | 4 + arch/riscv/dts/Makefile | 2 + arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi | 5 ++ arch/riscv/dts/xilinx-mbv32.dts | 106 +++ board/sifive/unmatched/unmatched.env | 19 board/xilinx/Kconfig | 3 +- board/xilinx/common/board.c | 5 ++ board/xilinx/mbv/Kconfig | 28 ++ board/xilinx/mbv/MAINTAINERS | 7 ++ board/xilinx/mbv/Makefile| 5 ++ board/xilinx/mbv/board.c | 11 +++ configs/sifive_unmatched_defconfig | 2 +- configs/starfive_visionfive2_defconfig | 1 + configs/xilinx_mbv32_defconfig | 30 +++ configs/xilinx_mbv32_smode_defconfig | 32 +++ drivers/timer/starfive-timer.c | 16 ++-- include/configs/sifive-unmatched.h | 37 include/configs/xilinx_mbv.h | 6 ++ 18 files changed, 273 insertions(+), 46 deletions(-) create mode 100644 arch/riscv/dts/xilinx-mbv32.dts create mode 100644 board/sifive/unmatched/unmatched.env create mode 100644 board/xilinx/mbv/Kconfig create mode 100644 board/xilinx/mbv/MAINTAINERS create mode 100644 board/xilinx/mbv/Makefile create mode 100644 board/xilinx/mbv/board.c create mode 100644 configs/xilinx_mbv32_defconfig create mode 100644 configs/xilinx_mbv32_smode_defconfig create mode 100644 include/configs/xilinx_mbv.h Best regards, Leo
Re: [PULL] u-boot-riscv/next
On Thu, Sep 21, 2023 at 09:28:46AM +0800, Leo Liang wrote: > Hi Tom, > > The following changes since commit c58ee1c9946a1550b1f6fee2b25da9ecc89baf71: > > Merge branch '2023-09-19-tidy-up-some-kconfig-options' into next > (2023-09-19 17:44:18 -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git next > > for you to fetch changes up to 90602e779d3ae3bd02faae0eb40b4fcefec419f7: > > riscv: dts: starfive: generate u-boot-spl.bin.normal.out (2023-09-20 > 21:05:16 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17779 Applied to u-boot/next, thanks! -- Tom signature.asc Description: PGP signature
[PULL] u-boot-riscv/next
Hi Tom, The following changes since commit c58ee1c9946a1550b1f6fee2b25da9ecc89baf71: Merge branch '2023-09-19-tidy-up-some-kconfig-options' into next (2023-09-19 17:44:18 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git next for you to fetch changes up to 90602e779d3ae3bd02faae0eb40b4fcefec419f7: riscv: dts: starfive: generate u-boot-spl.bin.normal.out (2023-09-20 21:05:16 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/17779 + Add NVMe & USB boot devices for VisionFive2 + Add StarFive SPL image support in mkimage tool Heinrich Schuchardt (4): riscv: set fdtfile on VisionFive 2 configs: NVMe/USB target boot devices on VisionFive 2 tools: mkimage: Add StarFive SPL image support riscv: dts: starfive: generate u-boot-spl.bin.normal.out Milan P. Stanić (1): starfive: visionfive2: add mmc0 and nvme boot targets arch/riscv/Kconfig | 1 + .../dts/jh7110-starfive-visionfive-2-u-boot.dtsi | 11 ++ board/starfive/visionfive2/starfive_visionfive2.c | 43 - boot/image.c | 1 + doc/board/starfive/visionfive2.rst | 14 +- include/configs/starfive-visionfive2.h | 3 + include/image.h| 1 + tools/Makefile | 1 + tools/sfspl.c | 174 + 9 files changed, 235 insertions(+), 14 deletions(-) create mode 100644 tools/sfspl.c Best regards, Leo
Re: [PULL] u-boot-riscv/next
On Mon, Sep 26, 2022 at 07:39:22AM +, Leo Liang wrote: > Hi Tom, > > The following changes since commit 435596d57f8beedf36b5dc858fe7ba9d6c03334b: > > Merge tag 'u-boot-imx-20220922' of > https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2022-09-22 10:29:29 > -0400) > > are available in the Git repository at: > > https://source.denx.de/u-boot/custodians/u-boot-riscv.git next > > for you to fetch changes up to 3c1ec13317292933fd01d9c60aae3ff1d5bc171e: > > riscv: ae350: Disable AVAILABLE_HARTS (2022-09-26 14:29:44 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/13595 > Applied to u-boot/next, thanks! -- Tom signature.asc Description: PGP signature
[PULL] u-boot-riscv/next
Hi Tom, The following changes since commit 435596d57f8beedf36b5dc858fe7ba9d6c03334b: Merge tag 'u-boot-imx-20220922' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx (2022-09-22 10:29:29 -0400) are available in the Git repository at: https://source.denx.de/u-boot/custodians/u-boot-riscv.git next for you to fetch changes up to 3c1ec13317292933fd01d9c60aae3ff1d5bc171e: riscv: ae350: Disable AVAILABLE_HARTS (2022-09-26 14:29:44 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/13595 Nikita Shubin (1): spl: introduce SPL_XIP to config Rick Chen (2): riscv: Introduce AVAILABLE_HARTS riscv: ae350: Disable AVAILABLE_HARTS arch/riscv/Kconfig | 14 ++ arch/riscv/cpu/cpu.c | 4 +++- arch/riscv/cpu/start.S | 17 ++--- arch/riscv/include/asm/global_data.h | 4 +++- arch/riscv/lib/asm-offsets.c | 4 +++- arch/riscv/lib/smp.c | 4 +++- configs/ae350_rv32_spl_defconfig | 1 + configs/ae350_rv32_spl_xip_defconfig | 2 +- configs/ae350_rv64_spl_defconfig | 1 + configs/ae350_rv64_spl_xip_defconfig | 2 +- 10 files changed, 40 insertions(+), 13 deletions(-) Best regards, Leo
Re: [PULL] u-boot-riscv/next
On Wed, Jun 16, 2021 at 04:28:21PM +0800, Leo Liang wrote: > On Wed, Jun 16, 2021 at 04:07:26PM +0800, Bin Meng wrote: > > Hi Leo, > > > > On Wed, Jun 16, 2021 at 3:44 PM Leo Liang wrote: > > > > > > Hi Tom, > > > > > > Please pull u-boot-riscv/next into -next. > > > > > > The following changes on the "next" branch since commit > > > c4737cd594b5c4c47aff789fc53f7dd36ed03c94: > > > > > > Merge tag 'xilinx-for-v2021.07-rc5' of > > > https://source.denx.de/u-boot/custodians/u-boot-microblaze (2021-06-11 > > > 08:29:34 -0400) > > > > > > are available in the Git repository at: > > > > > > g...@source.denx.de:u-boot/custodians/u-boot-riscv.git > > > > > > for you to fetch changes up to efbcd66af3c83b14efb72eb38f73cd4af8128208: > > > > > > test: Add K210 PLL tests to sandbox defconfigs (2021-06-16 10:04:23 > > > +0800) > > > > > > CI result shows no issue: > > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7856 > > > > > > > > > Bin Meng (6): > > > riscv: ae350: dts: Add SPDX license header > > > riscv: ae350: dts: Remove the unnecessary space in bootargs > > > riscv: ae350: dts: Remove the unnecessary #address-cells in plic > > > nodes > > > riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit > > > riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL config > > > riscv: ae350: doc: Remove CONFIG_SKIP_LOWLEVEL_INIT > > > > It seems this patch is missing? > > > > riscv: andes_plic: Fix riscv_get_ipi() mask > > http://patchwork.ozlabs.org/project/uboot/patch/20210615054557.376750-1-bmeng...@gmail.com/ > > > > Regards, > > Bin > > Hi Bin, > > Sorry, I must have omitted it by accident. > > Hi Tom, > > Could you drop this PR ? > I will send another one including the patch Bin mentioned. > Thanks! Will do. -- Tom signature.asc Description: PGP signature
Re: [PULL] u-boot-riscv/next
On Wed, Jun 16, 2021 at 04:07:26PM +0800, Bin Meng wrote: > Hi Leo, > > On Wed, Jun 16, 2021 at 3:44 PM Leo Liang wrote: > > > > Hi Tom, > > > > Please pull u-boot-riscv/next into -next. > > > > The following changes on the "next" branch since commit > > c4737cd594b5c4c47aff789fc53f7dd36ed03c94: > > > > Merge tag 'xilinx-for-v2021.07-rc5' of > > https://source.denx.de/u-boot/custodians/u-boot-microblaze (2021-06-11 > > 08:29:34 -0400) > > > > are available in the Git repository at: > > > > g...@source.denx.de:u-boot/custodians/u-boot-riscv.git > > > > for you to fetch changes up to efbcd66af3c83b14efb72eb38f73cd4af8128208: > > > > test: Add K210 PLL tests to sandbox defconfigs (2021-06-16 10:04:23 +0800) > > > > CI result shows no issue: > > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7856 > > > > > > Bin Meng (6): > > riscv: ae350: dts: Add SPDX license header > > riscv: ae350: dts: Remove the unnecessary space in bootargs > > riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes > > riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit > > riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL config > > riscv: ae350: doc: Remove CONFIG_SKIP_LOWLEVEL_INIT > > It seems this patch is missing? > > riscv: andes_plic: Fix riscv_get_ipi() mask > http://patchwork.ozlabs.org/project/uboot/patch/20210615054557.376750-1-bmeng...@gmail.com/ > > Regards, > Bin Hi Bin, Sorry, I must have omitted it by accident. Hi Tom, Could you drop this PR ? I will send another one including the patch Bin mentioned. Thanks! Best regards, Leo
Re: [PULL] u-boot-riscv/next
Hi Leo, On Wed, Jun 16, 2021 at 3:44 PM Leo Liang wrote: > > Hi Tom, > > Please pull u-boot-riscv/next into -next. > > The following changes on the "next" branch since commit > c4737cd594b5c4c47aff789fc53f7dd36ed03c94: > > Merge tag 'xilinx-for-v2021.07-rc5' of > https://source.denx.de/u-boot/custodians/u-boot-microblaze (2021-06-11 > 08:29:34 -0400) > > are available in the Git repository at: > > g...@source.denx.de:u-boot/custodians/u-boot-riscv.git > > for you to fetch changes up to efbcd66af3c83b14efb72eb38f73cd4af8128208: > > test: Add K210 PLL tests to sandbox defconfigs (2021-06-16 10:04:23 +0800) > > CI result shows no issue: > https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7856 > > > Bin Meng (6): > riscv: ae350: dts: Add SPDX license header > riscv: ae350: dts: Remove the unnecessary space in bootargs > riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes > riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit > riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL config > riscv: ae350: doc: Remove CONFIG_SKIP_LOWLEVEL_INIT It seems this patch is missing? riscv: andes_plic: Fix riscv_get_ipi() mask http://patchwork.ozlabs.org/project/uboot/patch/20210615054557.376750-1-bmeng...@gmail.com/ Regards, Bin
[PULL] u-boot-riscv/next
Hi Tom, Please pull u-boot-riscv/next into -next. The following changes on the "next" branch since commit c4737cd594b5c4c47aff789fc53f7dd36ed03c94: Merge tag 'xilinx-for-v2021.07-rc5' of https://source.denx.de/u-boot/custodians/u-boot-microblaze (2021-06-11 08:29:34 -0400) are available in the Git repository at: g...@source.denx.de:u-boot/custodians/u-boot-riscv.git for you to fetch changes up to efbcd66af3c83b14efb72eb38f73cd4af8128208: test: Add K210 PLL tests to sandbox defconfigs (2021-06-16 10:04:23 +0800) CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/7856 Bin Meng (6): riscv: ae350: dts: Add SPDX license header riscv: ae350: dts: Remove the unnecessary space in bootargs riscv: ae350: dts: Remove the unnecessary #address-cells in plic nodes riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit riscv: ae350: dts: Add missing "u-boot, dm-spl" for SPL config riscv: ae350: doc: Remove CONFIG_SKIP_LOWLEVEL_INIT Sean Anderson (11): clk: Allow force setting clock defaults before relocation clk: k210: Rewrite to remove CCF clk: k210: Move pll into the rest of the driver clk: k210: Implement soc_clk_dump clk: k210: Re-add support for setting rate clk: k210: Don't set PLL rates if we are already at the correct rate clk: k210: Remove bypass driver clk: k210: Move k210 clock out of its own subdirectory k210: dts: Set PLL1 to the same rate as PLL0 k210: Don't imply CCF test: Add K210 PLL tests to sandbox defconfigs MAINTAINERS |4 +- arch/riscv/dts/ae350-u-boot.dtsi| 52 ++ arch/riscv/dts/ae350_32.dts |9 +- arch/riscv/dts/ae350_64.dts |7 +- arch/riscv/dts/k210.dtsi|2 + board/sipeed/maix/Kconfig |2 - configs/sandbox64_defconfig |2 + configs/sandbox_defconfig |2 + configs/sandbox_flattree_defconfig |2 + configs/sipeed_maix_bitm_defconfig |2 +- doc/board/AndesTech/ax25-ae350.rst | 19 +- drivers/clk/Kconfig | 14 +- drivers/clk/Makefile|2 +- drivers/clk/clk-uclass.c| 27 +- drivers/clk/clk_kendryte.c | 1320 +++ drivers/clk/kendryte/Kconfig| 12 - drivers/clk/kendryte/Makefile |1 - drivers/clk/kendryte/bypass.c | 273 --- drivers/clk/kendryte/clk.c | 668 drivers/clk/kendryte/pll.c | 585 -- drivers/clk/rockchip/clk_rk3308.c |2 +- drivers/core/device.c |2 +- drivers/net/gmac_rockchip.c |2 +- include/clk.h | 30 +- include/dt-bindings/clock/k210-sysctl.h | 94 ++- include/kendryte/bypass.h | 31 - include/kendryte/clk.h | 35 - include/kendryte/pll.h | 34 - 28 files changed, 1502 insertions(+), 1733 deletions(-) create mode 100644 arch/riscv/dts/ae350-u-boot.dtsi create mode 100644 drivers/clk/clk_kendryte.c delete mode 100644 drivers/clk/kendryte/Kconfig delete mode 100644 drivers/clk/kendryte/Makefile delete mode 100644 drivers/clk/kendryte/bypass.c delete mode 100644 drivers/clk/kendryte/clk.c delete mode 100644 drivers/clk/kendryte/pll.c delete mode 100644 include/kendryte/bypass.h delete mode 100644 include/kendryte/clk.h Best regards, Leo
