This patch adds a gpmc_init function for OMAP4 and adds calls to
gpmc_init for existing OMAP4 boards: panda and sdp4430
Signed-off-by: Steve Sakoman st...@sakoman.com
---
arch/arm/cpu/armv7/omap4/Makefile |1 +
arch/arm/cpu/armv7/omap4/mem.c | 45 +
arch/arm/include/asm/arch-omap4/cpu.h | 48 +++
arch/arm/include/asm/arch-omap4/omap4.h |2 +-
arch/arm/include/asm/arch-omap4/sys_proto.h |1 +
board/ti/panda/panda.c |2 +
board/ti/sdp4430/sdp.c |2 +
7 files changed, 100 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/cpu/armv7/omap4/mem.c
diff --git a/arch/arm/cpu/armv7/omap4/Makefile
b/arch/arm/cpu/armv7/omap4/Makefile
index ecf64f9..d926fbb 100644
--- a/arch/arm/cpu/armv7/omap4/Makefile
+++ b/arch/arm/cpu/armv7/omap4/Makefile
@@ -28,6 +28,7 @@ LIB = $(obj)lib$(SOC).a
SOBJS += lowlevel_init.o
COBJS += board.o
+COBJS += mem.o
COBJS += sys_info.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/arch/arm/cpu/armv7/omap4/mem.c b/arch/arm/cpu/armv7/omap4/mem.c
new file mode 100644
index 000..208f3a8
--- /dev/null
+++ b/arch/arm/cpu/armv7/omap4/mem.c
@@ -0,0 +1,45 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, www.ti.com
+ *
+ * Steve Sakoman st...@sakoman.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include asm/arch/cpu.h
+#include asm/arch/sys_proto.h
+
+struct gpmc *gpmc_cfg;
+
+/*
+ * gpmc_init(): init gpmc bus
+ * This code can only be executed from SRAM or SDRAM.
+ */
+void gpmc_init(void)
+{
+ gpmc_cfg = (struct gpmc *)GPMC_BASE;
+
+ /* global settings */
+ writel(0, gpmc_cfg-irqenable); /* isr's sources masked */
+ writel(0, gpmc_cfg-timeout_control);/* timeout disable */
+
+ /*
+* Disable the GPMC0 config set by ROM code
+* It conflicts with our MPDB (both at 0x0800)
+*/
+ writel(0, gpmc_cfg-cs[0].config7);
+}
diff --git a/arch/arm/include/asm/arch-omap4/cpu.h
b/arch/arm/include/asm/arch-omap4/cpu.h
index 7d8aa20..1b65408 100644
--- a/arch/arm/include/asm/arch-omap4/cpu.h
+++ b/arch/arm/include/asm/arch-omap4/cpu.h
@@ -31,6 +31,51 @@
#ifndef __KERNEL_STRICT_NAMES
#ifndef __ASSEMBLY__
+struct gpmc_cs {
+ u32 config1;/* 0x00 */
+ u32 config2;/* 0x04 */
+ u32 config3;/* 0x08 */
+ u32 config4;/* 0x0C */
+ u32 config5;/* 0x10 */
+ u32 config6;/* 0x14 */
+ u32 config7;/* 0x18 */
+ u32 nand_cmd; /* 0x1C */
+ u32 nand_adr; /* 0x20 */
+ u32 nand_dat; /* 0x24 */
+ u8 res[8]; /* blow up to 0x30 byte */
+};
+
+struct gpmc {
+ u8 res1[0x10];
+ u32 sysconfig; /* 0x10 */
+ u8 res2[0x4];
+ u32 irqstatus; /* 0x18 */
+ u32 irqenable; /* 0x1C */
+ u8 res3[0x20];
+ u32 timeout_control;/* 0x40 */
+ u8 res4[0xC];
+ u32 config; /* 0x50 */
+ u32 status; /* 0x54 */
+ u8 res5[0x8]; /* 0x58 */
+ struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
+ u8 res6[0x14]; /* 0x1E0 */
+ u32 ecc_config; /* 0x1F4 */
+ u32 ecc_control;/* 0x1F8 */
+ u32 ecc_size_config;/* 0x1FC */
+ u32 ecc1_result;/* 0x200 */
+ u32 ecc2_result;/* 0x204 */
+ u32 ecc3_result;/* 0x208 */
+ u32 ecc4_result;/* 0x20C */
+ u32 ecc5_result;/* 0x210 */
+ u32 ecc6_result;/* 0x214 */
+ u32 ecc7_result;/* 0x218 */
+ u32 ecc8_result;/* 0x21C */
+ u32 ecc9_result;/* 0x220 */
+};
+
+/* Used for board specific gpmc initialization */
+extern struct gpmc *gpmc_cfg;
+
struct gptimer {
u32 tidr; /* 0x00 r */
u8 res[0xc];
@@ -86,6 +131,9 @@ struct watchdog {
#define TCLR_AR(0x1 1)
#define TCLR_PRE (0x1 5)
+/* GPMC BASE */
+#define GPMC_BASE (OMAP44XX_GPMC_BASE)
+
