Re: [U-Boot] [PATCH] EXYNOS5: Add L2 Cache Support.
On 30/11/12 15:29, Rajeshwari Shinde wrote: This patch set adds L2 Cache Support to EXYNOS. Signed-off-by: Arun Mankuzhi aru...@samsung.com Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com --- arch/arm/cpu/armv7/exynos/soc.c | 37 + 1 files changed, 37 insertions(+), 0 deletions(-) Sorry! too late. appiled to u-boot-samsung. Thanks, Minkyu Kang. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] EXYNOS5: Add L2 Cache Support.
Hi Minkyu, Please do let me know if any comments for same. Regards, Rajeshwari Shinde. On Thu, Dec 27, 2012 at 11:29 AM, Rajeshwari Birje rajeshwari.bi...@gmail.com wrote: Minkyu Kang, Please do let me know if any comments regarding this patch. Regards, Rajeshwari Shinde. -- Regards, Rajeshwari Shinde ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] EXYNOS5: Add L2 Cache Support.
Hi Minkyu Kang,
Please do let me know if any comments regarding this patch.
Regards,
Rajeshwari Shinde.
On Sun, Dec 9, 2012 at 1:08 AM, Simon Glass s...@chromium.org wrote:
On Thu, Nov 29, 2012 at 10:29 PM, Rajeshwari Shinde
rajeshwar...@samsung.com wrote:
This patch set adds L2 Cache Support to EXYNOS.
Signed-off-by: Arun Mankuzhi aru...@samsung.com
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
Acked-by: Simon Glass s...@chromium.org
---
arch/arm/cpu/armv7/exynos/soc.c | 37
+
1 files changed, 37 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/soc.c
b/arch/arm/cpu/armv7/exynos/soc.c
index ab65b8d..676a388 100644
--- a/arch/arm/cpu/armv7/exynos/soc.c
+++ b/arch/arm/cpu/armv7/exynos/soc.c
@@ -23,6 +23,14 @@
#include common.h
#include asm/io.h
+#include asm/system.h
+
+enum l2_cache_params {
+ CACHE_TAG_RAM_SETUP = (19),
+ CACHE_DATA_RAM_SETUP = (15),
+ CACHE_TAG_RAM_LATENCY = (26),
+ CACHE_DATA_RAM_LATENCY = (20)
+};
void reset_cpu(ulong addr)
{
@@ -36,3 +44,32 @@ void enable_caches(void)
dcache_enable();
}
#endif
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+/*
+ * Set L2 cache parameters
+ */
+static void exynos5_set_l2cache_params(void)
+{
+ unsigned int val = 0;
+
+ asm volatile(mrc p15, 1, %0, c9, c0, 2\n : =r(val));
+
+ val |= CACHE_TAG_RAM_SETUP |
+ CACHE_DATA_RAM_SETUP |
+ CACHE_TAG_RAM_LATENCY |
+ CACHE_DATA_RAM_LATENCY;
+
+ asm volatile(mcr p15, 1, %0, c9, c0, 2\n : : r(val));
+}
+
+/*
+ * Sets L2 cache related parameters before enabling data cache
+ */
+void v7_outer_cache_enable(void)
+{
+ if (cpu_is_exynos5())
+ exynos5_set_l2cache_params();
+}
+#endif
+
--
1.7.4.4
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--
Regards,
Rajeshwari Shinde
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Re: [U-Boot] [PATCH] EXYNOS5: Add L2 Cache Support.
Hi Simon, Yes it is a V2 patch. Sorry I missed the add the same will submitting the patch. Regards, Rajeshwari Shinde. On Sun, Dec 9, 2012 at 1:08 AM, Simon Glass s...@chromium.org wrote: On Sat, Dec 8, 2012 at 11:38 AM, Simon Glass s...@chromium.org wrote: On Thu, Nov 29, 2012 at 10:29 PM, Rajeshwari Shinde rajeshwar...@samsung.com wrote: This patch set adds L2 Cache Support to EXYNOS. Signed-off-by: Arun Mankuzhi aru...@samsung.com Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com Acked-by: Simon Glass s...@chromium.org BTW I am assuming this is v2? It looks like it. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] EXYNOS5: Add L2 Cache Support.
On Thu, Nov 29, 2012 at 10:29 PM, Rajeshwari Shinde
rajeshwar...@samsung.com wrote:
This patch set adds L2 Cache Support to EXYNOS.
Signed-off-by: Arun Mankuzhi aru...@samsung.com
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
Acked-by: Simon Glass s...@chromium.org
---
arch/arm/cpu/armv7/exynos/soc.c | 37 +
1 files changed, 37 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/soc.c b/arch/arm/cpu/armv7/exynos/soc.c
index ab65b8d..676a388 100644
--- a/arch/arm/cpu/armv7/exynos/soc.c
+++ b/arch/arm/cpu/armv7/exynos/soc.c
@@ -23,6 +23,14 @@
#include common.h
#include asm/io.h
+#include asm/system.h
+
+enum l2_cache_params {
+ CACHE_TAG_RAM_SETUP = (19),
+ CACHE_DATA_RAM_SETUP = (15),
+ CACHE_TAG_RAM_LATENCY = (26),
+ CACHE_DATA_RAM_LATENCY = (20)
+};
void reset_cpu(ulong addr)
{
@@ -36,3 +44,32 @@ void enable_caches(void)
dcache_enable();
}
#endif
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+/*
+ * Set L2 cache parameters
+ */
+static void exynos5_set_l2cache_params(void)
+{
+ unsigned int val = 0;
+
+ asm volatile(mrc p15, 1, %0, c9, c0, 2\n : =r(val));
+
+ val |= CACHE_TAG_RAM_SETUP |
+ CACHE_DATA_RAM_SETUP |
+ CACHE_TAG_RAM_LATENCY |
+ CACHE_DATA_RAM_LATENCY;
+
+ asm volatile(mcr p15, 1, %0, c9, c0, 2\n : : r(val));
+}
+
+/*
+ * Sets L2 cache related parameters before enabling data cache
+ */
+void v7_outer_cache_enable(void)
+{
+ if (cpu_is_exynos5())
+ exynos5_set_l2cache_params();
+}
+#endif
+
--
1.7.4.4
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Re: [U-Boot] [PATCH] EXYNOS5: Add L2 Cache Support.
On Sat, Dec 8, 2012 at 11:38 AM, Simon Glass s...@chromium.org wrote: On Thu, Nov 29, 2012 at 10:29 PM, Rajeshwari Shinde rajeshwar...@samsung.com wrote: This patch set adds L2 Cache Support to EXYNOS. Signed-off-by: Arun Mankuzhi aru...@samsung.com Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com Acked-by: Simon Glass s...@chromium.org BTW I am assuming this is v2? It looks like it. Regards, Simon ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] EXYNOS5: Add L2 Cache Support.
This patch set adds L2 Cache Support to EXYNOS.
Signed-off-by: Arun Mankuzhi aru...@samsung.com
Signed-off-by: Rajeshwari Shinde rajeshwar...@samsung.com
---
arch/arm/cpu/armv7/exynos/soc.c | 37 +
1 files changed, 37 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/soc.c b/arch/arm/cpu/armv7/exynos/soc.c
index ab65b8d..676a388 100644
--- a/arch/arm/cpu/armv7/exynos/soc.c
+++ b/arch/arm/cpu/armv7/exynos/soc.c
@@ -23,6 +23,14 @@
#include common.h
#include asm/io.h
+#include asm/system.h
+
+enum l2_cache_params {
+ CACHE_TAG_RAM_SETUP = (19),
+ CACHE_DATA_RAM_SETUP = (15),
+ CACHE_TAG_RAM_LATENCY = (26),
+ CACHE_DATA_RAM_LATENCY = (20)
+};
void reset_cpu(ulong addr)
{
@@ -36,3 +44,32 @@ void enable_caches(void)
dcache_enable();
}
#endif
+
+#ifndef CONFIG_SYS_L2CACHE_OFF
+/*
+ * Set L2 cache parameters
+ */
+static void exynos5_set_l2cache_params(void)
+{
+ unsigned int val = 0;
+
+ asm volatile(mrc p15, 1, %0, c9, c0, 2\n : =r(val));
+
+ val |= CACHE_TAG_RAM_SETUP |
+ CACHE_DATA_RAM_SETUP |
+ CACHE_TAG_RAM_LATENCY |
+ CACHE_DATA_RAM_LATENCY;
+
+ asm volatile(mcr p15, 1, %0, c9, c0, 2\n : : r(val));
+}
+
+/*
+ * Sets L2 cache related parameters before enabling data cache
+ */
+void v7_outer_cache_enable(void)
+{
+ if (cpu_is_exynos5())
+ exynos5_set_l2cache_params();
+}
+#endif
+
--
1.7.4.4
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