Re: [U-Boot] [PATCH] PCI: layerscape: Make the pcie link up status judgement more specific

2017-09-14 Thread Xiaowei Bao 
Hi York,

I will update the patch at next week, I have other thing to do this week.

Thanks

-Original Message-
From: York Sun 
Sent: Friday, September 15, 2017 4:07 AM
To: Xiaowei Bao ; u-boot@lists.denx.de; Priyanka Jain 
; Z.q. Hou ; M.h. Lian 
; s...@chromium.org
Subject: Re: [PATCH] PCI: layerscape: Make the pcie link up status judgement 
more specific

On 08/15/2017 11:32 PM, Xiaowei Bao wrote:
> Hi York,
> 
> Yes, it is my mean, I am not brief enough to express, thank you correct me.

Xiaowei,

Please update his patch as discussed.

York
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Re: [U-Boot] [PATCH] PCI: layerscape: Make the pcie link up status judgement more specific

2017-09-14 Thread York Sun 
On 08/15/2017 11:32 PM, Xiaowei Bao wrote:
> Hi York,
> 
> Yes, it is my mean, I am not brief enough to express, thank you correct me.

Xiaowei,

Please update his patch as discussed.

York
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Re: [U-Boot] [PATCH] PCI: layerscape: Make the pcie link up status judgement more specific

2017-08-16 Thread Xiaowei Bao 
Hi York,

Yes, it is my mean, I am not brief enough to express, thank you correct me.

Thanks

-Original Message-
From: York Sun 
Sent: Tuesday, August 15, 2017 11:20 PM
To: Xiaowei Bao ; u-boot@lists.denx.de; Priyanka Jain 
; Z.q. Hou ; M.h. Lian 
; s...@chromium.org
Subject: Re: [PATCH] PCI: layerscape: Make the pcie link up status judgement 
more specific

On 08/15/2017 03:03 AM, Bao Xiaowei wrote:
> For some special reset times for longer pcie devices, in this case, 
> the pcie device may on polling compliance state, the RC considers the 
> pcie device is link up, but the pcie device is not link up, only the 
> L0 state is link up state. So add the link up status judgement mechanisms.
> 

Xiaowei,

Let me try to rephrase your commit message. Correct me if I get it wrong. I 
think you mean

Determine PCIe link status by checking L0 state. If L0 state is detected within 
100ms, link status is reported as up.

> Signed-off-by: Bao Xiaowei 
> ---

For future patches, please add change log here and revision number in the 
subject.

>   drivers/pci/pcie_layerscape.c | 25 +
>   drivers/pci/pcie_layerscape.h |  3 +++
>   2 files changed, 24 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/pci/pcie_layerscape.c 
> b/drivers/pci/pcie_layerscape.c index 78cde21..4db95c5 100644
> --- a/drivers/pci/pcie_layerscape.c
> +++ b/drivers/pci/pcie_layerscape.c
> @@ -69,13 +69,30 @@ static int ls_pcie_ltssm(struct ls_pcie *pcie)
>   
>   static int ls_pcie_link_up(struct ls_pcie *pcie)
>   {
> - int ltssm;
> + int ltssm, i;
>   
>   ltssm = ls_pcie_ltssm(pcie);
> - if (ltssm < LTSSM_PCIE_L0)
> - return 0;
>   
> - return 1;
> + /*
> +  * For some special reset times for longer pcie devices,
> +  * the pcie device may on polling compliance state,
> +  * on this state, if the device can restored to the L0 state
> +  * within 100ms considers the pcie device is link up
> +  */

> + if (ltssm == LTSSM_PCIE_DETECT_QUIET ||
> + ltssm == LTSSM_PCIE_DETECT_ACTIVE) {

Please explain the above two lines with comment.

> + return 0;
> + } else if (ltssm == LTSSM_PCIE_L0) {
> + return 1;
> + } else {

How about this comment?
/*
 * For some devices requiring longer reset time, check if L0
 * state can be reached within 100ms.
 */

> + for (i = 0; i < 100; i++) {
> + udelay(1000);
> + ltssm = ls_pcie_ltssm(pcie);
> + if (ltssm == LTSSM_PCIE_L0)
> + return 1;
> + }
> + return 0;
> + }
>   }
>   
>   static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 
> busdev) diff --git a/drivers/pci/pcie_layerscape.h 
> b/drivers/pci/pcie_layerscape.h index 782e3ab..4313e85 100644
> --- a/drivers/pci/pcie_layerscape.h
> +++ b/drivers/pci/pcie_layerscape.h
> @@ -70,6 +70,9 @@
>   
>   #define LTSSM_STATE_MASK0x3f
>   #define LTSSM_PCIE_L0   0x11 /* L0 state */
> +#define LTSSM_PCIE_DETECT_QUIET  0x00 /* L0 state */
> +#define LTSSM_PCIE_DETECT_ACTIVE 0x01 /* L0 state */
> +#define LTSSM_PCIE_L00x11 /* L0 state */
>   
>   #define PCIE_DBI_SIZE   0x10 /* 1M */
>   
> 

York
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Re: [U-Boot] [PATCH] PCI: layerscape: Make the pcie link up status judgement more specific

2017-08-15 Thread York Sun 
On 08/15/2017 03:03 AM, Bao Xiaowei wrote:
> For some special reset times for longer pcie devices, in this case, the
> pcie device may on polling compliance state, the RC considers the pcie
> device is link up, but the pcie device is not link up, only the L0 state
> is link up state. So add the link up status judgement mechanisms.
> 

Xiaowei,

Let me try to rephrase your commit message. Correct me if I get it 
wrong. I think you mean

Determine PCIe link status by checking L0 state. If L0 state is detected 
within 100ms, link status is reported as up.

> Signed-off-by: Bao Xiaowei 
> ---

For future patches, please add change log here and revision number in 
the subject.

>   drivers/pci/pcie_layerscape.c | 25 +
>   drivers/pci/pcie_layerscape.h |  3 +++
>   2 files changed, 24 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
> index 78cde21..4db95c5 100644
> --- a/drivers/pci/pcie_layerscape.c
> +++ b/drivers/pci/pcie_layerscape.c
> @@ -69,13 +69,30 @@ static int ls_pcie_ltssm(struct ls_pcie *pcie)
>   
>   static int ls_pcie_link_up(struct ls_pcie *pcie)
>   {
> - int ltssm;
> + int ltssm, i;
>   
>   ltssm = ls_pcie_ltssm(pcie);
> - if (ltssm < LTSSM_PCIE_L0)
> - return 0;
>   
> - return 1;
> + /*
> +  * For some special reset times for longer pcie devices,
> +  * the pcie device may on polling compliance state,
> +  * on this state, if the device can restored to the L0 state
> +  * within 100ms considers the pcie device is link up
> +  */

> + if (ltssm == LTSSM_PCIE_DETECT_QUIET ||
> + ltssm == LTSSM_PCIE_DETECT_ACTIVE) {

Please explain the above two lines with comment.

> + return 0;
> + } else if (ltssm == LTSSM_PCIE_L0) {
> + return 1;
> + } else {

How about this comment?
/*
 * For some devices requiring longer reset time, check if L0
 * state can be reached within 100ms.
 */

> + for (i = 0; i < 100; i++) {
> + udelay(1000);
> + ltssm = ls_pcie_ltssm(pcie);
> + if (ltssm == LTSSM_PCIE_L0)
> + return 1;
> + }
> + return 0;
> + }
>   }
>   
>   static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev)
> diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
> index 782e3ab..4313e85 100644
> --- a/drivers/pci/pcie_layerscape.h
> +++ b/drivers/pci/pcie_layerscape.h
> @@ -70,6 +70,9 @@
>   
>   #define LTSSM_STATE_MASK0x3f
>   #define LTSSM_PCIE_L0   0x11 /* L0 state */
> +#define LTSSM_PCIE_DETECT_QUIET  0x00 /* L0 state */
> +#define LTSSM_PCIE_DETECT_ACTIVE 0x01 /* L0 state */
> +#define LTSSM_PCIE_L00x11 /* L0 state */
>   
>   #define PCIE_DBI_SIZE   0x10 /* 1M */
>   
> 

York
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[U-Boot] [PATCH] PCI: layerscape: Make the pcie link up status judgement more specific

2017-08-15 Thread Bao Xiaowei 
For some special reset times for longer pcie devices, in this case, the
pcie device may on polling compliance state, the RC considers the pcie
device is link up, but the pcie device is not link up, only the L0 state
is link up state. So add the link up status judgement mechanisms.

Signed-off-by: Bao Xiaowei 
---
 drivers/pci/pcie_layerscape.c | 25 +
 drivers/pci/pcie_layerscape.h |  3 +++
 2 files changed, 24 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c
index 78cde21..4db95c5 100644
--- a/drivers/pci/pcie_layerscape.c
+++ b/drivers/pci/pcie_layerscape.c
@@ -69,13 +69,30 @@ static int ls_pcie_ltssm(struct ls_pcie *pcie)
 
 static int ls_pcie_link_up(struct ls_pcie *pcie)
 {
-   int ltssm;
+   int ltssm, i;
 
ltssm = ls_pcie_ltssm(pcie);
-   if (ltssm < LTSSM_PCIE_L0)
-   return 0;
 
-   return 1;
+   /*
+* For some special reset times for longer pcie devices,
+* the pcie device may on polling compliance state,
+* on this state, if the device can restored to the L0 state
+* within 100ms considers the pcie device is link up
+*/
+   if (ltssm == LTSSM_PCIE_DETECT_QUIET ||
+   ltssm == LTSSM_PCIE_DETECT_ACTIVE) {
+   return 0;
+   } else if (ltssm == LTSSM_PCIE_L0) {
+   return 1;
+   } else {
+   for (i = 0; i < 100; i++) {
+   udelay(1000);
+   ltssm = ls_pcie_ltssm(pcie);
+   if (ltssm == LTSSM_PCIE_L0)
+   return 1;
+   }
+   return 0;
+   }
 }
 
 static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev)
diff --git a/drivers/pci/pcie_layerscape.h b/drivers/pci/pcie_layerscape.h
index 782e3ab..4313e85 100644
--- a/drivers/pci/pcie_layerscape.h
+++ b/drivers/pci/pcie_layerscape.h
@@ -70,6 +70,9 @@
 
 #define LTSSM_STATE_MASK   0x3f
 #define LTSSM_PCIE_L0  0x11 /* L0 state */
+#define LTSSM_PCIE_DETECT_QUIET0x00 /* L0 state */
+#define LTSSM_PCIE_DETECT_ACTIVE   0x01 /* L0 state */
+#define LTSSM_PCIE_L0  0x11 /* L0 state */
 
 #define PCIE_DBI_SIZE  0x10 /* 1M */
 
-- 
2.1.0.27.g96db324

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