[U-Boot] [PATCH] PCIe:Add a function to get the address of requested capability structure.

2013-09-08 Thread Zhao Qiang 
Add a function to get the address of requested capability structure in PCIe
configuration space by capability ID.
The step of this function:
1. Read Status register in PCIe configuration space to confirm that
   Capabilities List is valid.
2. Find the address of Capabilities Pointer Register.
3. Find the address of requested capability from the first capability.

Signed-off-by: Zhao Qiang b45...@freescale.com
---
 arch/powerpc/include/asm/fsl_pci.h | 13 +---
 drivers/pci/fsl_pci_init.c | 44 +++---
 drivers/pci/pci.c  | 65 ++
 include/pci.h  | 10 ++
 4 files changed, 108 insertions(+), 24 deletions(-)

diff --git a/arch/powerpc/include/asm/fsl_pci.h 
b/arch/powerpc/include/asm/fsl_pci.h
index 90b0a2f..6b12afa 100644
--- a/arch/powerpc/include/asm/fsl_pci.h
+++ b/arch/powerpc/include/asm/fsl_pci.h
@@ -32,22 +32,11 @@
 /* Freescale-specific PCI config registers */
 #define FSL_PCI_PBFR   0x44
 
-#ifdef CONFIG_SYS_FSL_PCI_VER_3_X
+#ifndef CONFIG_SYS_FSL_PCI_VER_3_X
 /* Currently only the PCIe capability is used, so hardcode the offset.
  * if more capabilities need to be justified, the capability link method
  * should be applied here
  */
-#define FSL_PCIE_CAP_ID0x70
-#define PCI_DCR0x78/* PCIe Device Control Register */
-#define PCI_DSR0x7a/* PCIe Device Status Register */
-#define PCI_LSR0x82/* PCIe Link Status Register */
-#define PCI_LCR0x80/* PCIe Link Control Register */
-#else
-#define FSL_PCIE_CAP_ID0x4c
-#define PCI_DCR0x54/* PCIe Device Control Register */
-#define PCI_DSR0x56/* PCIe Device Status Register */
-#define PCI_LSR0x5e/* PCIe Link Status Register */
-#define PCI_LCR0x5c/* PCIe Link Control Register */
 #define FSL_PCIE_CFG_RDY   0x4b0
 #endif
 #define FSL_PCI_CFG_READY  1 /* Endpoint: allow inbound configuration */
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 76337fe..492efcf 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -308,6 +308,15 @@ void fsl_pci_init(struct pci_controller *hose, struct 
fsl_pci_info *pci_info)
int enabled, r, inbound = 0;
u16 ltssm;
u8 temp8, pcie_cap;
+   int pcie_cap_pos;
+   int pci_dcr;
+   int pci_dsr;
+   int pci_lsr;
+
+#if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
+   int pci_lcr;
+#endif
+
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
struct pci_region *reg = hose-regions + hose-region_count;
pci_dev_t dev = PCI_BDF(hose-first_busno, 0, 0);
@@ -380,7 +389,12 @@ void fsl_pci_init(struct pci_controller *hose, struct 
fsl_pci_info *pci_info)
hose-region_count++;
 
/* see if we are a PCIe or PCI controller */
-   pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, pcie_cap);
+   pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
+   pci_dcr = pcie_cap_pos + 0x08;
+   pci_dsr = pcie_cap_pos + 0x0a;
+   pci_lsr = pcie_cap_pos + 0x12;
+
+   pci_hose_read_config_byte(hose, dev, pcie_cap_pos, pcie_cap);
 
 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
/* boot from PCIE --master */
@@ -419,15 +433,16 @@ void fsl_pci_init(struct pci_controller *hose, struct 
fsl_pci_info *pci_info)
 * - Master PERR (pci)
 * - ICCA (PCIe)
 */
-   pci_hose_read_config_dword(hose, dev, PCI_DCR, temp32);
+   pci_hose_read_config_dword(hose, dev, pci_dcr, temp32);
temp32 |= 0xf000e;  /* set URR, FER, NFER (but not CER) */
-   pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32);
+   pci_hose_write_config_dword(hose, dev, pci_dcr, temp32);
 
 #if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
+   pci_lcr = pcie_cap_pos + 0x10;
temp32 = 0;
-   pci_hose_read_config_dword(hose, dev, PCI_LCR, temp32);
+   pci_hose_read_config_dword(hose, dev, pci_lcr, temp32);
temp32 = ~0x03;/* Disable ASPM  */
-   pci_hose_write_config_dword(hose, dev, PCI_LCR, temp32);
+   pci_hose_write_config_dword(hose, dev, pci_lcr, temp32);
udelay(1);
 #endif
if (pcie_cap == PCI_CAP_ID_EXP) {
@@ -507,7 +522,7 @@ void fsl_pci_init(struct pci_controller *hose, struct 
fsl_pci_info *pci_info)
out_be32(pci-pme_msg_int_en, 0x);
 
/* Print the negotiated PCIe link width */
-   pci_hose_read_config_word(hose, dev, PCI_LSR, temp16);
+   pci_hose_read_config_word(hose, dev, pci_lsr, temp16);
printf(x%d, regs @ 0x%lx\n, (temp16  0x3f0 )  4,
pci_info-regs);
 
@@ -554,9 +569,9 @@ void

Re: [U-Boot] [PATCH] PCIe:Add a function to get the address of requested capability structure.

2013-09-08 Thread Wolfgang Denk 
Dear Zhao Qiang,

In message 1378689694-26708-1-git-send-email-b45...@freescale.com you wrote:
 Add a function to get the address of requested capability structure in PCIe
 configuration space by capability ID.
 The step of this function:
   1. Read Status register in PCIe configuration space to confirm that
  Capabilities List is valid.
   2. Find the address of Capabilities Pointer Register.
   3. Find the address of requested capability from the first capability.

Why would such an extension be needed?  As is, you are just adding
dead code.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH, MD: Wolfgang Denk  Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
I haven't lost my mind - it's backed up on tape somewhere.
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[U-Boot] [PATCH] PCIe:Add a function to get the address of requested capability structure.

2013-08-19 Thread Zhao Qiang 
Add a function to get the address of requested capability structure in PCIe
configuration space by capability ID.
The step of this function:
1. Read Status register in PCIe configuration space to confirm that
   Capabilities List is valid.
2. Find the address of Capabilities Pointer Register.
3. Find the address of requested capability from the first capability.

Signed-off-by: Zhao Qiang b45...@freescale.com
---
 arch/powerpc/include/asm/fsl_pci.h | 13 +---
 drivers/pci/fsl_pci_init.c | 40 +++---
 drivers/pci/pci.c  | 68 ++
 include/pci.h  |  7 
 4 files changed, 104 insertions(+), 24 deletions(-)

diff --git a/arch/powerpc/include/asm/fsl_pci.h 
b/arch/powerpc/include/asm/fsl_pci.h
index 90b0a2f..6b12afa 100644
--- a/arch/powerpc/include/asm/fsl_pci.h
+++ b/arch/powerpc/include/asm/fsl_pci.h
@@ -32,22 +32,11 @@
 /* Freescale-specific PCI config registers */
 #define FSL_PCI_PBFR   0x44
 
-#ifdef CONFIG_SYS_FSL_PCI_VER_3_X
+#ifndef CONFIG_SYS_FSL_PCI_VER_3_X
 /* Currently only the PCIe capability is used, so hardcode the offset.
  * if more capabilities need to be justified, the capability link method
  * should be applied here
  */
-#define FSL_PCIE_CAP_ID0x70
-#define PCI_DCR0x78/* PCIe Device Control Register */
-#define PCI_DSR0x7a/* PCIe Device Status Register */
-#define PCI_LSR0x82/* PCIe Link Status Register */
-#define PCI_LCR0x80/* PCIe Link Control Register */
-#else
-#define FSL_PCIE_CAP_ID0x4c
-#define PCI_DCR0x54/* PCIe Device Control Register */
-#define PCI_DSR0x56/* PCIe Device Status Register */
-#define PCI_LSR0x5e/* PCIe Link Status Register */
-#define PCI_LCR0x5c/* PCIe Link Control Register */
 #define FSL_PCIE_CFG_RDY   0x4b0
 #endif
 #define FSL_PCI_CFG_READY  1 /* Endpoint: allow inbound configuration */
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 76337fe..5004fea 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -308,6 +308,11 @@ void fsl_pci_init(struct pci_controller *hose, struct 
fsl_pci_info *pci_info)
int enabled, r, inbound = 0;
u16 ltssm;
u8 temp8, pcie_cap;
+   int pcie_cap_pos;
+   int pci_dcr;
+   int pci_dsr;
+   int pci_lsr;
+   int pci_lcr;
volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
struct pci_region *reg = hose-regions + hose-region_count;
pci_dev_t dev = PCI_BDF(hose-first_busno, 0, 0);
@@ -380,7 +385,13 @@ void fsl_pci_init(struct pci_controller *hose, struct 
fsl_pci_info *pci_info)
hose-region_count++;
 
/* see if we are a PCIe or PCI controller */
-   pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, pcie_cap);
+   pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
+   pci_dcr = pcie_cap_pos + 0x08;
+   pci_dsr = pcie_cap_pos + 0x0a;
+   pci_lsr = pcie_cap_pos + 0x12;
+   pci_lcr = pcie_cap_pos + 0x10;
+
+   pci_hose_read_config_byte(hose, dev, pcie_cap_pos, pcie_cap);
 
 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
/* boot from PCIE --master */
@@ -419,15 +430,15 @@ void fsl_pci_init(struct pci_controller *hose, struct 
fsl_pci_info *pci_info)
 * - Master PERR (pci)
 * - ICCA (PCIe)
 */
-   pci_hose_read_config_dword(hose, dev, PCI_DCR, temp32);
+   pci_hose_read_config_dword(hose, dev, pci_dcr, temp32);
temp32 |= 0xf000e;  /* set URR, FER, NFER (but not CER) */
-   pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32);
+   pci_hose_write_config_dword(hose, dev, pci_dcr, temp32);
 
 #if defined(CONFIG_FSL_PCIE_DISABLE_ASPM)
temp32 = 0;
-   pci_hose_read_config_dword(hose, dev, PCI_LCR, temp32);
+   pci_hose_read_config_dword(hose, dev, pci_lcr, temp32);
temp32 = ~0x03;/* Disable ASPM  */
-   pci_hose_write_config_dword(hose, dev, PCI_LCR, temp32);
+   pci_hose_write_config_dword(hose, dev, pci_lcr, temp32);
udelay(1);
 #endif
if (pcie_cap == PCI_CAP_ID_EXP) {
@@ -507,7 +518,7 @@ void fsl_pci_init(struct pci_controller *hose, struct 
fsl_pci_info *pci_info)
out_be32(pci-pme_msg_int_en, 0x);
 
/* Print the negotiated PCIe link width */
-   pci_hose_read_config_word(hose, dev, PCI_LSR, temp16);
+   pci_hose_read_config_word(hose, dev, pci_lsr, temp16);
printf(x%d, regs @ 0x%lx\n, (temp16  0x3f0 )  4,
pci_info-regs);
 
@@ -554,9 +565,9 @@ void fsl_pci_init(struct pci_controller *hose, struct