Re: [U-Boot] [PATCH] am335x:Handle worst case scenario for Errata 1.0.24
On Mon, Jul 22, 2013 at 08:33:44PM +0530, Lokesh Vutla wrote: > On Monday 22 July 2013 08:12 PM, Tom Rini wrote: > > From: Steve Kipisz > > > > In Errata 1.0.24, if the board is running at OPP50 and has a warm reset, > > the boot ROM sets the frequencies for OPP100. This patch attempts to > > drop the frequencies back to OPP50 as soon as possible in the SPL. Then > > later the voltages and frequencies up set higher. > > > > Cc: Enric Balletbo i Serra > > Cc: Lars Poeschel > > Signed-off-by: Steve Kipisz > > [trini: Adapt to current framework] > > Signed-off-by: Tom Rini > Doesn't this patch gives a conflict with recent cleanup series > for Am33xx ? > http://patchwork.ozlabs.org/patch/253831/ Yes, and in a non-trivial fashion since we need to be able to give an initial configuration to the clock, and then change it again, and I don't see how to do that with your cleanup. In fact, the other series I posted, for scaling up the MPU clock also won't work with your cleanup. -- Tom signature.asc Description: Digital signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] am335x:Handle worst case scenario for Errata 1.0.24
On Monday 22 July 2013 08:12 PM, Tom Rini wrote:
> From: Steve Kipisz
>
> In Errata 1.0.24, if the board is running at OPP50 and has a warm reset,
> the boot ROM sets the frequencies for OPP100. This patch attempts to
> drop the frequencies back to OPP50 as soon as possible in the SPL. Then
> later the voltages and frequencies up set higher.
>
> Cc: Enric Balletbo i Serra
> Cc: Lars Poeschel
> Signed-off-by: Steve Kipisz
> [trini: Adapt to current framework]
> Signed-off-by: Tom Rini
Doesn't this patch gives a conflict with recent cleanup series
for Am33xx ?
http://patchwork.ozlabs.org/patch/253831/
Thanks,
Lokesh
> ---
> arch/arm/cpu/armv7/am33xx/board.c|2 +
> arch/arm/cpu/armv7/am33xx/clock_am33xx.c | 72
> ++
> arch/arm/include/asm/arch-am33xx/clocks_am33xx.h |3 +
> arch/arm/include/asm/arch-am33xx/sys_proto.h |1 +
> board/ti/am335x/board.c | 11
> include/configs/pcm051.h |1 +
> include/power/tps65217.h |1 +
> 7 files changed, 67 insertions(+), 24 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/am33xx/board.c
> b/arch/arm/cpu/armv7/am33xx/board.c
> index 9356501..03427da 100644
> --- a/arch/arm/cpu/armv7/am33xx/board.c
> +++ b/arch/arm/cpu/armv7/am33xx/board.c
> @@ -158,6 +158,8 @@ int arch_misc_init(void)
> */
> __weak void am33xx_spl_board_init(void)
> {
> + mpu_pll_config_val(CONFIG_SYS_MPUCLK);
> + core_pll_config(OPP_100);
> }
>
> void rtc32k_enable(void)
> diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
> b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
> index 9c4d0b4..ef06814 100644
> --- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
> +++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
> @@ -50,12 +50,17 @@
>
> /* Core PLL Fdll = 1 GHZ, */
> #define COREPLL_M1000
> +#define COREPLL_M_OPP50 50
> #define COREPLL_N(OSC-1)
>
> #define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */
> #define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */
> #define COREPLL_M6 4 /* CORE_CLKOUTM6 = 500 MHZ */
>
> +#define COREPLL_M4_OPP50 1
> +#define COREPLL_M5_OPP50 1
> +#define COREPLL_M6_OPP50 1
> +
> /*
> * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
> * frequency needs to be set to 960 MHZ. Hence,
> @@ -274,12 +279,7 @@ void mpu_pll_config_val(int mpull_m)
> ;
> }
>
> -static void mpu_pll_config(void)
> -{
> - mpu_pll_config_val(CONFIG_SYS_MPUCLK);
> -}
> -
> -static void core_pll_config(void)
> +void core_pll_config(int opp)
> {
> u32 clkmode, clksel, div_m4, div_m5, div_m6;
>
> @@ -293,29 +293,53 @@ static void core_pll_config(void)
> writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllcore);
>
> while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS)
> - ;
> + ;
> + if (opp == OPP_50) {
> + clksel = clksel & (~CLK_SEL_MASK);
> + clksel = clksel | ((COREPLL_M_OPP50 << CLK_SEL_SHIFT)
> + | COREPLL_N);
> + writel(clksel, &cmwkup->clkseldpllcore);
>
> - clksel = clksel & (~CLK_SEL_MASK);
> - clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N);
> - writel(clksel, &cmwkup->clkseldpllcore);
> + div_m4 = div_m4 & ~CLK_DIV_MASK;
> + div_m4 = div_m4 | COREPLL_M4_OPP50;
> + writel(div_m4, &cmwkup->divm4dpllcore);
>
> - div_m4 = div_m4 & ~CLK_DIV_MASK;
> - div_m4 = div_m4 | COREPLL_M4;
> - writel(div_m4, &cmwkup->divm4dpllcore);
> + div_m5 = div_m5 & ~CLK_DIV_MASK;
> + div_m5 = div_m5 | COREPLL_M5_OPP50;
> + writel(div_m5, &cmwkup->divm5dpllcore);
>
> - div_m5 = div_m5 & ~CLK_DIV_MASK;
> - div_m5 = div_m5 | COREPLL_M5;
> - writel(div_m5, &cmwkup->divm5dpllcore);
> + div_m6 = div_m6 & ~CLK_DIV_MASK;
> + div_m6 = div_m6 | COREPLL_M6_OPP50;
> + writel(div_m6, &cmwkup->divm6dpllcore);
>
> - div_m6 = div_m6 & ~CLK_DIV_MASK;
> - div_m6 = div_m6 | COREPLL_M6;
> - writel(div_m6, &cmwkup->divm6dpllcore);
> + clkmode = clkmode | CLK_MODE_SEL;
> + writel(clkmode, &cmwkup->clkmoddpllcore);
>
> - clkmode = clkmode | CLK_MODE_SEL;
> - writel(clkmode, &cmwkup->clkmoddpllcore);
> + while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK)
> + ;
> + } else {
> + clksel = clksel & (~CLK_SEL_MASK);
> + clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N);
> + writel(clksel, &cmwkup->clkseldpllcore);
> +
> + div_m4 = div_m4 & ~CLK_DIV_MASK;
> + div_m4 = div_m4 | COREPLL_M4;
> + writel(div_m4, &cmwkup->divm4dpllcore);
> +
> + div_m5 = div_m5 & ~CLK_DIV_MASK;
> + div_m5 = div_m5 | COREPLL_M5;
> + writel(div_m5, &cmwkup-
Re: [U-Boot] [PATCH] am335x:Handle worst case scenario for Errata 1.0.24
On 07/22/2013 09:42 AM, Tom Rini wrote:
> From: Steve Kipisz
>
> In Errata 1.0.24, if the board is running at OPP50 and has a warm reset,
> the boot ROM sets the frequencies for OPP100. This patch attempts to
> drop the frequencies back to OPP50 as soon as possible in the SPL. Then
> later the voltages and frequencies up set higher.
>
> Cc: Enric Balletbo i Serra
> Cc: Lars Poeschel
> Signed-off-by: Steve Kipisz
> [trini: Adapt to current framework]
> Signed-off-by: Tom Rini
> ---
> arch/arm/cpu/armv7/am33xx/board.c|2 +
> arch/arm/cpu/armv7/am33xx/clock_am33xx.c | 72
> ++
> arch/arm/include/asm/arch-am33xx/clocks_am33xx.h |3 +
> arch/arm/include/asm/arch-am33xx/sys_proto.h |1 +
> board/ti/am335x/board.c | 11
> include/configs/pcm051.h |1 +
> include/power/tps65217.h |1 +
> 7 files changed, 67 insertions(+), 24 deletions(-)
>
> diff --git a/arch/arm/cpu/armv7/am33xx/board.c
> b/arch/arm/cpu/armv7/am33xx/board.c
> index 9356501..03427da 100644
> --- a/arch/arm/cpu/armv7/am33xx/board.c
> +++ b/arch/arm/cpu/armv7/am33xx/board.c
> @@ -158,6 +158,8 @@ int arch_misc_init(void)
> */
> __weak void am33xx_spl_board_init(void)
> {
> + mpu_pll_config_val(CONFIG_SYS_MPUCLK);
> + core_pll_config(OPP_100);
> }
>
> void rtc32k_enable(void)
> diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
> b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
> index 9c4d0b4..ef06814 100644
> --- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
> +++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
> @@ -50,12 +50,17 @@
>
> /* Core PLL Fdll = 1 GHZ, */
> #define COREPLL_M1000
> +#define COREPLL_M_OPP50 50
> #define COREPLL_N(OSC-1)
>
> #define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */
> #define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */
> #define COREPLL_M6 4 /* CORE_CLKOUTM6 = 500 MHZ */
>
> +#define COREPLL_M4_OPP50 1
> +#define COREPLL_M5_OPP50 1
> +#define COREPLL_M6_OPP50 1
> +
> /*
> * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
> * frequency needs to be set to 960 MHZ. Hence,
> @@ -274,12 +279,7 @@ void mpu_pll_config_val(int mpull_m)
> ;
> }
>
> -static void mpu_pll_config(void)
> -{
> - mpu_pll_config_val(CONFIG_SYS_MPUCLK);
> -}
> -
> -static void core_pll_config(void)
> +void core_pll_config(int opp)
> {
> u32 clkmode, clksel, div_m4, div_m5, div_m6;
>
> @@ -293,29 +293,53 @@ static void core_pll_config(void)
> writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllcore);
>
> while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS)
> - ;
> + ;
> + if (opp == OPP_50) {
> + clksel = clksel & (~CLK_SEL_MASK);
> + clksel = clksel | ((COREPLL_M_OPP50 << CLK_SEL_SHIFT)
> + | COREPLL_N);
> + writel(clksel, &cmwkup->clkseldpllcore);
>
> - clksel = clksel & (~CLK_SEL_MASK);
> - clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N);
> - writel(clksel, &cmwkup->clkseldpllcore);
> + div_m4 = div_m4 & ~CLK_DIV_MASK;
> + div_m4 = div_m4 | COREPLL_M4_OPP50;
> + writel(div_m4, &cmwkup->divm4dpllcore);
>
> - div_m4 = div_m4 & ~CLK_DIV_MASK;
> - div_m4 = div_m4 | COREPLL_M4;
> - writel(div_m4, &cmwkup->divm4dpllcore);
> + div_m5 = div_m5 & ~CLK_DIV_MASK;
> + div_m5 = div_m5 | COREPLL_M5_OPP50;
> + writel(div_m5, &cmwkup->divm5dpllcore);
>
> - div_m5 = div_m5 & ~CLK_DIV_MASK;
> - div_m5 = div_m5 | COREPLL_M5;
> - writel(div_m5, &cmwkup->divm5dpllcore);
> + div_m6 = div_m6 & ~CLK_DIV_MASK;
> + div_m6 = div_m6 | COREPLL_M6_OPP50;
> + writel(div_m6, &cmwkup->divm6dpllcore);
>
> - div_m6 = div_m6 & ~CLK_DIV_MASK;
> - div_m6 = div_m6 | COREPLL_M6;
> - writel(div_m6, &cmwkup->divm6dpllcore);
> + clkmode = clkmode | CLK_MODE_SEL;
> + writel(clkmode, &cmwkup->clkmoddpllcore);
>
> - clkmode = clkmode | CLK_MODE_SEL;
> - writel(clkmode, &cmwkup->clkmoddpllcore);
> + while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK)
> + ;
> + } else {
> + clksel = clksel & (~CLK_SEL_MASK);
> + clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N);
> + writel(clksel, &cmwkup->clkseldpllcore);
> +
> + div_m4 = div_m4 & ~CLK_DIV_MASK;
> + div_m4 = div_m4 | COREPLL_M4;
> + writel(div_m4, &cmwkup->divm4dpllcore);
> +
> + div_m5 = div_m5 & ~CLK_DIV_MASK;
> + div_m5 = div_m5 | COREPLL_M5;
> + writel(div_m5, &cmwkup->divm5dpllcore);
> +
> + div_m6 = div_m6 & ~CLK_DIV_MASK;
> + div_m6 = div_m6 | COREPLL_M6;
> + writel(div_m6,
[U-Boot] [PATCH] am335x:Handle worst case scenario for Errata 1.0.24
From: Steve Kipisz
In Errata 1.0.24, if the board is running at OPP50 and has a warm reset,
the boot ROM sets the frequencies for OPP100. This patch attempts to
drop the frequencies back to OPP50 as soon as possible in the SPL. Then
later the voltages and frequencies up set higher.
Cc: Enric Balletbo i Serra
Cc: Lars Poeschel
Signed-off-by: Steve Kipisz
[trini: Adapt to current framework]
Signed-off-by: Tom Rini
---
arch/arm/cpu/armv7/am33xx/board.c|2 +
arch/arm/cpu/armv7/am33xx/clock_am33xx.c | 72 ++
arch/arm/include/asm/arch-am33xx/clocks_am33xx.h |3 +
arch/arm/include/asm/arch-am33xx/sys_proto.h |1 +
board/ti/am335x/board.c | 11
include/configs/pcm051.h |1 +
include/power/tps65217.h |1 +
7 files changed, 67 insertions(+), 24 deletions(-)
diff --git a/arch/arm/cpu/armv7/am33xx/board.c
b/arch/arm/cpu/armv7/am33xx/board.c
index 9356501..03427da 100644
--- a/arch/arm/cpu/armv7/am33xx/board.c
+++ b/arch/arm/cpu/armv7/am33xx/board.c
@@ -158,6 +158,8 @@ int arch_misc_init(void)
*/
__weak void am33xx_spl_board_init(void)
{
+ mpu_pll_config_val(CONFIG_SYS_MPUCLK);
+ core_pll_config(OPP_100);
}
void rtc32k_enable(void)
diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
index 9c4d0b4..ef06814 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c
@@ -50,12 +50,17 @@
/* Core PLL Fdll = 1 GHZ, */
#define COREPLL_M 1000
+#define COREPLL_M_OPP50 50
#define COREPLL_N (OSC-1)
#define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */
#define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */
#define COREPLL_M6 4 /* CORE_CLKOUTM6 = 500 MHZ */
+#define COREPLL_M4_OPP50 1
+#define COREPLL_M5_OPP50 1
+#define COREPLL_M6_OPP50 1
+
/*
* USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
* frequency needs to be set to 960 MHZ. Hence,
@@ -274,12 +279,7 @@ void mpu_pll_config_val(int mpull_m)
;
}
-static void mpu_pll_config(void)
-{
- mpu_pll_config_val(CONFIG_SYS_MPUCLK);
-}
-
-static void core_pll_config(void)
+void core_pll_config(int opp)
{
u32 clkmode, clksel, div_m4, div_m5, div_m6;
@@ -293,29 +293,53 @@ static void core_pll_config(void)
writel(PLL_BYPASS_MODE, &cmwkup->clkmoddpllcore);
while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS)
- ;
+ ;
+ if (opp == OPP_50) {
+ clksel = clksel & (~CLK_SEL_MASK);
+ clksel = clksel | ((COREPLL_M_OPP50 << CLK_SEL_SHIFT)
+ | COREPLL_N);
+ writel(clksel, &cmwkup->clkseldpllcore);
- clksel = clksel & (~CLK_SEL_MASK);
- clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N);
- writel(clksel, &cmwkup->clkseldpllcore);
+ div_m4 = div_m4 & ~CLK_DIV_MASK;
+ div_m4 = div_m4 | COREPLL_M4_OPP50;
+ writel(div_m4, &cmwkup->divm4dpllcore);
- div_m4 = div_m4 & ~CLK_DIV_MASK;
- div_m4 = div_m4 | COREPLL_M4;
- writel(div_m4, &cmwkup->divm4dpllcore);
+ div_m5 = div_m5 & ~CLK_DIV_MASK;
+ div_m5 = div_m5 | COREPLL_M5_OPP50;
+ writel(div_m5, &cmwkup->divm5dpllcore);
- div_m5 = div_m5 & ~CLK_DIV_MASK;
- div_m5 = div_m5 | COREPLL_M5;
- writel(div_m5, &cmwkup->divm5dpllcore);
+ div_m6 = div_m6 & ~CLK_DIV_MASK;
+ div_m6 = div_m6 | COREPLL_M6_OPP50;
+ writel(div_m6, &cmwkup->divm6dpllcore);
- div_m6 = div_m6 & ~CLK_DIV_MASK;
- div_m6 = div_m6 | COREPLL_M6;
- writel(div_m6, &cmwkup->divm6dpllcore);
+ clkmode = clkmode | CLK_MODE_SEL;
+ writel(clkmode, &cmwkup->clkmoddpllcore);
- clkmode = clkmode | CLK_MODE_SEL;
- writel(clkmode, &cmwkup->clkmoddpllcore);
+ while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK)
+ ;
+ } else {
+ clksel = clksel & (~CLK_SEL_MASK);
+ clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N);
+ writel(clksel, &cmwkup->clkseldpllcore);
+
+ div_m4 = div_m4 & ~CLK_DIV_MASK;
+ div_m4 = div_m4 | COREPLL_M4;
+ writel(div_m4, &cmwkup->divm4dpllcore);
+
+ div_m5 = div_m5 & ~CLK_DIV_MASK;
+ div_m5 = div_m5 | COREPLL_M5;
+ writel(div_m5, &cmwkup->divm5dpllcore);
+
+ div_m6 = div_m6 & ~CLK_DIV_MASK;
+ div_m6 = div_m6 | COREPLL_M6;
+ writel(div_m6, &cmwkup->divm6dpllcore);
+
+ clkmode = clkmode | CLK_MODE_SEL;
+ writel(clkmode, &cmwkup->clkmoddpllcore);
- while (readl(&cmwkup->idlestdpllcor
