After wakeup from deep sleep, Clear EPU registers as early as possible
to prevent from possible issue. It's also safe to clear at normal boot.
Signed-off-by: Chenhui Zhao chenhui.z...@freescale.com
---
arch/arm/cpu/armv7/ls102xa/Makefile|1 +
arch/arm/cpu/armv7/ls102xa/cpu.c | 16 +++
arch/arm/cpu/armv7/ls102xa/fsl_epu.c | 57 +++
arch/arm/cpu/armv7/ls102xa/fsl_epu.h | 68
arch/arm/include/asm/arch-ls102xa/config.h |1 +
5 files changed, 143 insertions(+), 0 deletions(-)
create mode 100644 arch/arm/cpu/armv7/ls102xa/fsl_epu.c
create mode 100644 arch/arm/cpu/armv7/ls102xa/fsl_epu.h
diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile
b/arch/arm/cpu/armv7/ls102xa/Makefile
index d82ce8d..ae4f25d 100644
--- a/arch/arm/cpu/armv7/ls102xa/Makefile
+++ b/arch/arm/cpu/armv7/ls102xa/Makefile
@@ -7,6 +7,7 @@
obj-y += cpu.o
obj-y += clock.o
obj-y += timer.o
+obj-y += fsl_epu.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o
obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index b7dde45..fae6c68 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -12,6 +12,8 @@
#include netdev.h
#include fsl_esdhc.h
+#include fsl_epu.h
+
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_DISPLAY_CPUINFO)
@@ -101,3 +103,17 @@ int cpu_eth_init(bd_t *bis)
return 0;
}
+
+int arch_cpu_init(void)
+{
+ void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
+
+ /*
+* After wakeup from deep sleep, Clear EPU registers
+* as early as possible to prevent from possible issue.
+* It's also safe to clear at normal boot.
+*/
+ fsl_epu_clean(epu_base);
+
+ return 0;
+}
diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_epu.c
b/arch/arm/cpu/armv7/ls102xa/fsl_epu.c
new file mode 100644
index 000..6212640
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/fsl_epu.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include common.h
+#include asm/io.h
+
+#include fsl_epu.h
+
+/**
+ * fsl_epu_clean - Clear EPU registers
+ */
+void fsl_epu_clean(void *epu_base)
+{
+ u32 offset;
+
+ /* follow the exact sequence to clear the registers */
+ /* Clear EPACRn */
+ for (offset = EPACR0; offset = EPACR15; offset += EPACR_STRIDE)
+ out_be32(epu_base + offset, 0);
+
+ /* Clear EPEVTCRn */
+ for (offset = EPEVTCR0; offset = EPEVTCR9; offset += EPEVTCR_STRIDE)
+ out_be32(epu_base + offset, 0);
+
+ /* Clear EPGCR */
+ out_be32(epu_base + EPGCR, 0);
+
+ /* Clear EPSMCRn */
+ for (offset = EPSMCR0; offset = EPSMCR15; offset += EPSMCR_STRIDE)
+ out_be32(epu_base + offset, 0);
+
+ /* Clear EPCCRn */
+ for (offset = EPCCR0; offset = EPCCR31; offset += EPCCR_STRIDE)
+ out_be32(epu_base + offset, 0);
+
+ /* Clear EPCMPRn */
+ for (offset = EPCMPR0; offset = EPCMPR31; offset += EPCMPR_STRIDE)
+ out_be32(epu_base + offset, 0);
+
+ /* Clear EPCTRn */
+ for (offset = EPCTR0; offset = EPCTR31; offset += EPCTR_STRIDE)
+ out_be32(epu_base + offset, 0);
+
+ /* Clear EPIMCRn */
+ for (offset = EPIMCR0; offset = EPIMCR31; offset += EPIMCR_STRIDE)
+ out_be32(epu_base + offset, 0);
+
+ /* Clear EPXTRIGCRn */
+ out_be32(epu_base + EPXTRIGCR, 0);
+
+ /* Clear EPECRn */
+ for (offset = EPECR0; offset = EPECR15; offset += EPECR_STRIDE)
+ out_be32(epu_base + offset, 0);
+}
diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_epu.h
b/arch/arm/cpu/armv7/ls102xa/fsl_epu.h
new file mode 100644
index 000..d658aad
--- /dev/null
+++ b/arch/arm/cpu/armv7/ls102xa/fsl_epu.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef __FSL_EPU_H
+#define __FSL_EPU_H
+
+#include asm/types.h
+
+#define FSL_STRIDE_4B 4
+#define FSL_STRIDE_8B 8
+
+/* Block offsets */
+#define EPU_BLOCK_OFFSET 0x
+
+/* EPGCR (Event Processor Global Control Register) */
+#define EPGCR 0x000
+
+/* EPEVTCR0-9 (Event Processor EVT Pin Control Registers) */
+#define EPEVTCR0 0x050
+#define EPEVTCR9 0x074
+#define EPEVTCR_STRIDE FSL_STRIDE_4B
+
+/* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
+#define EPXTRIGCR 0x090
+
+/* EPIMCR0-31 (Event Processor Input Mux Control Registers) */
+#define EPIMCR00x100
+#define EPIMCR31 0x17C
+#define EPIMCR_STRIDE FSL_STRIDE_4B
+
+/* EPSMCR0-15 (Event Processor SCU Mux Control Registers) */
+#define EPSMCR00x200
+#define EPSMCR15 0x278
+#define EPSMCR_STRIDE FSL_STRIDE_8B
+
+/* EPECR0-15 (Event Processor Event Control
