Freescale's flash control driver is using architecture specific timer API
i.e. usec2ticks
Replace usec2ticks with get_timer() (generic timer API)
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
---
drivers/mtd/nand/fsl_elbc_nand.c |8
drivers/mtd/nand/fsl_ifc_nand.c | 21 ++---
2 files changed, 14 insertions(+), 15 deletions(-)
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 2f31fc9..58b55cb 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -37,7 +37,6 @@
#define MAX_BANKS 8
#define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */
-#define FCM_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for FCM */
#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
@@ -199,7 +198,8 @@ static int fsl_elbc_run_command(struct mtd_info *mtd)
struct fsl_elbc_mtd *priv = chip-priv;
struct fsl_elbc_ctrl *ctrl = priv-ctrl;
fsl_lbc_t *lbc = ctrl-regs;
- long long end_tick;
+ u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
+ u32 time_start;
u32 ltesr;
/* Setup the FMR[OP] to execute without write protection */
@@ -218,10 +218,10 @@ static int fsl_elbc_run_command(struct mtd_info *mtd)
out_be32(lbc-lsor, priv-bank);
/* wait for FCM complete flag or timeout */
- end_tick = usec2ticks(FCM_TIMEOUT_MSECS * 1000) + get_ticks();
+ time_start = get_timer(0);
ltesr = 0;
- while (end_tick get_ticks()) {
+ while (get_timer(time_start) timeo) {
ltesr = in_be32(lbc-ltesr);
if (ltesr LTESR_CC)
break;
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
index 8b453cb..6c158f5 100644
--- a/drivers/mtd/nand/fsl_ifc_nand.c
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -26,8 +26,6 @@
#define MAX_BANKS CONFIG_SYS_FSL_IFC_BANK_COUNT
#define ERR_BYTE 0xFF /* Value returned for read bytes
when read failed */
-#define IFC_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for IFC
- NAND Machine */
struct fsl_ifc_ctrl;
@@ -292,7 +290,8 @@ static int fsl_ifc_run_command(struct mtd_info *mtd)
struct fsl_ifc_mtd *priv = chip-priv;
struct fsl_ifc_ctrl *ctrl = priv-ctrl;
struct fsl_ifc *ifc = ctrl-regs;
- long long end_tick;
+ u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
+ u32 time_start;
u32 eccstat[4];
int i;
@@ -304,9 +303,9 @@ static int fsl_ifc_run_command(struct mtd_info *mtd)
IFC_NAND_SEQ_STRT_FIR_STRT);
/* wait for NAND Machine complete flag or timeout */
- end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
+ time_start = get_timer(0);
- while (end_tick get_ticks()) {
+ while (get_timer(time_start) timeo) {
ctrl-status = ifc_in32(ifc-ifc_nand.nand_evter_stat);
if (ctrl-status IFC_NAND_EVTER_STAT_OPC)
@@ -810,15 +809,16 @@ static int fsl_ifc_sram_init(uint32_t ver)
struct fsl_ifc *ifc = ifc_ctrl-regs;
uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0;
uint32_t ncfgr = 0;
- long long end_tick;
+ u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
+ u32 time_start;
if (ver FSL_IFC_V1_1_0) {
ncfgr = ifc_in32(ifc-ifc_nand.ncfgr);
ifc_out32(ifc-ifc_nand.ncfgr, ncfgr | IFC_NAND_SRAM_INIT_EN);
/* wait for SRAM_INIT bit to be clear or timeout */
- end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
- while (end_tick get_ticks()) {
+ time_start = get_timer(0);
+ while (get_timer(time_start) timeo) {
ifc_ctrl-status =
ifc_in32(ifc-ifc_nand.nand_evter_stat);
@@ -861,10 +861,9 @@ static int fsl_ifc_sram_init(uint32_t ver)
/* start read seq */
ifc_out32(ifc-ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
- /* wait for NAND Machine complete flag or timeout */
- end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks();
+ time_start = get_timer(0);
- while (end_tick get_ticks()) {
+ while (get_timer(time_start) timeo) {
ifc_ctrl-status = ifc_in32(ifc-ifc_nand.nand_evter_stat);
if (ifc_ctrl-status IFC_NAND_EVTER_STAT_OPC)
--
1.7.9.5
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