Re: [U-Boot] [PATCH] powerpc/esdhc: Map register for eSDHC host controller 3.0
On Tue, 2013-10-29 at 11:48 +0800, Haijun Zhang wrote: eSDHC host controller has new register to support SD Spec 3.0. And the according host controller version was Freescale eSDHC Version 3.0. Add some new register and it simple description. Signed-off-by: Haijun Zhang haijun.zh...@freescale.com --- drivers/mmc/fsl_esdhc.c | 62 + 1 file changed, 37 insertions(+), 25 deletions(-) By adding a register in the same patch as you add descriptions, you make it hard to see what register you added. -Scott ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/esdhc: Map register for eSDHC host controller 3.0
I'll split it to two patches. Thanks. δΊ 2013/10/30 1:54, Scott Wood ει: On Tue, 2013-10-29 at 11:48 +0800, Haijun Zhang wrote: eSDHC host controller has new register to support SD Spec 3.0. And the according host controller version was Freescale eSDHC Version 3.0. Add some new register and it simple description. Signed-off-by: Haijun Zhang haijun.zh...@freescale.com --- drivers/mmc/fsl_esdhc.c | 62 + 1 file changed, 37 insertions(+), 25 deletions(-) By adding a register in the same patch as you add descriptions, you make it hard to see what register you added. -Scott -- Thanks Regards Haijun. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/esdhc: Map register for eSDHC host controller 3.0
eSDHC host controller has new register to support SD Spec 3.0.
And the according host controller version was Freescale eSDHC
Version 3.0. Add some new register and it simple description.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
drivers/mmc/fsl_esdhc.c | 62 +
1 file changed, 37 insertions(+), 25 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 589288b..f3d4b90 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -40,31 +40,43 @@
DECLARE_GLOBAL_DATA_PTR;
struct fsl_esdhc {
- uintdsaddr;
- uintblkattr;
- uintcmdarg;
- uintxfertyp;
- uintcmdrsp0;
- uintcmdrsp1;
- uintcmdrsp2;
- uintcmdrsp3;
- uintdatport;
- uintprsstat;
- uintproctl;
- uintsysctl;
- uintirqstat;
- uintirqstaten;
- uintirqsigen;
- uintautoc12err;
- uinthostcapblt;
- uintwml;
- uintmixctrl;
- charreserved1[4];
- uintfevt;
- charreserved2[168];
- uinthostver;
- charreserved3[780];
- uintscr;
+ uintdsaddr; /* SDMA system address register */
+ uintblkattr;/* Block attributes register */
+ uintcmdarg; /* Command argument register */
+ uintxfertyp;/* Transfer type register */
+ uintcmdrsp0;/* Command response 0 register */
+ uintcmdrsp1;/* Command response 1 register */
+ uintcmdrsp2;/* Command response 2 register */
+ uintcmdrsp3;/* Command response 3 register */
+ uintdatport;/* Buffer data port register */
+ uintprsstat;/* Present state register */
+ uintproctl; /* Protocol control register */
+ uintsysctl; /* System Control Register */
+ uintirqstat;/* Interrupt status register */
+ uintirqstaten; /* Interrupt status enable register */
+ uintirqsigen; /* Interrupt signal enable register */
+ uintautoc12err; /* Auto CMD error status register */
+ uinthostcapblt; /* Host controller capabilities register */
+ uintwml;/* Watermark level register */
+ uintmixctrl;/* For USDHC */
+ charreserved1[4]; /* reserved */
+ uintfevt; /* Force event register */
+ uintadmaes; /* ADMA error status register */
+ uintadsaddr;/* ADMA system address register */
+ charreserved2[160]; /* reserved */
+ uinthostver;/* Host controller version register */
+ charreserved3[4]; /* reserved */
+ uintdmaerraddr; /* DMA error address register */
+ charreserved4[4]; /* reserved */
+ uintdmaerrattr; /* DMA error attribute register */
+ charreserved5[4]; /* reserved */
+ uinthostcapblt2;/* Host controller capabilities register 2 */
+ charreserved6[8]; /* reserved */
+ uinttcr;/* Tuning control register */
+ charreserved7[28]; /* reserved */
+ uintsddirctl; /* SD direction control register */
+ charreserved8[712]; /* reserved */
+ uintscr;/* eSDHC control register */
};
/* Return the XFERTYP flags for a given command and data packet */
--
1.8.4
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[U-Boot] [PATCH] powerpc/esdhc: Map register for eSDHC host controller 3.0
eSDHC host controller has new register to support SD Spec 3.0.
And the according host controller version was Freescale eSDHC
Version 3.0. Add some new register and it simple description.
Signed-off-by: Haijun Zhang haijun.zh...@freescale.com
---
drivers/mmc/fsl_esdhc.c | 62 +
1 file changed, 37 insertions(+), 25 deletions(-)
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 589288b..f3d4b90 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -40,31 +40,43 @@
DECLARE_GLOBAL_DATA_PTR;
struct fsl_esdhc {
- uintdsaddr;
- uintblkattr;
- uintcmdarg;
- uintxfertyp;
- uintcmdrsp0;
- uintcmdrsp1;
- uintcmdrsp2;
- uintcmdrsp3;
- uintdatport;
- uintprsstat;
- uintproctl;
- uintsysctl;
- uintirqstat;
- uintirqstaten;
- uintirqsigen;
- uintautoc12err;
- uinthostcapblt;
- uintwml;
- uintmixctrl;
- charreserved1[4];
- uintfevt;
- charreserved2[168];
- uinthostver;
- charreserved3[780];
- uintscr;
+ uintdsaddr; /* SDMA system address register */
+ uintblkattr;/* Block attributes register */
+ uintcmdarg; /* Command argument register */
+ uintxfertyp;/* Transfer type register */
+ uintcmdrsp0;/* Command response 0 register */
+ uintcmdrsp1;/* Command response 1 register */
+ uintcmdrsp2;/* Command response 2 register */
+ uintcmdrsp3;/* Command response 3 register */
+ uintdatport;/* Buffer data port register */
+ uintprsstat;/* Present state register */
+ uintproctl; /* Protocol control register */
+ uintsysctl; /* System Control Register */
+ uintirqstat;/* Interrupt status register */
+ uintirqstaten; /* Interrupt status enable register */
+ uintirqsigen; /* Interrupt signal enable register */
+ uintautoc12err; /* Auto CMD error status register */
+ uinthostcapblt; /* Host controller capabilities register */
+ uintwml;/* Watermark level register */
+ uintmixctrl;/* For USDHC */
+ charreserved1[4]; /* reserved */
+ uintfevt; /* Force event register */
+ uintadmaes; /* ADMA error status register */
+ uintadsaddr;/* ADMA system address register */
+ charreserved2[160]; /* reserved */
+ uinthostver;/* Host controller version register */
+ charreserved3[4]; /* reserved */
+ uintdmaerraddr; /* DMA error address register */
+ charreserved4[4]; /* reserved */
+ uintdmaerrattr; /* DMA error attribute register */
+ charreserved5[4]; /* reserved */
+ uinthostcapblt2;/* Host controller capabilities register 2 */
+ charreserved6[8]; /* reserved */
+ uinttcr;/* Tuning control register */
+ charreserved7[28]; /* reserved */
+ uintsddirctl; /* SD direction control register */
+ charreserved8[712]; /* reserved */
+ uintscr;/* eSDHC control register */
};
/* Return the XFERTYP flags for a given command and data packet */
--
1.8.4
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