[U-Boot] [PATCH] rockchip: clk: rk3188: update dpll settings to make EMAC work

2018-02-26 Thread Alexander Kochetkov 
The patch set dpll settings for 300MHz to values used by binary
blob[1]. With new values dpll still generate 300MHz clock, but
EMAC work. Probably with new values dpll generate more stable clock.

dpll on rk3188 provide clocks to DDR and EMAC. With current
dpll settings EMAC doesn't work on radxa rock. EMAC sends packets
to network, but it doesn't receive anything. ifconfig shows a lot
of framing errors.

[1] https://github.com/linux-rockchip/u-boot-rockchip/blob/u-boot-rk3288/
tools/rk_tools/3188_LPDDR2_300MHz_DDR3_300MHz_20130830.bin

Signed-off-by: Alexander Kochetkov 
---
 drivers/clk/rockchip/clk_rk3188.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk_rk3188.c 
b/drivers/clk/rockchip/clk_rk3188.c
index 6451c95..f674e60 100644
--- a/drivers/clk/rockchip/clk_rk3188.c
+++ b/drivers/clk/rockchip/clk_rk3188.c
@@ -123,7 +123,7 @@ static int rkclk_configure_ddr(struct rk3188_cru *cru, 
struct rk3188_grf *grf,
   unsigned int hz, bool has_bwadj)
 {
static const struct pll_div dpll_cfg[] = {
-   {.nf = 25, .nr = 2, .no = 1},
+   {.nf = 75, .nr = 1, .no = 6},
{.nf = 400, .nr = 9, .no = 2},
{.nf = 500, .nr = 9, .no = 2},
{.nf = 100, .nr = 3, .no = 1},
-- 
1.7.9.5

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Re: [U-Boot] [PATCH] rockchip: clk: rk3188: update dpll settings to make EMAC work

2018-02-26 Thread Dr. Philipp Tomsich 
Kever,

please review.

Thanks,
Philipp.

> On 26 Feb 2018, at 12:27, Alexander Kochetkov  wrote:
> 
> The patch set dpll settings for 300MHz to values used by binary
> blob[1]. With new values dpll still generate 300MHz clock, but
> EMAC work. Probably with new values dpll generate more stable clock.
> 
> dpll on rk3188 provide clocks to DDR and EMAC. With current
> dpll settings EMAC doesn't work on radxa rock. EMAC sends packets
> to network, but it doesn't receive anything. ifconfig shows a lot
> of framing errors.
> 
> [1] https://github.com/linux-rockchip/u-boot-rockchip/blob/u-boot-rk3288/
>tools/rk_tools/3188_LPDDR2_300MHz_DDR3_300MHz_20130830.bin
> 
> Signed-off-by: Alexander Kochetkov 
> ---
> drivers/clk/rockchip/clk_rk3188.c |2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/rockchip/clk_rk3188.c 
> b/drivers/clk/rockchip/clk_rk3188.c
> index 6451c95..f674e60 100644
> --- a/drivers/clk/rockchip/clk_rk3188.c
> +++ b/drivers/clk/rockchip/clk_rk3188.c
> @@ -123,7 +123,7 @@ static int rkclk_configure_ddr(struct rk3188_cru *cru, 
> struct rk3188_grf *grf,
>  unsigned int hz, bool has_bwadj)
> {
>   static const struct pll_div dpll_cfg[] = {
> - {.nf = 25, .nr = 2, .no = 1},
> + {.nf = 75, .nr = 1, .no = 6},
>   {.nf = 400, .nr = 9, .no = 2},
>   {.nf = 500, .nr = 9, .no = 2},
>   {.nf = 100, .nr = 3, .no = 1},
> -- 
> 1.7.9.5
> 

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Re: [U-Boot] [PATCH] rockchip: clk: rk3188: update dpll settings to make EMAC work

2018-03-27 Thread Kever Yang 
Hi Philipp,

    Sorry for reply so late.
On 02/26/2018 07:28 PM, Dr. Philipp Tomsich wrote:
> Kever,
>
> please review.
>
> Thanks,
> Philipp.
>
>> On 26 Feb 2018, at 12:27, Alexander Kochetkov  wrote:
>>
>> The patch set dpll settings for 300MHz to values used by binary
>> blob[1]. With new values dpll still generate 300MHz clock, but
>> EMAC work. Probably with new values dpll generate more stable clock.
>>
>> dpll on rk3188 provide clocks to DDR and EMAC. With current
>> dpll settings EMAC doesn't work on radxa rock. EMAC sends packets
>> to network, but it doesn't receive anything. ifconfig shows a lot
>> of framing errors.
>>
>> [1] https://github.com/linux-rockchip/u-boot-rockchip/blob/u-boot-rk3288/
>>tools/rk_tools/3188_LPDDR2_300MHz_DDR3_300MHz_20130830.bin
>>
>> Signed-off-by: Alexander Kochetkov 
>> ---
>> drivers/clk/rockchip/clk_rk3188.c |2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/rockchip/clk_rk3188.c 
>> b/drivers/clk/rockchip/clk_rk3188.c
>> index 6451c95..f674e60 100644
>> --- a/drivers/clk/rockchip/clk_rk3188.c
>> +++ b/drivers/clk/rockchip/clk_rk3188.c
>> @@ -123,7 +123,7 @@ static int rkclk_configure_ddr(struct rk3188_cru *cru, 
>> struct rk3188_grf *grf,
>> unsigned int hz, bool has_bwadj)
>> {
>>  static const struct pll_div dpll_cfg[] = {
>> -{.nf = 25, .nr = 2, .no = 1},
>> +{.nf = 75, .nr = 1, .no = 6},

Rockchip always prefer to use nr=1 even if we can only get a frequency
close to target frequency,
because this setting can get smaller jitter. Some of IP like jitter may
very sensitive to this setting.

Reviewed-by: Kever Yang 

Thanks,
- Kever
>>  {.nf = 400, .nr = 9, .no = 2},
>>  {.nf = 500, .nr = 9, .no = 2},
>>  {.nf = 100, .nr = 3, .no = 1},
>> -- 
>> 1.7.9.5
>>
>


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