[U-Boot] [PATCH] vf610twr: Tune DDR initialization settings
Removed settings in unsupported register fields. They didn’t do anything, and in most cases, were not documented in the reference manual. Changed register settings to comply with JEDEC required values. Changed timing parameters because they included full clock periods that were doing nothing. Signed-off-by: Anthony Felice --- arch/arm/include/asm/arch-vf610/imx-regs.h| 50 +++--- arch/arm/include/asm/arch-vf610/iomux-vf610.h | 44 +++-- arch/arm/include/asm/imx-common/iomux-v3.h| 2 + board/freescale/vf610twr/vf610twr.c | 93 +-- 4 files changed, 128 insertions(+), 61 deletions(-) diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index c2f9761..a11b419 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -100,9 +100,11 @@ /* DDRMC */ #define DDRMC_PHY_DQ_TIMING0x2613 #define DDRMC_PHY_DQS_TIMING 0x2615 -#define DDRMC_PHY_CTRL 0x01210080 +#define DDRMC_PHY_CTRL 0x0021 #define DDRMC_PHY_MASTER_CTRL 0x0001012a -#define DDRMC_PHY_SLAVE_CTRL 0x00012020 +#define DDRMC_PHY_SLAVE_CTRL 0x2000 +#define DDRMC_PHY_OFF 0x +#define DDRMC_PHY_PROC_PAD_ODT 0x00010101 #define DDRMC_PHY50_DDR3_MODE (1 << 12) #define DDRMC_PHY50_EN_SW_HALF_CYCLE (1 << 8) @@ -135,7 +137,7 @@ #define DDRMC_CR21_CCMAP_EN1 #define DDRMC_CR22_TDAL(v) (((v) & 0x3f) << 16) #define DDRMC_CR23_BSTLEN(v) (((v) & 0x7) << 24) -#define DDRMC_CR23_TDLL(v) ((v) & 0xff) +#define DDRMC_CR23_TDLL(v) ((v) & 0x) #define DDRMC_CR24_TRP_AB(v) ((v) & 0x1f) #define DDRMC_CR25_TREF_EN (1 << 16) #define DDRMC_CR26_TREF(v) (((v) & 0x) << 16) @@ -148,7 +150,7 @@ #define DDRMC_CR33_EN_QK_SREF (1 << 16) #define DDRMC_CR34_CKSRX(v)(((v) & 0xf) << 16) #define DDRMC_CR34_CKSRE(v)(((v) & 0xf) << 8) -#define DDRMC_CR38_FREQ_CHG_EN (1 << 8) +#define DDRMC_CR38_FREQ_CHG_EN(v) (((v) & 0x1) << 8) #define DDRMC_CR39_PHY_INI_COM(v) (((v) & 0x) << 16) #define DDRMC_CR39_PHY_INI_STA(v) (((v) & 0xff) << 8) #define DDRMC_CR39_FRQ_CH_DLLOFF(v)((v) & 0x3) @@ -160,7 +162,7 @@ #define DDRMC_CR67_ZQCS(v) ((v) & 0xfff) #define DDRMC_CR69_ZQ_ON_SREF_EX(v)(((v) & 0xf) << 8) #define DDRMC_CR70_REF_PER_ZQ(v) (v) -#define DDRMC_CR72_ZQCS_ROTATE (1 << 24) +#define DDRMC_CR72_ZQCS_ROTATE(v) (((v) & 0x1) << 24) #define DDRMC_CR73_APREBIT(v) (((v) & 0xf) << 24) #define DDRMC_CR73_COL_DIFF(v) (((v) & 0x7) << 16) #define DDRMC_CR73_ROW_DIFF(v) (((v) & 0x3) << 8) @@ -179,9 +181,10 @@ #define DDRMC_CR77_CS_MAP (1 << 24) #define DDRMC_CR77_DI_RD_INTLEAVE (1 << 8) #define DDRMC_CR77_SWAP_EN 1 +#define DDRMC_CR78_Q_FULLNESS(v) (((v) & 0x7) << 24) #define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf) -#define DDRMC_CR79_CTLUPD_AREF (1 << 24) -#define DDRMC_CR82_INT_MASK0x1fff +#define DDRMC_CR79_CTLUPD_AREF(v) (((v) & 0x1) << 24) +#define DDRMC_CR82_INT_MASK0x1000 #define DDRMC_CR87_ODT_WR_MAPCS0 (1 << 24) #define DDRMC_CR87_ODT_RD_MAPCS0 (1 << 16) #define DDRMC_CR88_TODTL_CMD(v)(((v) & 0x1f) << 16) @@ -189,9 +192,17 @@ #define DDRMC_CR91_R2W_SMCSDL(v) (((v) & 0x7) << 16) #define DDRMC_CR96_WLMRD(v)(((v) & 0x3f) << 8) #define DDRMC_CR96_WLDQSEN(v) ((v) & 0x3f) +#define DDRMC_CR97_WRLVL_EN(1 << 24) +#define DDRMC_CR98_WRLVL_DL_0 (0) +#define DDRMC_CR99_WRLVL_DL_1 (0) +#define DDRMC_CR102_RDLVL_GT_REGEN (1 << 16) +#define DDRMC_CR102_RDLVL_REG_EN (1 << 8) #define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << 8) +#define DDRMC_CR106_RDLVL_GTDL_0(v)((v) & 0xff) #define DDRMC_
Re: [U-Boot] [PATCH] vf610twr: Tune DDR initialization settings
Hi Anthony, On Wed, 14 May 2014 17:29:48 -0400, Anthony Felice wrote: > Removed settings in unsupported register fields. They didn’t > do anything, and in most cases, were not documented in the > reference manual. > > Changed register settings to comply with JEDEC required values. Is this just a compliance fix, or a bug fix? > Changed timing parameters because they included full clock > periods that were doing nothing. > > Signed-off-by: Anthony Felice Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] vf610twr: Tune DDR initialization settings
Hi Albert, On Mon, 9 Jun 2014 10:11:28 +0200, Albert ARIBAUD wrote: > Hi Anthony, > > On Wed, 14 May 2014 17:29:48 -0400, Anthony Felice > wrote: > > > Removed settings in unsupported register fields. They didn’t > > do anything, and in most cases, were not documented in the > > reference manual. > > > > Changed register settings to comply with JEDEC required values. > > Is this just a compliance fix, or a bug fix? Ping. Amicalement, -- Albert. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] vf610twr: Tune DDR initialization settings
Am 2014-05-14 23:29, schrieb Anthony Felice: > Removed settings in unsupported register fields. They didn’t > do anything, and in most cases, were not documented in the > reference manual. > > Changed register settings to comply with JEDEC required values. > > Changed timing parameters because they included full clock > periods that were doing nothing. > > Signed-off-by: Anthony Felice > --- > arch/arm/include/asm/arch-vf610/imx-regs.h| 50 +++--- > arch/arm/include/asm/arch-vf610/iomux-vf610.h | 44 +++-- > arch/arm/include/asm/imx-common/iomux-v3.h| 2 + > board/freescale/vf610twr/vf610twr.c | 93 > +-- > 4 files changed, 128 insertions(+), 61 deletions(-) > > diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h > b/arch/arm/include/asm/arch-vf610/imx-regs.h > index c2f9761..a11b419 100644 > --- a/arch/arm/include/asm/arch-vf610/imx-regs.h > +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h > @@ -100,9 +100,11 @@ > /* DDRMC */ > #define DDRMC_PHY_DQ_TIMING 0x2613 > #define DDRMC_PHY_DQS_TIMING 0x2615 > -#define DDRMC_PHY_CTRL 0x01210080 > +#define DDRMC_PHY_CTRL 0x0021 > #define DDRMC_PHY_MASTER_CTRL0x0001012a > -#define DDRMC_PHY_SLAVE_CTRL 0x00012020 > +#define DDRMC_PHY_SLAVE_CTRL 0x2000 > +#define DDRMC_PHY_OFF0x > +#define DDRMC_PHY_PROC_PAD_ODT 0x00010101 > > #define DDRMC_PHY50_DDR3_MODE(1 << 12) > #define DDRMC_PHY50_EN_SW_HALF_CYCLE (1 << 8) > @@ -135,7 +137,7 @@ > #define DDRMC_CR21_CCMAP_EN 1 > #define DDRMC_CR22_TDAL(v) (((v) & 0x3f) << 16) > #define DDRMC_CR23_BSTLEN(v) (((v) & 0x7) << 24) > -#define DDRMC_CR23_TDLL(v) ((v) & 0xff) > +#define DDRMC_CR23_TDLL(v) ((v) & 0x) > #define DDRMC_CR24_TRP_AB(v) ((v) & 0x1f) > #define DDRMC_CR25_TREF_EN (1 << 16) > #define DDRMC_CR26_TREF(v) (((v) & 0x) << 16) > @@ -148,7 +150,7 @@ > #define DDRMC_CR33_EN_QK_SREF(1 << 16) > #define DDRMC_CR34_CKSRX(v) (((v) & 0xf) << 16) > #define DDRMC_CR34_CKSRE(v) (((v) & 0xf) << 8) > -#define DDRMC_CR38_FREQ_CHG_EN (1 << 8) > +#define DDRMC_CR38_FREQ_CHG_EN(v)(((v) & 0x1) << 8) > #define DDRMC_CR39_PHY_INI_COM(v)(((v) & 0x) << 16) > #define DDRMC_CR39_PHY_INI_STA(v)(((v) & 0xff) << 8) > #define DDRMC_CR39_FRQ_CH_DLLOFF(v) ((v) & 0x3) > @@ -160,7 +162,7 @@ > #define DDRMC_CR67_ZQCS(v) ((v) & 0xfff) > #define DDRMC_CR69_ZQ_ON_SREF_EX(v) (((v) & 0xf) << 8) > #define DDRMC_CR70_REF_PER_ZQ(v) (v) > -#define DDRMC_CR72_ZQCS_ROTATE (1 << 24) > +#define DDRMC_CR72_ZQCS_ROTATE(v)(((v) & 0x1) << 24) > #define DDRMC_CR73_APREBIT(v)(((v) & 0xf) << > 24) > #define DDRMC_CR73_COL_DIFF(v) (((v) & 0x7) << > 16) > #define DDRMC_CR73_ROW_DIFF(v) (((v) & 0x3) << > 8) > @@ -179,9 +181,10 @@ > #define DDRMC_CR77_CS_MAP(1 << 24) > #define DDRMC_CR77_DI_RD_INTLEAVE(1 << 8) > #define DDRMC_CR77_SWAP_EN 1 > +#define DDRMC_CR78_Q_FULLNESS(v) (((v) & 0x7) << 24) > #define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf) > -#define DDRMC_CR79_CTLUPD_AREF (1 << 24) > -#define DDRMC_CR82_INT_MASK 0x1fff > +#define DDRMC_CR79_CTLUPD_AREF(v)(((v) & 0x1) << 24) > +#define DDRMC_CR82_INT_MASK 0x1000 > #define DDRMC_CR87_ODT_WR_MAPCS0 (1 << 24) > #define DDRMC_CR87_ODT_RD_MAPCS0 (1 << 16) > #define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) > << 16) > @@ -189,9 +192,17 @@ > #define DDRMC_CR91_R2W_SMCSDL(v) (((v) & 0x7) << 16) > #define DDRMC_CR96_WLMRD(v) (((v) & 0x3f) << 8) > #define DDRMC_CR96_WLDQSEN(v)((v) & 0x3f) > +#define DDRMC_CR97_WRLVL_EN (1 << 24) > +#define DDRMC_CR98_WRLVL_DL_0(0) > +#define DDRMC_CR99_WRLVL_DL_1(0) > +#define DDRMC_CR102_RDLVL_GT_REGEN
Re: [U-Boot] [PATCH] vf610twr: Tune DDR initialization settings
Am 2014-07-22 00:42, schrieb Stefan Agner: > Am 2014-05-14 23:29, schrieb Anthony Felice: >> Removed settings in unsupported register fields. They didn’t >> do anything, and in most cases, were not documented in the >> reference manual. >> >> Changed register settings to comply with JEDEC required values. >> >> Changed timing parameters because they included full clock >> periods that were doing nothing. >> >> Signed-off-by: Anthony Felice >> --- >> arch/arm/include/asm/arch-vf610/imx-regs.h| 50 +++--- >> arch/arm/include/asm/arch-vf610/iomux-vf610.h | 44 +++-- >> arch/arm/include/asm/imx-common/iomux-v3.h| 2 + >> board/freescale/vf610twr/vf610twr.c | 93 >> +-- >> 4 files changed, 128 insertions(+), 61 deletions(-) >> >> diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h >> b/arch/arm/include/asm/arch-vf610/imx-regs.h >> index c2f9761..a11b419 100644 >> --- a/arch/arm/include/asm/arch-vf610/imx-regs.h >> +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h >> @@ -100,9 +100,11 @@ >> /* DDRMC */ >> #define DDRMC_PHY_DQ_TIMING 0x2613 >> #define DDRMC_PHY_DQS_TIMING0x2615 >> -#define DDRMC_PHY_CTRL 0x01210080 >> +#define DDRMC_PHY_CTRL 0x0021 >> #define DDRMC_PHY_MASTER_CTRL 0x0001012a >> -#define DDRMC_PHY_SLAVE_CTRL0x00012020 >> +#define DDRMC_PHY_SLAVE_CTRL0x2000 >> +#define DDRMC_PHY_OFF 0x >> +#define DDRMC_PHY_PROC_PAD_ODT 0x00010101 >> >> #define DDRMC_PHY50_DDR3_MODE (1 << 12) >> #define DDRMC_PHY50_EN_SW_HALF_CYCLE(1 << 8) >> @@ -135,7 +137,7 @@ >> #define DDRMC_CR21_CCMAP_EN 1 >> #define DDRMC_CR22_TDAL(v) (((v) & 0x3f) << 16) >> #define DDRMC_CR23_BSTLEN(v)(((v) & 0x7) << >> 24) >> -#define DDRMC_CR23_TDLL(v) ((v) & 0xff) >> +#define DDRMC_CR23_TDLL(v) ((v) & 0x) >> #define DDRMC_CR24_TRP_AB(v)((v) & 0x1f) >> #define DDRMC_CR25_TREF_EN (1 << 16) >> #define DDRMC_CR26_TREF(v) (((v) & 0x) << 16) >> @@ -148,7 +150,7 @@ >> #define DDRMC_CR33_EN_QK_SREF (1 << 16) >> #define DDRMC_CR34_CKSRX(v) (((v) & 0xf) << 16) >> #define DDRMC_CR34_CKSRE(v) (((v) & 0xf) << 8) >> -#define DDRMC_CR38_FREQ_CHG_EN (1 << 8) >> +#define DDRMC_CR38_FREQ_CHG_EN(v) (((v) & 0x1) << 8) >> #define DDRMC_CR39_PHY_INI_COM(v) (((v) & 0x) << 16) >> #define DDRMC_CR39_PHY_INI_STA(v) (((v) & 0xff) << 8) >> #define DDRMC_CR39_FRQ_CH_DLLOFF(v) ((v) & 0x3) >> @@ -160,7 +162,7 @@ >> #define DDRMC_CR67_ZQCS(v) ((v) & 0xfff) >> #define DDRMC_CR69_ZQ_ON_SREF_EX(v) (((v) & 0xf) << 8) >> #define DDRMC_CR70_REF_PER_ZQ(v)(v) >> -#define DDRMC_CR72_ZQCS_ROTATE (1 << 24) >> +#define DDRMC_CR72_ZQCS_ROTATE(v) (((v) & 0x1) << 24) >> #define DDRMC_CR73_APREBIT(v) (((v) & 0xf) << >> 24) >> #define DDRMC_CR73_COL_DIFF(v) (((v) & 0x7) << >> 16) >> #define DDRMC_CR73_ROW_DIFF(v) (((v) & 0x3) << >> 8) >> @@ -179,9 +181,10 @@ >> #define DDRMC_CR77_CS_MAP (1 << 24) >> #define DDRMC_CR77_DI_RD_INTLEAVE (1 << 8) >> #define DDRMC_CR77_SWAP_EN 1 >> +#define DDRMC_CR78_Q_FULLNESS(v)(((v) & 0x7) << 24) >> #define DDRMC_CR78_BUR_ON_FLY_BIT(v)((v) & 0xf) >> -#define DDRMC_CR79_CTLUPD_AREF (1 << 24) >> -#define DDRMC_CR82_INT_MASK 0x1fff >> +#define DDRMC_CR79_CTLUPD_AREF(v) (((v) & 0x1) << 24) >> +#define DDRMC_CR82_INT_MASK 0x1000 >> #define DDRMC_CR87_ODT_WR_MAPCS0(1 << 24) >> #define DDRMC_CR87_ODT_RD_MAPCS0(1 << 16) >> #define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) >> << 16) >> @@ -189,9 +192,17 @@ >> #define DDRMC_CR91_R2W_SMCSDL(v)(((v) & 0x7) << 16) >> #define DDRMC_CR96_WLMRD(v) (((v) & 0x3f) << 8) >> #define DDRMC_CR96_WLDQSEN(v) ((v) & 0x3f) >> +#define DDRMC_CR97_WRLVL_EN (1 << 24) >> +#define DDRMC_CR98_WRLVL_DL_0
Re: [U-Boot] [PATCH] vf610twr: Tune DDR initialization settings
On Thu, Aug 14, 2014 at 6:08 PM, Stefan Agner wrote: > Am 2014-07-22 00:42, schrieb Stefan Agner: > I would like to see this merged since it really fixes a lot of > wrong/undocumented access in the RAM initialization code. It looks like > the original code was copied from some other (full featured) SoC, > whereas the Vybrid is a striped down variant of it. > > I ran that code on Tower and our Vybrid based Colibri VF61, hence you > can add a > Tested-By: Stefan Agner > > As mentioned above, the patch currently does not apply cleanly, but the > merge is trivial. In case you prefer a rebased/updated V2 of it, I can > send one (since Anthony seems not very responsive). I also want this merged. This is a step further in dropping the U-Boot from, for Tower, from meta-fsl-arm. -- Otavio Salvador O.S. Systems http://www.ossystems.com.brhttp://code.ossystems.com.br Mobile: +55 (53) 9981-7854Mobile: +1 (347) 903-9750 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
