Re: [U-Boot] [PATCH] x86: minnowmax: add GPIO mapping support
Hi Simon, On 04/07/2015 07:03 PM, Simon Glass wrote: Hi Gabriel, On 6 April 2015 at 00:10, Gabriel Huau wrote: Hi Simon, On 04/05/2015 11:31 AM, Simon Glass wrote: Hi Gabriel, On 1 April 2015 at 05:20, Gabriel Huau wrote: Hi Simon, On 03/31/2015 07:32 PM, Simon Glass wrote: Hi Gabriel, On 27 February 2015 at 01:52, Bin Meng wrote: Hi Gabriel, On Fri, Feb 27, 2015 at 3:54 PM, gabriel huau wrote: Hi Bin, On 02/26/2015 07:30 PM, Bin Meng wrote: Hi Gabriel, On Thu, Feb 26, 2015 at 12:27 AM, Gabriel Huau wrote: Hi Bin, On 02/24/2015 11:52 PM, Bin Meng wrote: Hi Gabriel, On Mon, Feb 16, 2015 at 5:55 AM, Gabriel Huau wrote: Configure the pinctrl as it required to make some IO controllers working (USB/UART/I2C/...). The idea would be in the next version to modify the pch GPIO driver and configure these pins through the device tree. These modifications are ported from the coreboot project. Signed-off-by: Gabriel Huau --- arch/x86/cpu/baytrail/Makefile| 1 + arch/x86/cpu/baytrail/gpio.c | 206 +++ arch/x86/include/asm/arch-baytrail/gpio.h | 364 ++ arch/x86/include/asm/arch-baytrail/iomap.h| 73 ++ arch/x86/include/asm/arch-baytrail/irq.h | 119 + arch/x86/include/asm/arch-baytrail/irqroute.h | 67 + arch/x86/include/asm/arch-baytrail/pci_devs.h | 144 ++ arch/x86/include/asm/arch-baytrail/pmc.h | 253 ++ board/intel/minnowmax/minnowmax.c | 212 +++ include/configs/minnowmax.h | 11 + 10 files changed, 1450 insertions(+) create mode 100644 arch/x86/cpu/baytrail/gpio.c create mode 100644 arch/x86/include/asm/arch-baytrail/iomap.h create mode 100644 arch/x86/include/asm/arch-baytrail/irq.h create mode 100644 arch/x86/include/asm/arch-baytrail/irqroute.h create mode 100644 arch/x86/include/asm/arch-baytrail/pci_devs.h create mode 100644 arch/x86/include/asm/arch-baytrail/pmc.h [snip] diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index 823e051..738c6fa 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -69,4 +69,15 @@ /* Avoid a warning in the Realtek Ethernet driver */ #define CONFIG_SYS_CACHELINE_SIZE 16 +/* + * Baytrail has 3 GPIOs bank over PCI, there is no + * driver at the moment so let's disable the command + * and the default x86 driver to avoid any collision + * with the GPIO mapping code. + * @TODO: adding a baytrail-gpio driver and configure + * the muxing through the device tree + */ +#undef CONFIG_INTEL_ICH6_GPIO +#undef CONFIG_CMD_GPIO + Why undef these two? The BayTrail SoC does support GPIO banks in the legacy bridge. I might misunderstood the GPIO subsystem but I thought there was 2 banks available through the PCU iLB GPIO controller which contains the SCORE and SSUS (102 / 44 pins). The intel_ich6_gpio has a limitation of 32 GPIOs per bank and I thought it was just a different controller from the Baytrail, but if I can use it to control all the GPIOs + doing the IO mapping, I'll be glad to do it! I checked the BayTrail datasheet. Its GPIO is in the iLB (legacy bridge), which is the same as other IA chipset (Ivybridge, TunnelCreek, Quark). It has 4 banks in core domain and 2 banks in sus domain. So 6 banks in total. You need define 6 gpio nodes in the minnowmax board dts file. You should be able to use the existing gpio driver to configure. Thanks for the clarification! Actually, I saw it today when I was doing some tests and I configured the 6 banks in the devices tree. I also fixed the GPIO base address to 0x48 but I got some issues like the fact I'm reading only 0 from all the registers. Yep, the offset should be 0x48 for BayTrail. The registers are configured to be in the IO Space (0x500), I checked the PCI configuration space to make sure that everything is enabled correctly, but I'm still missing something. I checked the gpio driver codes, and it currently has: /* * Okay, I guess we're looking at the right device. The actual * GPIO registers are in the PCI device's I/O space, starting * at the offset that we just read. Bit 0 indicates that it's * an I/O address, not a memory address, so mask that off. */ gpiobase = tmplong & 0xfffe; This should be changed to gpiobase = tmplong & 0xfffc; as bit1 is the enable bit on BayTrail (Intel changes this GPIO base register again for BayTrail, sigh...) Once I'll be able to use these GPIOs, I will update the entire patch to remove the port from Coreboot as this is not necessary. #endif /* __CONFIG_H */ -- What is the next step with this patch please? It would be good to apply it to with the changes discussed. Sorry, actually I was super busy and wasn't able to work on the minnowb
Re: [U-Boot] [PATCH] x86: minnowmax: add GPIO mapping support
Hi Gabriel, On 6 April 2015 at 00:10, Gabriel Huau wrote: > Hi Simon, > > > On 04/05/2015 11:31 AM, Simon Glass wrote: >> >> Hi Gabriel, >> >> On 1 April 2015 at 05:20, Gabriel Huau wrote: >>> >>> Hi Simon, >>> >>> >>> On 03/31/2015 07:32 PM, Simon Glass wrote: Hi Gabriel, On 27 February 2015 at 01:52, Bin Meng wrote: > > Hi Gabriel, > > On Fri, Feb 27, 2015 at 3:54 PM, gabriel huau > wrote: >> >> Hi Bin, >> >> >> On 02/26/2015 07:30 PM, Bin Meng wrote: >>> >>> Hi Gabriel, >>> >>> On Thu, Feb 26, 2015 at 12:27 AM, Gabriel Huau >>> >>> wrote: Hi Bin, On 02/24/2015 11:52 PM, Bin Meng wrote: > > Hi Gabriel, > > On Mon, Feb 16, 2015 at 5:55 AM, Gabriel Huau > > wrote: >> >> Configure the pinctrl as it required to make some IO controllers >> working (USB/UART/I2C/...). >> The idea would be in the next version to modify the pch GPIO >> driver >> and >> configure these pins through the device tree. >> >> These modifications are ported from the coreboot project. >> >> Signed-off-by: Gabriel Huau >> --- >> arch/x86/cpu/baytrail/Makefile| 1 + >> arch/x86/cpu/baytrail/gpio.c | 206 >> +++ >> arch/x86/include/asm/arch-baytrail/gpio.h | 364 >> ++ >> arch/x86/include/asm/arch-baytrail/iomap.h| 73 ++ >> arch/x86/include/asm/arch-baytrail/irq.h | 119 + >> arch/x86/include/asm/arch-baytrail/irqroute.h | 67 + >> arch/x86/include/asm/arch-baytrail/pci_devs.h | 144 >> ++ >> arch/x86/include/asm/arch-baytrail/pmc.h | 253 >> ++ >> board/intel/minnowmax/minnowmax.c | 212 >> +++ >> include/configs/minnowmax.h | 11 + >> 10 files changed, 1450 insertions(+) >> create mode 100644 arch/x86/cpu/baytrail/gpio.c >> create mode 100644 arch/x86/include/asm/arch-baytrail/iomap.h >> create mode 100644 arch/x86/include/asm/arch-baytrail/irq.h >> create mode 100644 >> arch/x86/include/asm/arch-baytrail/irqroute.h >> create mode 100644 >> arch/x86/include/asm/arch-baytrail/pci_devs.h >> create mode 100644 arch/x86/include/asm/arch-baytrail/pmc.h >> > [snip] > >> diff --git a/include/configs/minnowmax.h >> b/include/configs/minnowmax.h >> index 823e051..738c6fa 100644 >> --- a/include/configs/minnowmax.h >> +++ b/include/configs/minnowmax.h >> @@ -69,4 +69,15 @@ >> /* Avoid a warning in the Realtek Ethernet driver */ >> #define CONFIG_SYS_CACHELINE_SIZE 16 >> >> +/* >> + * Baytrail has 3 GPIOs bank over PCI, there is no >> + * driver at the moment so let's disable the command >> + * and the default x86 driver to avoid any collision >> + * with the GPIO mapping code. >> + * @TODO: adding a baytrail-gpio driver and configure >> + * the muxing through the device tree >> + */ >> +#undef CONFIG_INTEL_ICH6_GPIO >> +#undef CONFIG_CMD_GPIO >> + > > Why undef these two? The BayTrail SoC does support GPIO banks in > the > legacy bridge. I might misunderstood the GPIO subsystem but I thought there was 2 banks available through the PCU iLB GPIO controller which contains the SCORE and SSUS (102 / 44 pins). The intel_ich6_gpio has a limitation of 32 GPIOs per bank and I thought it was just a different controller from the Baytrail, but if I can use it to control all the GPIOs + doing the IO mapping, I'll be glad to do it! >>> >>> I checked the BayTrail datasheet. Its GPIO is in the iLB (legacy >>> bridge), which is the same as other IA chipset (Ivybridge, >>> TunnelCreek, Quark). It has 4 banks in core domain and 2 banks in sus >>> domain. So 6 banks in total. You need define 6 gpio nodes in the >>> minnowmax board dts file. You should be able to use the existing gpio >>> driver to configure. >> >> >> Thanks for the clarification! >> Actually, I saw it today when I was doing some tests and I configured >> the 6 >> banks in the devices tree. I also fixed the GPIO base address to 0x48 >> but I >> got some issues like the fact I'm reading only 0 from all the >> registers. > > Yep, the offset should be 0x48 for BayTrail. > >>>
Re: [U-Boot] [PATCH] x86: minnowmax: add GPIO mapping support
Hi Simon, On 04/05/2015 11:31 AM, Simon Glass wrote: Hi Gabriel, On 1 April 2015 at 05:20, Gabriel Huau wrote: Hi Simon, On 03/31/2015 07:32 PM, Simon Glass wrote: Hi Gabriel, On 27 February 2015 at 01:52, Bin Meng wrote: Hi Gabriel, On Fri, Feb 27, 2015 at 3:54 PM, gabriel huau wrote: Hi Bin, On 02/26/2015 07:30 PM, Bin Meng wrote: Hi Gabriel, On Thu, Feb 26, 2015 at 12:27 AM, Gabriel Huau wrote: Hi Bin, On 02/24/2015 11:52 PM, Bin Meng wrote: Hi Gabriel, On Mon, Feb 16, 2015 at 5:55 AM, Gabriel Huau wrote: Configure the pinctrl as it required to make some IO controllers working (USB/UART/I2C/...). The idea would be in the next version to modify the pch GPIO driver and configure these pins through the device tree. These modifications are ported from the coreboot project. Signed-off-by: Gabriel Huau --- arch/x86/cpu/baytrail/Makefile| 1 + arch/x86/cpu/baytrail/gpio.c | 206 +++ arch/x86/include/asm/arch-baytrail/gpio.h | 364 ++ arch/x86/include/asm/arch-baytrail/iomap.h| 73 ++ arch/x86/include/asm/arch-baytrail/irq.h | 119 + arch/x86/include/asm/arch-baytrail/irqroute.h | 67 + arch/x86/include/asm/arch-baytrail/pci_devs.h | 144 ++ arch/x86/include/asm/arch-baytrail/pmc.h | 253 ++ board/intel/minnowmax/minnowmax.c | 212 +++ include/configs/minnowmax.h | 11 + 10 files changed, 1450 insertions(+) create mode 100644 arch/x86/cpu/baytrail/gpio.c create mode 100644 arch/x86/include/asm/arch-baytrail/iomap.h create mode 100644 arch/x86/include/asm/arch-baytrail/irq.h create mode 100644 arch/x86/include/asm/arch-baytrail/irqroute.h create mode 100644 arch/x86/include/asm/arch-baytrail/pci_devs.h create mode 100644 arch/x86/include/asm/arch-baytrail/pmc.h [snip] diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index 823e051..738c6fa 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -69,4 +69,15 @@ /* Avoid a warning in the Realtek Ethernet driver */ #define CONFIG_SYS_CACHELINE_SIZE 16 +/* + * Baytrail has 3 GPIOs bank over PCI, there is no + * driver at the moment so let's disable the command + * and the default x86 driver to avoid any collision + * with the GPIO mapping code. + * @TODO: adding a baytrail-gpio driver and configure + * the muxing through the device tree + */ +#undef CONFIG_INTEL_ICH6_GPIO +#undef CONFIG_CMD_GPIO + Why undef these two? The BayTrail SoC does support GPIO banks in the legacy bridge. I might misunderstood the GPIO subsystem but I thought there was 2 banks available through the PCU iLB GPIO controller which contains the SCORE and SSUS (102 / 44 pins). The intel_ich6_gpio has a limitation of 32 GPIOs per bank and I thought it was just a different controller from the Baytrail, but if I can use it to control all the GPIOs + doing the IO mapping, I'll be glad to do it! I checked the BayTrail datasheet. Its GPIO is in the iLB (legacy bridge), which is the same as other IA chipset (Ivybridge, TunnelCreek, Quark). It has 4 banks in core domain and 2 banks in sus domain. So 6 banks in total. You need define 6 gpio nodes in the minnowmax board dts file. You should be able to use the existing gpio driver to configure. Thanks for the clarification! Actually, I saw it today when I was doing some tests and I configured the 6 banks in the devices tree. I also fixed the GPIO base address to 0x48 but I got some issues like the fact I'm reading only 0 from all the registers. Yep, the offset should be 0x48 for BayTrail. The registers are configured to be in the IO Space (0x500), I checked the PCI configuration space to make sure that everything is enabled correctly, but I'm still missing something. I checked the gpio driver codes, and it currently has: /* * Okay, I guess we're looking at the right device. The actual * GPIO registers are in the PCI device's I/O space, starting * at the offset that we just read. Bit 0 indicates that it's * an I/O address, not a memory address, so mask that off. */ gpiobase = tmplong & 0xfffe; This should be changed to gpiobase = tmplong & 0xfffc; as bit1 is the enable bit on BayTrail (Intel changes this GPIO base register again for BayTrail, sigh...) Once I'll be able to use these GPIOs, I will update the entire patch to remove the port from Coreboot as this is not necessary. #endif /* __CONFIG_H */ -- What is the next step with this patch please? It would be good to apply it to with the changes discussed. Sorry, actually I was super busy and wasn't able to work on the minnowboard max ... I should have some time this week end. But you can go ahead and drop this patch, I will submit a new one because most of the modific
Re: [U-Boot] [PATCH] x86: minnowmax: add GPIO mapping support
Hi Gabriel, On 1 April 2015 at 05:20, Gabriel Huau wrote: > Hi Simon, > > > On 03/31/2015 07:32 PM, Simon Glass wrote: >> >> Hi Gabriel, >> >> On 27 February 2015 at 01:52, Bin Meng wrote: >>> >>> Hi Gabriel, >>> >>> On Fri, Feb 27, 2015 at 3:54 PM, gabriel huau >>> wrote: Hi Bin, On 02/26/2015 07:30 PM, Bin Meng wrote: > > Hi Gabriel, > > On Thu, Feb 26, 2015 at 12:27 AM, Gabriel Huau > > wrote: >> >> Hi Bin, >> >> >> On 02/24/2015 11:52 PM, Bin Meng wrote: >>> >>> Hi Gabriel, >>> >>> On Mon, Feb 16, 2015 at 5:55 AM, Gabriel Huau >>> >>> wrote: Configure the pinctrl as it required to make some IO controllers working (USB/UART/I2C/...). The idea would be in the next version to modify the pch GPIO driver and configure these pins through the device tree. These modifications are ported from the coreboot project. Signed-off-by: Gabriel Huau --- arch/x86/cpu/baytrail/Makefile| 1 + arch/x86/cpu/baytrail/gpio.c | 206 +++ arch/x86/include/asm/arch-baytrail/gpio.h | 364 ++ arch/x86/include/asm/arch-baytrail/iomap.h| 73 ++ arch/x86/include/asm/arch-baytrail/irq.h | 119 + arch/x86/include/asm/arch-baytrail/irqroute.h | 67 + arch/x86/include/asm/arch-baytrail/pci_devs.h | 144 ++ arch/x86/include/asm/arch-baytrail/pmc.h | 253 ++ board/intel/minnowmax/minnowmax.c | 212 +++ include/configs/minnowmax.h | 11 + 10 files changed, 1450 insertions(+) create mode 100644 arch/x86/cpu/baytrail/gpio.c create mode 100644 arch/x86/include/asm/arch-baytrail/iomap.h create mode 100644 arch/x86/include/asm/arch-baytrail/irq.h create mode 100644 arch/x86/include/asm/arch-baytrail/irqroute.h create mode 100644 arch/x86/include/asm/arch-baytrail/pci_devs.h create mode 100644 arch/x86/include/asm/arch-baytrail/pmc.h >>> [snip] >>> diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index 823e051..738c6fa 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -69,4 +69,15 @@ /* Avoid a warning in the Realtek Ethernet driver */ #define CONFIG_SYS_CACHELINE_SIZE 16 +/* + * Baytrail has 3 GPIOs bank over PCI, there is no + * driver at the moment so let's disable the command + * and the default x86 driver to avoid any collision + * with the GPIO mapping code. + * @TODO: adding a baytrail-gpio driver and configure + * the muxing through the device tree + */ +#undef CONFIG_INTEL_ICH6_GPIO +#undef CONFIG_CMD_GPIO + >>> >>> Why undef these two? The BayTrail SoC does support GPIO banks in the >>> legacy bridge. >> >> I might misunderstood the GPIO subsystem but I thought there was 2 >> banks >> available through the PCU iLB GPIO controller which contains the SCORE >> and >> SSUS (102 / 44 pins). >> The intel_ich6_gpio has a limitation of 32 GPIOs per bank and I >> thought >> it >> was just a different controller from the Baytrail, but if I can use it >> to >> control all the GPIOs + doing the IO mapping, I'll be glad to do it! > > I checked the BayTrail datasheet. Its GPIO is in the iLB (legacy > bridge), which is the same as other IA chipset (Ivybridge, > TunnelCreek, Quark). It has 4 banks in core domain and 2 banks in sus > domain. So 6 banks in total. You need define 6 gpio nodes in the > minnowmax board dts file. You should be able to use the existing gpio > driver to configure. Thanks for the clarification! Actually, I saw it today when I was doing some tests and I configured the 6 banks in the devices tree. I also fixed the GPIO base address to 0x48 but I got some issues like the fact I'm reading only 0 from all the registers. >>> >>> Yep, the offset should be 0x48 for BayTrail. >>> The registers are configured to be in the IO Space (0x500), I checked the PCI configuration space to make sure that everything is enabled correctly, but I'm still missing something. >>> >>> I checked the gpio driver codes, and it currently has: >>> >>> /* >>> * Okay, I guess we're looking at the right device. The actual >>> * GPIO registers are in the PCI device's I/O space, starting >>> * at the offset that we just
Re: [U-Boot] [PATCH] x86: minnowmax: add GPIO mapping support
Hi Simon, On 03/31/2015 07:32 PM, Simon Glass wrote: Hi Gabriel, On 27 February 2015 at 01:52, Bin Meng wrote: Hi Gabriel, On Fri, Feb 27, 2015 at 3:54 PM, gabriel huau wrote: Hi Bin, On 02/26/2015 07:30 PM, Bin Meng wrote: Hi Gabriel, On Thu, Feb 26, 2015 at 12:27 AM, Gabriel Huau wrote: Hi Bin, On 02/24/2015 11:52 PM, Bin Meng wrote: Hi Gabriel, On Mon, Feb 16, 2015 at 5:55 AM, Gabriel Huau wrote: Configure the pinctrl as it required to make some IO controllers working (USB/UART/I2C/...). The idea would be in the next version to modify the pch GPIO driver and configure these pins through the device tree. These modifications are ported from the coreboot project. Signed-off-by: Gabriel Huau --- arch/x86/cpu/baytrail/Makefile| 1 + arch/x86/cpu/baytrail/gpio.c | 206 +++ arch/x86/include/asm/arch-baytrail/gpio.h | 364 ++ arch/x86/include/asm/arch-baytrail/iomap.h| 73 ++ arch/x86/include/asm/arch-baytrail/irq.h | 119 + arch/x86/include/asm/arch-baytrail/irqroute.h | 67 + arch/x86/include/asm/arch-baytrail/pci_devs.h | 144 ++ arch/x86/include/asm/arch-baytrail/pmc.h | 253 ++ board/intel/minnowmax/minnowmax.c | 212 +++ include/configs/minnowmax.h | 11 + 10 files changed, 1450 insertions(+) create mode 100644 arch/x86/cpu/baytrail/gpio.c create mode 100644 arch/x86/include/asm/arch-baytrail/iomap.h create mode 100644 arch/x86/include/asm/arch-baytrail/irq.h create mode 100644 arch/x86/include/asm/arch-baytrail/irqroute.h create mode 100644 arch/x86/include/asm/arch-baytrail/pci_devs.h create mode 100644 arch/x86/include/asm/arch-baytrail/pmc.h [snip] diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index 823e051..738c6fa 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -69,4 +69,15 @@ /* Avoid a warning in the Realtek Ethernet driver */ #define CONFIG_SYS_CACHELINE_SIZE 16 +/* + * Baytrail has 3 GPIOs bank over PCI, there is no + * driver at the moment so let's disable the command + * and the default x86 driver to avoid any collision + * with the GPIO mapping code. + * @TODO: adding a baytrail-gpio driver and configure + * the muxing through the device tree + */ +#undef CONFIG_INTEL_ICH6_GPIO +#undef CONFIG_CMD_GPIO + Why undef these two? The BayTrail SoC does support GPIO banks in the legacy bridge. I might misunderstood the GPIO subsystem but I thought there was 2 banks available through the PCU iLB GPIO controller which contains the SCORE and SSUS (102 / 44 pins). The intel_ich6_gpio has a limitation of 32 GPIOs per bank and I thought it was just a different controller from the Baytrail, but if I can use it to control all the GPIOs + doing the IO mapping, I'll be glad to do it! I checked the BayTrail datasheet. Its GPIO is in the iLB (legacy bridge), which is the same as other IA chipset (Ivybridge, TunnelCreek, Quark). It has 4 banks in core domain and 2 banks in sus domain. So 6 banks in total. You need define 6 gpio nodes in the minnowmax board dts file. You should be able to use the existing gpio driver to configure. Thanks for the clarification! Actually, I saw it today when I was doing some tests and I configured the 6 banks in the devices tree. I also fixed the GPIO base address to 0x48 but I got some issues like the fact I'm reading only 0 from all the registers. Yep, the offset should be 0x48 for BayTrail. The registers are configured to be in the IO Space (0x500), I checked the PCI configuration space to make sure that everything is enabled correctly, but I'm still missing something. I checked the gpio driver codes, and it currently has: /* * Okay, I guess we're looking at the right device. The actual * GPIO registers are in the PCI device's I/O space, starting * at the offset that we just read. Bit 0 indicates that it's * an I/O address, not a memory address, so mask that off. */ gpiobase = tmplong & 0xfffe; This should be changed to gpiobase = tmplong & 0xfffc; as bit1 is the enable bit on BayTrail (Intel changes this GPIO base register again for BayTrail, sigh...) Once I'll be able to use these GPIOs, I will update the entire patch to remove the port from Coreboot as this is not necessary. #endif /* __CONFIG_H */ -- What is the next step with this patch please? It would be good to apply it to with the changes discussed. Sorry, actually I was super busy and wasn't able to work on the minnowboard max ... I should have some time this week end. But you can go ahead and drop this patch, I will submit a new one because most of the modification are actually not needed, we can use the generic pch_gpio driver already present in u-boot with some modification/fix. My only problem
Re: [U-Boot] [PATCH] x86: minnowmax: add GPIO mapping support
Hi Gabriel, On 27 February 2015 at 01:52, Bin Meng wrote: > Hi Gabriel, > > On Fri, Feb 27, 2015 at 3:54 PM, gabriel huau wrote: >> Hi Bin, >> >> >> On 02/26/2015 07:30 PM, Bin Meng wrote: >>> >>> Hi Gabriel, >>> >>> On Thu, Feb 26, 2015 at 12:27 AM, Gabriel Huau >>> wrote: Hi Bin, On 02/24/2015 11:52 PM, Bin Meng wrote: > > Hi Gabriel, > > On Mon, Feb 16, 2015 at 5:55 AM, Gabriel Huau > wrote: >> >> Configure the pinctrl as it required to make some IO controllers >> working (USB/UART/I2C/...). >> The idea would be in the next version to modify the pch GPIO driver and >> configure these pins through the device tree. >> >> These modifications are ported from the coreboot project. >> >> Signed-off-by: Gabriel Huau >> --- >>arch/x86/cpu/baytrail/Makefile| 1 + >>arch/x86/cpu/baytrail/gpio.c | 206 +++ >>arch/x86/include/asm/arch-baytrail/gpio.h | 364 >> ++ >>arch/x86/include/asm/arch-baytrail/iomap.h| 73 ++ >>arch/x86/include/asm/arch-baytrail/irq.h | 119 + >>arch/x86/include/asm/arch-baytrail/irqroute.h | 67 + >>arch/x86/include/asm/arch-baytrail/pci_devs.h | 144 ++ >>arch/x86/include/asm/arch-baytrail/pmc.h | 253 >> ++ >>board/intel/minnowmax/minnowmax.c | 212 +++ >>include/configs/minnowmax.h | 11 + >>10 files changed, 1450 insertions(+) >>create mode 100644 arch/x86/cpu/baytrail/gpio.c >>create mode 100644 arch/x86/include/asm/arch-baytrail/iomap.h >>create mode 100644 arch/x86/include/asm/arch-baytrail/irq.h >>create mode 100644 arch/x86/include/asm/arch-baytrail/irqroute.h >>create mode 100644 arch/x86/include/asm/arch-baytrail/pci_devs.h >>create mode 100644 arch/x86/include/asm/arch-baytrail/pmc.h >> > [snip] > >> diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h >> index 823e051..738c6fa 100644 >> --- a/include/configs/minnowmax.h >> +++ b/include/configs/minnowmax.h >> @@ -69,4 +69,15 @@ >>/* Avoid a warning in the Realtek Ethernet driver */ >>#define CONFIG_SYS_CACHELINE_SIZE 16 >> >> +/* >> + * Baytrail has 3 GPIOs bank over PCI, there is no >> + * driver at the moment so let's disable the command >> + * and the default x86 driver to avoid any collision >> + * with the GPIO mapping code. >> + * @TODO: adding a baytrail-gpio driver and configure >> + * the muxing through the device tree >> + */ >> +#undef CONFIG_INTEL_ICH6_GPIO >> +#undef CONFIG_CMD_GPIO >> + > > Why undef these two? The BayTrail SoC does support GPIO banks in the > legacy bridge. I might misunderstood the GPIO subsystem but I thought there was 2 banks available through the PCU iLB GPIO controller which contains the SCORE and SSUS (102 / 44 pins). The intel_ich6_gpio has a limitation of 32 GPIOs per bank and I thought it was just a different controller from the Baytrail, but if I can use it to control all the GPIOs + doing the IO mapping, I'll be glad to do it! >>> >>> I checked the BayTrail datasheet. Its GPIO is in the iLB (legacy >>> bridge), which is the same as other IA chipset (Ivybridge, >>> TunnelCreek, Quark). It has 4 banks in core domain and 2 banks in sus >>> domain. So 6 banks in total. You need define 6 gpio nodes in the >>> minnowmax board dts file. You should be able to use the existing gpio >>> driver to configure. >> >> >> Thanks for the clarification! >> Actually, I saw it today when I was doing some tests and I configured the 6 >> banks in the devices tree. I also fixed the GPIO base address to 0x48 but I >> got some issues like the fact I'm reading only 0 from all the registers. > > Yep, the offset should be 0x48 for BayTrail. > >> The registers are configured to be in the IO Space (0x500), I checked the >> PCI configuration space to make sure that everything is enabled correctly, >> but I'm still missing something. > > I checked the gpio driver codes, and it currently has: > > /* > * Okay, I guess we're looking at the right device. The actual > * GPIO registers are in the PCI device's I/O space, starting > * at the offset that we just read. Bit 0 indicates that it's > * an I/O address, not a memory address, so mask that off. > */ > gpiobase = tmplong & 0xfffe; > > This should be changed to > > gpiobase = tmplong & 0xfffc; > > as bit1 is the enable bit on BayTrail (Intel changes this GPIO base > register again for BayTrail, sigh...) > >> Once I'll be able to use these GPIOs, I will update the entire patch to >> remove the port from Coreboot as this is not necessary. >>
Re: [U-Boot] [PATCH] x86: minnowmax: add GPIO mapping support
Hi Gabriel, On Fri, Feb 27, 2015 at 3:54 PM, gabriel huau wrote: > Hi Bin, > > > On 02/26/2015 07:30 PM, Bin Meng wrote: >> >> Hi Gabriel, >> >> On Thu, Feb 26, 2015 at 12:27 AM, Gabriel Huau >> wrote: >>> >>> Hi Bin, >>> >>> >>> On 02/24/2015 11:52 PM, Bin Meng wrote: Hi Gabriel, On Mon, Feb 16, 2015 at 5:55 AM, Gabriel Huau wrote: > > Configure the pinctrl as it required to make some IO controllers > working (USB/UART/I2C/...). > The idea would be in the next version to modify the pch GPIO driver and > configure these pins through the device tree. > > These modifications are ported from the coreboot project. > > Signed-off-by: Gabriel Huau > --- >arch/x86/cpu/baytrail/Makefile| 1 + >arch/x86/cpu/baytrail/gpio.c | 206 +++ >arch/x86/include/asm/arch-baytrail/gpio.h | 364 > ++ >arch/x86/include/asm/arch-baytrail/iomap.h| 73 ++ >arch/x86/include/asm/arch-baytrail/irq.h | 119 + >arch/x86/include/asm/arch-baytrail/irqroute.h | 67 + >arch/x86/include/asm/arch-baytrail/pci_devs.h | 144 ++ >arch/x86/include/asm/arch-baytrail/pmc.h | 253 > ++ >board/intel/minnowmax/minnowmax.c | 212 +++ >include/configs/minnowmax.h | 11 + >10 files changed, 1450 insertions(+) >create mode 100644 arch/x86/cpu/baytrail/gpio.c >create mode 100644 arch/x86/include/asm/arch-baytrail/iomap.h >create mode 100644 arch/x86/include/asm/arch-baytrail/irq.h >create mode 100644 arch/x86/include/asm/arch-baytrail/irqroute.h >create mode 100644 arch/x86/include/asm/arch-baytrail/pci_devs.h >create mode 100644 arch/x86/include/asm/arch-baytrail/pmc.h > [snip] > diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h > index 823e051..738c6fa 100644 > --- a/include/configs/minnowmax.h > +++ b/include/configs/minnowmax.h > @@ -69,4 +69,15 @@ >/* Avoid a warning in the Realtek Ethernet driver */ >#define CONFIG_SYS_CACHELINE_SIZE 16 > > +/* > + * Baytrail has 3 GPIOs bank over PCI, there is no > + * driver at the moment so let's disable the command > + * and the default x86 driver to avoid any collision > + * with the GPIO mapping code. > + * @TODO: adding a baytrail-gpio driver and configure > + * the muxing through the device tree > + */ > +#undef CONFIG_INTEL_ICH6_GPIO > +#undef CONFIG_CMD_GPIO > + Why undef these two? The BayTrail SoC does support GPIO banks in the legacy bridge. >>> >>> I might misunderstood the GPIO subsystem but I thought there was 2 banks >>> available through the PCU iLB GPIO controller which contains the SCORE >>> and >>> SSUS (102 / 44 pins). >>> The intel_ich6_gpio has a limitation of 32 GPIOs per bank and I thought >>> it >>> was just a different controller from the Baytrail, but if I can use it to >>> control all the GPIOs + doing the IO mapping, I'll be glad to do it! >> >> I checked the BayTrail datasheet. Its GPIO is in the iLB (legacy >> bridge), which is the same as other IA chipset (Ivybridge, >> TunnelCreek, Quark). It has 4 banks in core domain and 2 banks in sus >> domain. So 6 banks in total. You need define 6 gpio nodes in the >> minnowmax board dts file. You should be able to use the existing gpio >> driver to configure. > > > Thanks for the clarification! > Actually, I saw it today when I was doing some tests and I configured the 6 > banks in the devices tree. I also fixed the GPIO base address to 0x48 but I > got some issues like the fact I'm reading only 0 from all the registers. Yep, the offset should be 0x48 for BayTrail. > The registers are configured to be in the IO Space (0x500), I checked the > PCI configuration space to make sure that everything is enabled correctly, > but I'm still missing something. I checked the gpio driver codes, and it currently has: /* * Okay, I guess we're looking at the right device. The actual * GPIO registers are in the PCI device's I/O space, starting * at the offset that we just read. Bit 0 indicates that it's * an I/O address, not a memory address, so mask that off. */ gpiobase = tmplong & 0xfffe; This should be changed to gpiobase = tmplong & 0xfffc; as bit1 is the enable bit on BayTrail (Intel changes this GPIO base register again for BayTrail, sigh...) > Once I'll be able to use these GPIOs, I will update the entire patch to > remove the port from Coreboot as this is not necessary. > >#endif /* __CONFIG_H */ > -- Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] x86: minnowmax: add GPIO mapping support
Hi Bin, On 02/26/2015 07:30 PM, Bin Meng wrote: Hi Gabriel, On Thu, Feb 26, 2015 at 12:27 AM, Gabriel Huau wrote: Hi Bin, On 02/24/2015 11:52 PM, Bin Meng wrote: Hi Gabriel, On Mon, Feb 16, 2015 at 5:55 AM, Gabriel Huau wrote: Configure the pinctrl as it required to make some IO controllers working (USB/UART/I2C/...). The idea would be in the next version to modify the pch GPIO driver and configure these pins through the device tree. These modifications are ported from the coreboot project. Signed-off-by: Gabriel Huau --- arch/x86/cpu/baytrail/Makefile| 1 + arch/x86/cpu/baytrail/gpio.c | 206 +++ arch/x86/include/asm/arch-baytrail/gpio.h | 364 ++ arch/x86/include/asm/arch-baytrail/iomap.h| 73 ++ arch/x86/include/asm/arch-baytrail/irq.h | 119 + arch/x86/include/asm/arch-baytrail/irqroute.h | 67 + arch/x86/include/asm/arch-baytrail/pci_devs.h | 144 ++ arch/x86/include/asm/arch-baytrail/pmc.h | 253 ++ board/intel/minnowmax/minnowmax.c | 212 +++ include/configs/minnowmax.h | 11 + 10 files changed, 1450 insertions(+) create mode 100644 arch/x86/cpu/baytrail/gpio.c create mode 100644 arch/x86/include/asm/arch-baytrail/iomap.h create mode 100644 arch/x86/include/asm/arch-baytrail/irq.h create mode 100644 arch/x86/include/asm/arch-baytrail/irqroute.h create mode 100644 arch/x86/include/asm/arch-baytrail/pci_devs.h create mode 100644 arch/x86/include/asm/arch-baytrail/pmc.h [snip] diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index 823e051..738c6fa 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -69,4 +69,15 @@ /* Avoid a warning in the Realtek Ethernet driver */ #define CONFIG_SYS_CACHELINE_SIZE 16 +/* + * Baytrail has 3 GPIOs bank over PCI, there is no + * driver at the moment so let's disable the command + * and the default x86 driver to avoid any collision + * with the GPIO mapping code. + * @TODO: adding a baytrail-gpio driver and configure + * the muxing through the device tree + */ +#undef CONFIG_INTEL_ICH6_GPIO +#undef CONFIG_CMD_GPIO + Why undef these two? The BayTrail SoC does support GPIO banks in the legacy bridge. I might misunderstood the GPIO subsystem but I thought there was 2 banks available through the PCU iLB GPIO controller which contains the SCORE and SSUS (102 / 44 pins). The intel_ich6_gpio has a limitation of 32 GPIOs per bank and I thought it was just a different controller from the Baytrail, but if I can use it to control all the GPIOs + doing the IO mapping, I'll be glad to do it! I checked the BayTrail datasheet. Its GPIO is in the iLB (legacy bridge), which is the same as other IA chipset (Ivybridge, TunnelCreek, Quark). It has 4 banks in core domain and 2 banks in sus domain. So 6 banks in total. You need define 6 gpio nodes in the minnowmax board dts file. You should be able to use the existing gpio driver to configure. Thanks for the clarification! Actually, I saw it today when I was doing some tests and I configured the 6 banks in the devices tree. I also fixed the GPIO base address to 0x48 but I got some issues like the fact I'm reading only 0 from all the registers. The registers are configured to be in the IO Space (0x500), I checked the PCI configuration space to make sure that everything is enabled correctly, but I'm still missing something. Once I'll be able to use these GPIOs, I will update the entire patch to remove the port from Coreboot as this is not necessary. #endif /* __CONFIG_H */ -- Regards, Bin Regards, Gabriel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] x86: minnowmax: add GPIO mapping support
Hi Gabriel, On Thu, Feb 26, 2015 at 12:27 AM, Gabriel Huau wrote: > Hi Bin, > > > On 02/24/2015 11:52 PM, Bin Meng wrote: >> >> Hi Gabriel, >> >> On Mon, Feb 16, 2015 at 5:55 AM, Gabriel Huau >> wrote: >>> >>> Configure the pinctrl as it required to make some IO controllers >>> working (USB/UART/I2C/...). >>> The idea would be in the next version to modify the pch GPIO driver and >>> configure these pins through the device tree. >>> >>> These modifications are ported from the coreboot project. >>> >>> Signed-off-by: Gabriel Huau >>> --- >>> arch/x86/cpu/baytrail/Makefile| 1 + >>> arch/x86/cpu/baytrail/gpio.c | 206 +++ >>> arch/x86/include/asm/arch-baytrail/gpio.h | 364 >>> ++ >>> arch/x86/include/asm/arch-baytrail/iomap.h| 73 ++ >>> arch/x86/include/asm/arch-baytrail/irq.h | 119 + >>> arch/x86/include/asm/arch-baytrail/irqroute.h | 67 + >>> arch/x86/include/asm/arch-baytrail/pci_devs.h | 144 ++ >>> arch/x86/include/asm/arch-baytrail/pmc.h | 253 ++ >>> board/intel/minnowmax/minnowmax.c | 212 +++ >>> include/configs/minnowmax.h | 11 + >>> 10 files changed, 1450 insertions(+) >>> create mode 100644 arch/x86/cpu/baytrail/gpio.c >>> create mode 100644 arch/x86/include/asm/arch-baytrail/iomap.h >>> create mode 100644 arch/x86/include/asm/arch-baytrail/irq.h >>> create mode 100644 arch/x86/include/asm/arch-baytrail/irqroute.h >>> create mode 100644 arch/x86/include/asm/arch-baytrail/pci_devs.h >>> create mode 100644 arch/x86/include/asm/arch-baytrail/pmc.h >>> >> [snip] >> >>> diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h >>> index 823e051..738c6fa 100644 >>> --- a/include/configs/minnowmax.h >>> +++ b/include/configs/minnowmax.h >>> @@ -69,4 +69,15 @@ >>> /* Avoid a warning in the Realtek Ethernet driver */ >>> #define CONFIG_SYS_CACHELINE_SIZE 16 >>> >>> +/* >>> + * Baytrail has 3 GPIOs bank over PCI, there is no >>> + * driver at the moment so let's disable the command >>> + * and the default x86 driver to avoid any collision >>> + * with the GPIO mapping code. >>> + * @TODO: adding a baytrail-gpio driver and configure >>> + * the muxing through the device tree >>> + */ >>> +#undef CONFIG_INTEL_ICH6_GPIO >>> +#undef CONFIG_CMD_GPIO >>> + >> >> Why undef these two? The BayTrail SoC does support GPIO banks in the >> legacy bridge. > > I might misunderstood the GPIO subsystem but I thought there was 2 banks > available through the PCU iLB GPIO controller which contains the SCORE and > SSUS (102 / 44 pins). > The intel_ich6_gpio has a limitation of 32 GPIOs per bank and I thought it > was just a different controller from the Baytrail, but if I can use it to > control all the GPIOs + doing the IO mapping, I'll be glad to do it! I checked the BayTrail datasheet. Its GPIO is in the iLB (legacy bridge), which is the same as other IA chipset (Ivybridge, TunnelCreek, Quark). It has 4 banks in core domain and 2 banks in sus domain. So 6 banks in total. You need define 6 gpio nodes in the minnowmax board dts file. You should be able to use the existing gpio driver to configure. >> >>> #endif /* __CONFIG_H */ >>> -- Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] x86: minnowmax: add GPIO mapping support
Hi Bin, On 02/24/2015 11:52 PM, Bin Meng wrote: Hi Gabriel, On Mon, Feb 16, 2015 at 5:55 AM, Gabriel Huau wrote: Configure the pinctrl as it required to make some IO controllers working (USB/UART/I2C/...). The idea would be in the next version to modify the pch GPIO driver and configure these pins through the device tree. These modifications are ported from the coreboot project. Signed-off-by: Gabriel Huau --- arch/x86/cpu/baytrail/Makefile| 1 + arch/x86/cpu/baytrail/gpio.c | 206 +++ arch/x86/include/asm/arch-baytrail/gpio.h | 364 ++ arch/x86/include/asm/arch-baytrail/iomap.h| 73 ++ arch/x86/include/asm/arch-baytrail/irq.h | 119 + arch/x86/include/asm/arch-baytrail/irqroute.h | 67 + arch/x86/include/asm/arch-baytrail/pci_devs.h | 144 ++ arch/x86/include/asm/arch-baytrail/pmc.h | 253 ++ board/intel/minnowmax/minnowmax.c | 212 +++ include/configs/minnowmax.h | 11 + 10 files changed, 1450 insertions(+) create mode 100644 arch/x86/cpu/baytrail/gpio.c create mode 100644 arch/x86/include/asm/arch-baytrail/iomap.h create mode 100644 arch/x86/include/asm/arch-baytrail/irq.h create mode 100644 arch/x86/include/asm/arch-baytrail/irqroute.h create mode 100644 arch/x86/include/asm/arch-baytrail/pci_devs.h create mode 100644 arch/x86/include/asm/arch-baytrail/pmc.h [snip] diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index 823e051..738c6fa 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -69,4 +69,15 @@ /* Avoid a warning in the Realtek Ethernet driver */ #define CONFIG_SYS_CACHELINE_SIZE 16 +/* + * Baytrail has 3 GPIOs bank over PCI, there is no + * driver at the moment so let's disable the command + * and the default x86 driver to avoid any collision + * with the GPIO mapping code. + * @TODO: adding a baytrail-gpio driver and configure + * the muxing through the device tree + */ +#undef CONFIG_INTEL_ICH6_GPIO +#undef CONFIG_CMD_GPIO + Why undef these two? The BayTrail SoC does support GPIO banks in the legacy bridge. I might misunderstood the GPIO subsystem but I thought there was 2 banks available through the PCU iLB GPIO controller which contains the SCORE and SSUS (102 / 44 pins). The intel_ich6_gpio has a limitation of 32 GPIOs per bank and I thought it was just a different controller from the Baytrail, but if I can use it to control all the GPIOs + doing the IO mapping, I'll be glad to do it! #endif /* __CONFIG_H */ -- Regards, Bin Regards, Gabriel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] x86: minnowmax: add GPIO mapping support
Hi Simon,
With a little bit of delay here are the responses ... :)
On 02/17/2015 08:04 PM, Simon Glass wrote:
Hi Gabriel,
On 15 February 2015 at 14:55, Gabriel Huau wrote:
Configure the pinctrl as it required to make some IO controllers
working (USB/UART/I2C/...).
The idea would be in the next version to modify the pch GPIO driver and
configure these pins through the device tree.
These modifications are ported from the coreboot project.
Signed-off-by: Gabriel Huau
Thanks for the patch!
I have mostly nits except for one comment about register access which
is different in U-Boot...
I read all the comments and I agree on almost all of them but I have
some questions.
+
+ /* Add correct func to GPIO pad config */
+ pad_conf0 = config->pad_conf0;
+ if (config->is_gpio) {
+ if (gpio >= bank->gpio_f1_range_start &&
+ gpio <= bank->gpio_f1_range_end)
+ pad_conf0 |= PAD_FUNC1;
+ else
+ pad_conf0 |= PAD_FUNC0;
+ }
+
+ writel(reg + PAD_CONF0_REG, pad_conf0);
+ writel(reg + PAD_CONF1_REG, config->pad_conf1);
+ writel(reg + PAD_VAL_REG, config->pad_val);
+ }
+
+ if (bank->legacy_base != GP_LEGACY_BASE_NONE)
+ for (set = 0; set <= (bank->gpio_count - 1) / 32; ++set) {
+ reg = bank->legacy_base + 0x20 * set;
+
+ outl(use_sel[set], reg + LEGACY_USE_SEL_REG);
+ outl(io_sel[set], reg + LEGACY_IO_SEL_REG);
+ outl(gp_lvl[set], reg + LEGACY_GP_LVL_REG);
+ outl(tpe[set], reg + LEGACY_TPE_REG);
+ outl(tne[set], reg + LEGACY_TNE_REG);
+
+ /* TS registers are WOC */
If you know what this comment means, please spell it out without abbreviations.
Actually, I don't know the meaning of WOC and I couldn't find a
definition in the datasheet.
+ outl(0, reg + LEGACY_TS_REG);
+
+ if (bank->has_wake_en)
+ outl(wake_en[set], reg + LEGACY_WAKE_EN_REG);
+ }
+}
+
+static void setup_gpio_route(const struct byt_gpio_map *sus,
+ const struct byt_gpio_map *core)
+{
+ uint32_t route_reg = 0;
+ int i;
+
+ for (i = 0; i < 8; i++) {
+ /* SMI takes precedence and wake_en implies SCI. */
+ if (sus[i].smi)
+ route_reg |= ROUTE_SMI << (2 * i);
+ else if (sus[i].sci)
+ route_reg |= ROUTE_SCI << (2 * i);
+
+ if (core[i].smi)
+ route_reg |= ROUTE_SMI << (2 * (i + 8));
+ else if (core[i].sci)
+ route_reg |= ROUTE_SCI << (2 * (i + 8));
+ }
What happens to route_reg after this? I don't see it get returned.
I will remove the code, actually it was used when the SMI was enabled.
+
+#define GPIO_LEVEL_LOW 0
+#define GPIO_LEVEL_HIGH1
+
+#define GPIO_PEDGE_DISABLE 0
+#define GPIO_PEDGE_ENABLE 1
+
+#define GPIO_NEDGE_DISABLE 0
+#define GPIO_NEDGE_ENABLE 1
+
+/* config0[29] - Disable second mask */
+#define PAD_MASK2_DISABLE (1 << 29)
+
+/* config0[27] - Direct Irq En */
+#define PAD_IRQ_EN (1 << 27)
+
+/* config0[26] - gd_tne */
+#define PAD_TNE_IRQ(1 << 26)
+
+/* config0[25] - gd_tpe */
+#define PAD_TPE_IRQ(1 << 25)
+
+/* config0[24] - Gd Level */
+#define PAD_LEVEL_IRQ (1 << 24)
+#define PAD_EDGE_IRQ (0 << 24)
+
+/* config0[17] - Slow clkgate / glitch filter */
+#define PAD_SLOWGF_ENABLE (1 << 17)
+
+/* config0[16] - Fast clkgate / glitch filter */
+#define PAD_FASTGF_ENABLE (1 << 16)
+
+/* config0[15] - Hysteresis enable (inverted) */
+#define PAD_HYST_DISABLE (1 << 15)
+#define PAD_HYST_ENABLE(0 << 15)
+
+/* config0[14:13] - Hysteresis control */
+#define PAD_HYST_CTRL_DEFAULT (2 << 13)
+
+/* config0[11] - Bypass Flop */
+#define PAD_FLOP_BYPASS(1 << 11)
+#define PAD_FLOP_ENABLE(0 << 11)
+
+/* config0[10:9] - Pull str */
+#define PAD_PU_2K (0 << 9)
+#define PAD_PU_10K (1 << 9)
+#define PAD_PU_20K (2 << 9)
+#define PAD_PU_40K (3 << 9)
+
+/* config0[8:7] - Pull assign */
+#define PAD_PULL_DISABLE (0 << 7)
+#define PAD_PULL_UP(1 << 7)
+#define PAD_PULL_DOWN (2 << 7)
+
+/* config0[2:0] - Func. pin mux */
+#define PAD_FUNC0 0x0
+#define PAD_FUNC1 0x1
+#define PAD_FUNC2 0x2
+#define PAD_FUNC3 0x3
+#define PAD_FUNC4 0x4
+#define PAD_FUNC5 0x5
+#define PAD_FUNC6 0x6
These could be an anonymous enum (optional)
For me, only the PAD_FUNC
Re: [U-Boot] [PATCH] x86: minnowmax: add GPIO mapping support
Hi Gabriel, On Mon, Feb 16, 2015 at 5:55 AM, Gabriel Huau wrote: > Configure the pinctrl as it required to make some IO controllers > working (USB/UART/I2C/...). > The idea would be in the next version to modify the pch GPIO driver and > configure these pins through the device tree. > > These modifications are ported from the coreboot project. > > Signed-off-by: Gabriel Huau > --- > arch/x86/cpu/baytrail/Makefile| 1 + > arch/x86/cpu/baytrail/gpio.c | 206 +++ > arch/x86/include/asm/arch-baytrail/gpio.h | 364 > ++ > arch/x86/include/asm/arch-baytrail/iomap.h| 73 ++ > arch/x86/include/asm/arch-baytrail/irq.h | 119 + > arch/x86/include/asm/arch-baytrail/irqroute.h | 67 + > arch/x86/include/asm/arch-baytrail/pci_devs.h | 144 ++ > arch/x86/include/asm/arch-baytrail/pmc.h | 253 ++ > board/intel/minnowmax/minnowmax.c | 212 +++ > include/configs/minnowmax.h | 11 + > 10 files changed, 1450 insertions(+) > create mode 100644 arch/x86/cpu/baytrail/gpio.c > create mode 100644 arch/x86/include/asm/arch-baytrail/iomap.h > create mode 100644 arch/x86/include/asm/arch-baytrail/irq.h > create mode 100644 arch/x86/include/asm/arch-baytrail/irqroute.h > create mode 100644 arch/x86/include/asm/arch-baytrail/pci_devs.h > create mode 100644 arch/x86/include/asm/arch-baytrail/pmc.h > [snip] > diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h > index 823e051..738c6fa 100644 > --- a/include/configs/minnowmax.h > +++ b/include/configs/minnowmax.h > @@ -69,4 +69,15 @@ > /* Avoid a warning in the Realtek Ethernet driver */ > #define CONFIG_SYS_CACHELINE_SIZE 16 > > +/* > + * Baytrail has 3 GPIOs bank over PCI, there is no > + * driver at the moment so let's disable the command > + * and the default x86 driver to avoid any collision > + * with the GPIO mapping code. > + * @TODO: adding a baytrail-gpio driver and configure > + * the muxing through the device tree > + */ > +#undef CONFIG_INTEL_ICH6_GPIO > +#undef CONFIG_CMD_GPIO > + Why undef these two? The BayTrail SoC does support GPIO banks in the legacy bridge. > #endif /* __CONFIG_H */ > -- Regards, Bin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] x86: minnowmax: add GPIO mapping support
Hi Gabriel,
On 15 February 2015 at 14:55, Gabriel Huau wrote:
> Configure the pinctrl as it required to make some IO controllers
> working (USB/UART/I2C/...).
> The idea would be in the next version to modify the pch GPIO driver and
> configure these pins through the device tree.
>
> These modifications are ported from the coreboot project.
>
> Signed-off-by: Gabriel Huau
Thanks for the patch!
I have mostly nits except for one comment about register access which
is different in U-Boot...
> ---
> arch/x86/cpu/baytrail/Makefile| 1 +
> arch/x86/cpu/baytrail/gpio.c | 206 +++
> arch/x86/include/asm/arch-baytrail/gpio.h | 364
> ++
> arch/x86/include/asm/arch-baytrail/iomap.h| 73 ++
> arch/x86/include/asm/arch-baytrail/irq.h | 119 +
> arch/x86/include/asm/arch-baytrail/irqroute.h | 67 +
> arch/x86/include/asm/arch-baytrail/pci_devs.h | 144 ++
> arch/x86/include/asm/arch-baytrail/pmc.h | 253 ++
> board/intel/minnowmax/minnowmax.c | 212 +++
> include/configs/minnowmax.h | 11 +
> 10 files changed, 1450 insertions(+)
> create mode 100644 arch/x86/cpu/baytrail/gpio.c
> create mode 100644 arch/x86/include/asm/arch-baytrail/iomap.h
> create mode 100644 arch/x86/include/asm/arch-baytrail/irq.h
> create mode 100644 arch/x86/include/asm/arch-baytrail/irqroute.h
> create mode 100644 arch/x86/include/asm/arch-baytrail/pci_devs.h
> create mode 100644 arch/x86/include/asm/arch-baytrail/pmc.h
>
> diff --git a/arch/x86/cpu/baytrail/Makefile b/arch/x86/cpu/baytrail/Makefile
> index 8914e8b..c20a616 100644
> --- a/arch/x86/cpu/baytrail/Makefile
> +++ b/arch/x86/cpu/baytrail/Makefile
> @@ -8,3 +8,4 @@ obj-y += early_uart.o
> obj-y += fsp_configs.o
> obj-y += pci.o
> obj-y += valleyview.o
> +obj-y += gpio.o
Please keep in alphabetical order.
> diff --git a/arch/x86/cpu/baytrail/gpio.c b/arch/x86/cpu/baytrail/gpio.c
> new file mode 100644
> index 000..0ad41cc
> --- /dev/null
> +++ b/arch/x86/cpu/baytrail/gpio.c
> @@ -0,0 +1,206 @@
> +/*
> + * Copyright (c) 2012 The Chromium OS Authors.
Please add 'From coreboot ' here so people know where it came from.
> + * SPDX-License-Identifier:GPL-2.0+
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +/* GPIO-to-Pad LUTs */
> +static const u8 gpncore_gpio_to_pad[GPNCORE_COUNT] = {
> + 19, 18, 17, 20, 21, 22, 24, 25, /* [ 0: 7] */
> + 23, 16, 14, 15, 12, 26, 27, 1, /* [ 8:15] */
> + 4, 8, 11, 0, 3, 6, 10, 13, /* [16:23] */
> + 2, 5, 9 /* [24:26] */
> +};
> +
> +static const u8 gpscore_gpio_to_pad[GPSCORE_COUNT] = {
> + 85, 89, 93, 96, 99, 102, 98, 101, /* [ 0: 7] */
> + 34, 37, 36, 38, 39, 35, 40, 84, /* [ 8: 15] */
> + 62, 61, 64, 59, 54, 56, 60, 55, /* [16: 23] */
> + 63, 57, 51, 50, 53, 47, 52, 49, /* [24: 31] */
> + 48, 43, 46, 41, 45, 42, 58, 44, /* [32: 39] */
> + 95, 105, 70, 68, 67, 66, 69, 71, /* [40: 47] */
> + 65, 72, 86, 90, 88, 92, 103, 77, /* [48: 55] */
> + 79, 83, 78, 81, 80, 82, 13, 12, /* [56: 63] */
> + 15, 14, 17, 18, 19, 16, 2, 1, /* [64: 71] */
> + 0, 4, 6, 7, 9, 8, 33, 32, /* [72: 79] */
> + 31, 30, 29, 27, 25, 28, 26, 23, /* [80: 87] */
> + 21, 20, 24, 22, 5, 3, 10, 11, /* [88: 95] */
> + 106, 87, 91, 104, 97, 100 /* [96:101] */
> +};
> +
> +static const u8 gpssus_gpio_to_pad[GPSSUS_COUNT] = {
> + 29, 33, 30, 31, 32, 34, 36, 35, /* [ 0: 7] */
> + 38, 37, 18, 7, 11, 20, 17, 1, /* [ 8:15] */
> + 8, 10, 19, 12, 0, 2, 23, 39, /* [16:23] */
> + 28, 27, 22, 21, 24, 25, 26, 51, /* [24:31] */
> + 56, 54, 49, 55, 48, 57, 50, 58, /* [32:39] */
> + 52, 53, 59, 40 /* [40:43] */
> +};
The above three tables are not quite lined up, but it looks like that
was your intention.
> +
> +/* GPIO bank descriptions */
> +static const struct gpio_bank gpncore_bank = {
> + .gpio_count = GPNCORE_COUNT,
> + .gpio_to_pad = gpncore_gpio_to_pad,
> + .legacy_base = GP_LEGACY_BASE_NONE,
> + .pad_base = GPNCORE_PAD_BASE,
> + .has_wake_en = 0,
> + .gpio_f1_range_start = GPNCORE_GPIO_F1_RANGE_START,
> + .gpio_f1_range_end = GPNCORE_GPIO_F1_RANGE_END,
> +};
> +
> +static const struct gpio_bank gpscore_bank = {
> + .gpio_count = GPSCORE_COUNT,
> + .gpio_to_pad = gpscore_gpio_to_pad,
> + .legacy_base = GPSCORE_LEGACY_BASE,
> + .pad_base = GPSCORE_PAD_BASE,
> + .has_wake_en = 0,
> + .gpio_f1_range_start = GPSCORE_GPIO_F1_RANGE_START,
> + .gpio_f1_range_end = GPSCORE_GPIO_F1_RANGE_END,
> +};
> +
> +static const struct gpio_bank gps
[U-Boot] [PATCH] x86: minnowmax: add GPIO mapping support
Configure the pinctrl as it required to make some IO controllers
working (USB/UART/I2C/...).
The idea would be in the next version to modify the pch GPIO driver and
configure these pins through the device tree.
These modifications are ported from the coreboot project.
Signed-off-by: Gabriel Huau
---
arch/x86/cpu/baytrail/Makefile| 1 +
arch/x86/cpu/baytrail/gpio.c | 206 +++
arch/x86/include/asm/arch-baytrail/gpio.h | 364 ++
arch/x86/include/asm/arch-baytrail/iomap.h| 73 ++
arch/x86/include/asm/arch-baytrail/irq.h | 119 +
arch/x86/include/asm/arch-baytrail/irqroute.h | 67 +
arch/x86/include/asm/arch-baytrail/pci_devs.h | 144 ++
arch/x86/include/asm/arch-baytrail/pmc.h | 253 ++
board/intel/minnowmax/minnowmax.c | 212 +++
include/configs/minnowmax.h | 11 +
10 files changed, 1450 insertions(+)
create mode 100644 arch/x86/cpu/baytrail/gpio.c
create mode 100644 arch/x86/include/asm/arch-baytrail/iomap.h
create mode 100644 arch/x86/include/asm/arch-baytrail/irq.h
create mode 100644 arch/x86/include/asm/arch-baytrail/irqroute.h
create mode 100644 arch/x86/include/asm/arch-baytrail/pci_devs.h
create mode 100644 arch/x86/include/asm/arch-baytrail/pmc.h
diff --git a/arch/x86/cpu/baytrail/Makefile b/arch/x86/cpu/baytrail/Makefile
index 8914e8b..c20a616 100644
--- a/arch/x86/cpu/baytrail/Makefile
+++ b/arch/x86/cpu/baytrail/Makefile
@@ -8,3 +8,4 @@ obj-y += early_uart.o
obj-y += fsp_configs.o
obj-y += pci.o
obj-y += valleyview.o
+obj-y += gpio.o
diff --git a/arch/x86/cpu/baytrail/gpio.c b/arch/x86/cpu/baytrail/gpio.c
new file mode 100644
index 000..0ad41cc
--- /dev/null
+++ b/arch/x86/cpu/baytrail/gpio.c
@@ -0,0 +1,206 @@
+/*
+ * Copyright (c) 2012 The Chromium OS Authors.
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* GPIO-to-Pad LUTs */
+static const u8 gpncore_gpio_to_pad[GPNCORE_COUNT] = {
+ 19, 18, 17, 20, 21, 22, 24, 25, /* [ 0: 7] */
+ 23, 16, 14, 15, 12, 26, 27, 1, /* [ 8:15] */
+ 4, 8, 11, 0, 3, 6, 10, 13, /* [16:23] */
+ 2, 5, 9 /* [24:26] */
+};
+
+static const u8 gpscore_gpio_to_pad[GPSCORE_COUNT] = {
+ 85, 89, 93, 96, 99, 102, 98, 101, /* [ 0: 7] */
+ 34, 37, 36, 38, 39, 35, 40, 84, /* [ 8: 15] */
+ 62, 61, 64, 59, 54, 56, 60, 55, /* [16: 23] */
+ 63, 57, 51, 50, 53, 47, 52, 49, /* [24: 31] */
+ 48, 43, 46, 41, 45, 42, 58, 44, /* [32: 39] */
+ 95, 105, 70, 68, 67, 66, 69, 71, /* [40: 47] */
+ 65, 72, 86, 90, 88, 92, 103, 77, /* [48: 55] */
+ 79, 83, 78, 81, 80, 82, 13, 12, /* [56: 63] */
+ 15, 14, 17, 18, 19, 16, 2, 1, /* [64: 71] */
+ 0, 4, 6, 7, 9, 8, 33, 32, /* [72: 79] */
+ 31, 30, 29, 27, 25, 28, 26, 23, /* [80: 87] */
+ 21, 20, 24, 22, 5, 3, 10, 11, /* [88: 95] */
+ 106, 87, 91, 104, 97, 100 /* [96:101] */
+};
+
+static const u8 gpssus_gpio_to_pad[GPSSUS_COUNT] = {
+ 29, 33, 30, 31, 32, 34, 36, 35, /* [ 0: 7] */
+ 38, 37, 18, 7, 11, 20, 17, 1, /* [ 8:15] */
+ 8, 10, 19, 12, 0, 2, 23, 39, /* [16:23] */
+ 28, 27, 22, 21, 24, 25, 26, 51, /* [24:31] */
+ 56, 54, 49, 55, 48, 57, 50, 58, /* [32:39] */
+ 52, 53, 59, 40 /* [40:43] */
+};
+
+/* GPIO bank descriptions */
+static const struct gpio_bank gpncore_bank = {
+ .gpio_count = GPNCORE_COUNT,
+ .gpio_to_pad = gpncore_gpio_to_pad,
+ .legacy_base = GP_LEGACY_BASE_NONE,
+ .pad_base = GPNCORE_PAD_BASE,
+ .has_wake_en = 0,
+ .gpio_f1_range_start = GPNCORE_GPIO_F1_RANGE_START,
+ .gpio_f1_range_end = GPNCORE_GPIO_F1_RANGE_END,
+};
+
+static const struct gpio_bank gpscore_bank = {
+ .gpio_count = GPSCORE_COUNT,
+ .gpio_to_pad = gpscore_gpio_to_pad,
+ .legacy_base = GPSCORE_LEGACY_BASE,
+ .pad_base = GPSCORE_PAD_BASE,
+ .has_wake_en = 0,
+ .gpio_f1_range_start = GPSCORE_GPIO_F1_RANGE_START,
+ .gpio_f1_range_end = GPSCORE_GPIO_F1_RANGE_END,
+};
+
+static const struct gpio_bank gpssus_bank = {
+ .gpio_count = GPSSUS_COUNT,
+ .gpio_to_pad = gpssus_gpio_to_pad,
+ .legacy_base = GPSSUS_LEGACY_BASE,
+ .pad_base = GPSSUS_PAD_BASE,
+ .has_wake_en = 1,
+ .gpio_f1_range_start = GPSSUS_GPIO_F1_RANGE_START,
+ .gpio_f1_range_end = GPSSUS_GPIO_F1_RANGE_END,
+};
+
+static void setup_gpios(const struct byt_gpio_map *gpios,
+ const struct gpio_bank *bank)
+{
+ const struct byt_gpio_map *config;
+ int gpio = 0;
+ u32 reg, pad_conf0;
+ u8 set, bit;
+
+ u32 use_sel[4] = {0};
+ u32 io_sel[4] = {0};
+
