subject:"\[U\-Boot\] \[PATCH 02\/05\] arm\: mach\-snapdragon\: refactor clock driver"

[U-Boot] [PATCH 02/05] arm: mach-snapdragon: refactor clock driver

2018-01-09 Thread Jorge Ramirez-Ortiz

From: Jorge Ramirez-Ortiz 

In preparation to add support for the Dragonboard820c (APQ8096),
refactor the current Snapdragon clock driver.

No new functionality has been added.

Signed-off-by: Jorge Ramirez-Ortiz 
---
 arch/arm/mach-snapdragon/Makefile  |   6 +-
 arch/arm/mach-snapdragon/clock-apq8016.c   | 181 ++---
 arch/arm/mach-snapdragon/clock-snapdragon.c| 134 +++
 arch/arm/mach-snapdragon/clock-snapdragon.h|  40 +
 .../mach-snapdragon/include/mach/sysmap-apq8016.h  |  29 +++-
 5 files changed, 217 insertions(+), 173 deletions(-)
 create mode 100644 arch/arm/mach-snapdragon/clock-snapdragon.c
 create mode 100644 arch/arm/mach-snapdragon/clock-snapdragon.h

diff --git a/arch/arm/mach-snapdragon/Makefile 
b/arch/arm/mach-snapdragon/Makefile
index d82a04d..74f90dc 100644
--- a/arch/arm/mach-snapdragon/Makefile
+++ b/arch/arm/mach-snapdragon/Makefile
@@ -4,5 +4,6 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y += clock-apq8016.o
-obj-y += sysmap-apq8016.o
+obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o
+obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o
+obj-y += clock-snapdragon.o
diff --git a/arch/arm/mach-snapdragon/clock-apq8016.c 
b/arch/arm/mach-snapdragon/clock-apq8016.c
index da05015..a242417 100644
--- a/arch/arm/mach-snapdragon/clock-apq8016.c
+++ b/arch/arm/mach-snapdragon/clock-apq8016.c
@@ -14,146 +14,12 @@
 #include 
 #include 
 #include 
+#include "clock-snapdragon.h"
 
 /* GPLL0 clock control registers */
-#define GPLL0_STATUS0x2101C
 #define GPLL0_STATUS_ACTIVE BIT(17)
-
-#define APCS_GPLL_ENA_VOTE  0x45000
 #define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0)
 
-/* vote reg for blsp1 clock */
-#define APCS_CLOCK_BRANCH_ENA_VOTE  0x45004
-#define APCS_CLOCK_BRANCH_ENA_VOTE_BLSP1 BIT(10)
-
-/* SDC(n) clock control registers; n=1,2 */
-
-/* block control register */
-#define SDCC_BCR(n) ((n * 0x1000) + 0x41000)
-/* cmd */
-#define SDCC_CMD_RCGR(n)((n * 0x1000) + 0x41004)
-/* cfg */
-#define SDCC_CFG_RCGR(n)((n * 0x1000) + 0x41008)
-/* m */
-#define SDCC_M(n)   ((n * 0x1000) + 0x4100C)
-/* n */
-#define SDCC_N(n)   ((n * 0x1000) + 0x41010)
-/* d */
-#define SDCC_D(n)   ((n * 0x1000) + 0x41014)
-/* branch control */
-#define SDCC_APPS_CBCR(n)   ((n * 0x1000) + 0x41018)
-#define SDCC_AHB_CBCR(n)((n * 0x1000) + 0x4101C)
-
-/* BLSP1 AHB clock (root clock for BLSP) */
-#define BLSP1_AHB_CBCR  0x1008
-
-/* Uart clock control registers */
-#define BLSP1_UART2_BCR 0x3028
-#define BLSP1_UART2_APPS_CBCR   0x302C
-#define BLSP1_UART2_APPS_CMD_RCGR   0x3034
-#define BLSP1_UART2_APPS_CFG_RCGR   0x3038
-#define BLSP1_UART2_APPS_M  0x303C
-#define BLSP1_UART2_APPS_N  0x3040
-#define BLSP1_UART2_APPS_D  0x3044
-
-/* CBCR register fields */
-#define CBCR_BRANCH_ENABLE_BIT  BIT(0)
-#define CBCR_BRANCH_OFF_BIT BIT(31)
-
-struct msm_clk_priv {
-   phys_addr_t base;
-};
-
-/* Enable clock controlled by CBC soft macro */
-static void clk_enable_cbc(phys_addr_t cbcr)
-{
-   setbits_le32(cbcr, CBCR_BRANCH_ENABLE_BIT);
-
-   while (readl(cbcr) & CBCR_BRANCH_OFF_BIT)
-   ;
-}
-
-/* clock has 800MHz */
-static void clk_enable_gpll0(phys_addr_t base)
-{
-   if (readl(base + GPLL0_STATUS) & GPLL0_STATUS_ACTIVE)
-   return; /* clock already enabled */
-
-   setbits_le32(base + APCS_GPLL_ENA_VOTE, APCS_GPLL_ENA_VOTE_GPLL0);
-
-   while ((readl(base + GPLL0_STATUS) & GPLL0_STATUS_ACTIVE) == 0)
-   ;
-}
-
-#define APPS_CMD_RGCR_UPDATE BIT(0)
-
-/* Update clock command via CMD_RGCR */
-static void clk_bcr_update(phys_addr_t apps_cmd_rgcr)
-{
-   setbits_le32(apps_cmd_rgcr, APPS_CMD_RGCR_UPDATE);
-
-   /* Wait for frequency to be updated. */
-   while (readl(apps_cmd_rgcr) & APPS_CMD_RGCR_UPDATE)
-   ;
-}
-
-struct bcr_regs {
-   uintptr_t cfg_rcgr;
-   uintptr_t cmd_rcgr;
-   uintptr_t M;
-   uintptr_t N;
-   uintptr_t D;
-};
-
-/* RCGR_CFG register fields */
-#define CFG_MODE_DUAL_EDGE (0x2 << 12) /* Counter mode */
-
-/* sources */
-#define CFG_CLK_SRC_CXO   (0 << 8)
-#define CFG_CLK_SRC_GPLL0 (1 << 8)
-#define CFG_CLK_SRC_MASK  (7 << 8)
-
-/* Mask for supported fields */
-#define CFG_MASK 0x3FFF
-
-#define CFG_DIVIDER_MASK 0x1F
-
-/* root set rate for clocks with half integer and MND divider */
-static void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
-int div, int m, int n, int source)
-{
-   uint32_t cfg;
-   /* M value for MND divider. */
-   uint32_t m_val = m;
-   /* NOT(N-M) value for MND divider. */
-   uint32_t n_val = ~((n)-(m)) * !!(n);
-   /* NOT 2D value for MND divider. */
-   uint32_t d_val = ~(n);
-
-   /*

[U-Boot] [PATCH 02/05] arm: mach-snapdragon: refactor clock driver

2018-01-05 Thread Jorge Ramirez-Ortiz

In preparation to add support for the Dragonboard820c (APQ8096),
refactor the current Snapdragon clock driver.

No new functionality has been added.

Signed-off-by: Jorge Ramirez-Ortiz 
---
 arch/arm/mach-snapdragon/Makefile  |   6 +-
 arch/arm/mach-snapdragon/clock-apq8016.c   | 181 ++---
 arch/arm/mach-snapdragon/clock-snapdragon.c| 134 +++
 arch/arm/mach-snapdragon/clock-snapdragon.h|  40 +
 .../mach-snapdragon/include/mach/sysmap-apq8016.h  |  29 +++-
 5 files changed, 217 insertions(+), 173 deletions(-)
 create mode 100644 arch/arm/mach-snapdragon/clock-snapdragon.c
 create mode 100644 arch/arm/mach-snapdragon/clock-snapdragon.h

diff --git a/arch/arm/mach-snapdragon/Makefile 
b/arch/arm/mach-snapdragon/Makefile
index d82a04d..74f90dc 100644
--- a/arch/arm/mach-snapdragon/Makefile
+++ b/arch/arm/mach-snapdragon/Makefile
@@ -4,5 +4,6 @@
 # SPDX-License-Identifier: GPL-2.0+
 #
 
-obj-y += clock-apq8016.o
-obj-y += sysmap-apq8016.o
+obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o
+obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o
+obj-y += clock-snapdragon.o
diff --git a/arch/arm/mach-snapdragon/clock-apq8016.c 
b/arch/arm/mach-snapdragon/clock-apq8016.c
index da05015..a242417 100644
--- a/arch/arm/mach-snapdragon/clock-apq8016.c
+++ b/arch/arm/mach-snapdragon/clock-apq8016.c
@@ -14,146 +14,12 @@
 #include 
 #include 
 #include 
+#include "clock-snapdragon.h"
 
 /* GPLL0 clock control registers */
-#define GPLL0_STATUS0x2101C
 #define GPLL0_STATUS_ACTIVE BIT(17)
-
-#define APCS_GPLL_ENA_VOTE  0x45000
 #define APCS_GPLL_ENA_VOTE_GPLL0 BIT(0)
 
-/* vote reg for blsp1 clock */
-#define APCS_CLOCK_BRANCH_ENA_VOTE  0x45004
-#define APCS_CLOCK_BRANCH_ENA_VOTE_BLSP1 BIT(10)
-
-/* SDC(n) clock control registers; n=1,2 */
-
-/* block control register */
-#define SDCC_BCR(n) ((n * 0x1000) + 0x41000)
-/* cmd */
-#define SDCC_CMD_RCGR(n)((n * 0x1000) + 0x41004)
-/* cfg */
-#define SDCC_CFG_RCGR(n)((n * 0x1000) + 0x41008)
-/* m */
-#define SDCC_M(n)   ((n * 0x1000) + 0x4100C)
-/* n */
-#define SDCC_N(n)   ((n * 0x1000) + 0x41010)
-/* d */
-#define SDCC_D(n)   ((n * 0x1000) + 0x41014)
-/* branch control */
-#define SDCC_APPS_CBCR(n)   ((n * 0x1000) + 0x41018)
-#define SDCC_AHB_CBCR(n)((n * 0x1000) + 0x4101C)
-
-/* BLSP1 AHB clock (root clock for BLSP) */
-#define BLSP1_AHB_CBCR  0x1008
-
-/* Uart clock control registers */
-#define BLSP1_UART2_BCR 0x3028
-#define BLSP1_UART2_APPS_CBCR   0x302C
-#define BLSP1_UART2_APPS_CMD_RCGR   0x3034
-#define BLSP1_UART2_APPS_CFG_RCGR   0x3038
-#define BLSP1_UART2_APPS_M  0x303C
-#define BLSP1_UART2_APPS_N  0x3040
-#define BLSP1_UART2_APPS_D  0x3044
-
-/* CBCR register fields */
-#define CBCR_BRANCH_ENABLE_BIT  BIT(0)
-#define CBCR_BRANCH_OFF_BIT BIT(31)
-
-struct msm_clk_priv {
-   phys_addr_t base;
-};
-
-/* Enable clock controlled by CBC soft macro */
-static void clk_enable_cbc(phys_addr_t cbcr)
-{
-   setbits_le32(cbcr, CBCR_BRANCH_ENABLE_BIT);
-
-   while (readl(cbcr) & CBCR_BRANCH_OFF_BIT)
-   ;
-}
-
-/* clock has 800MHz */
-static void clk_enable_gpll0(phys_addr_t base)
-{
-   if (readl(base + GPLL0_STATUS) & GPLL0_STATUS_ACTIVE)
-   return; /* clock already enabled */
-
-   setbits_le32(base + APCS_GPLL_ENA_VOTE, APCS_GPLL_ENA_VOTE_GPLL0);
-
-   while ((readl(base + GPLL0_STATUS) & GPLL0_STATUS_ACTIVE) == 0)
-   ;
-}
-
-#define APPS_CMD_RGCR_UPDATE BIT(0)
-
-/* Update clock command via CMD_RGCR */
-static void clk_bcr_update(phys_addr_t apps_cmd_rgcr)
-{
-   setbits_le32(apps_cmd_rgcr, APPS_CMD_RGCR_UPDATE);
-
-   /* Wait for frequency to be updated. */
-   while (readl(apps_cmd_rgcr) & APPS_CMD_RGCR_UPDATE)
-   ;
-}
-
-struct bcr_regs {
-   uintptr_t cfg_rcgr;
-   uintptr_t cmd_rcgr;
-   uintptr_t M;
-   uintptr_t N;
-   uintptr_t D;
-};
-
-/* RCGR_CFG register fields */
-#define CFG_MODE_DUAL_EDGE (0x2 << 12) /* Counter mode */
-
-/* sources */
-#define CFG_CLK_SRC_CXO   (0 << 8)
-#define CFG_CLK_SRC_GPLL0 (1 << 8)
-#define CFG_CLK_SRC_MASK  (7 << 8)
-
-/* Mask for supported fields */
-#define CFG_MASK 0x3FFF
-
-#define CFG_DIVIDER_MASK 0x1F
-
-/* root set rate for clocks with half integer and MND divider */
-static void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs,
-int div, int m, int n, int source)
-{
-   uint32_t cfg;
-   /* M value for MND divider. */
-   uint32_t m_val = m;
-   /* NOT(N-M) value for MND divider. */
-   uint32_t n_val = ~((n)-(m)) * !!(n);
-   /* NOT 2D value for MND divider. */
-   uint32_t d_val = ~(n);
-
-   /* Program MND values */
-   writel(m_val, base +

[U-Boot] [PATCH 02/05] arm: mach-snapdragon: refactor clock driver

[U-Boot] [PATCH 02/05] arm: mach-snapdragon: refactor clock driver

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