Re: [U-Boot] [PATCH 02/10] rockchip: rk3288: Add clock support for the gmac ethernet interface

[Simon Glass]

On 1 October 2015 at 10:48, Sjoerd Simons  wrote:
> Setup the clocks for the gmac ethernet interface. This assumes the mac
> clock is fed by an external clock which is common on RK3288 based
> devices.
>
> Signed-off-by: Sjoerd Simons 
> ---
>
>  arch/arm/include/asm/arch-rockchip/cru_rk3288.h | 17 +
>  drivers/clk/clk_rk3288.c| 16 
>  2 files changed, 33 insertions(+)

Acked-by: Simon Glass 
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[U-Boot] [PATCH 02/10] rockchip: rk3288: Add clock support for the gmac ethernet interface

[Sjoerd Simons]

Setup the clocks for the gmac ethernet interface. This assumes the mac
clock is fed by an external clock which is common on RK3288 based
devices.

Signed-off-by: Sjoerd Simons 
---

 arch/arm/include/asm/arch-rockchip/cru_rk3288.h | 17 +
 drivers/clk/clk_rk3288.c| 16 
 2 files changed, 33 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h 
b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
index 7ebcc40..69ec168 100644
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
@@ -90,6 +90,23 @@ enum {
SDIO0_DIV_MASK  = 0x3f,
 };
 
+/* CRU_CLKSEL21_CON */
+enum {
+   MAC_DIV_CON_SHIFT = 0xf,
+   MAC_DIV_CON_MASK = 0x1f,
+
+   RMII_EXTCLK_SHIFT = 4,
+   RMII_EXTCLK_MASK = 1,
+   RMII_EXTCLK_SELECT_INT_DIV_CLK = 0,
+   RMII_EXTCLK_SELECT_EXT_CLK = 1,
+
+   EMAC_PLL_SHIFT = 0,
+   EMAC_PLL_MASK = 0x3,
+   EMAC_PLL_SELECT_NEW = 0x0,
+   EMAC_PLL_SELECT_CODEC = 0x1,
+   EMAC_PLL_SELECT_GENERAL = 0x2,
+};
+
 /* CRU_CLKSEL25_CON */
 enum {
SPI1_PLL_SHIFT  = 0xf,
diff --git a/drivers/clk/clk_rk3288.c b/drivers/clk/clk_rk3288.c
index 54d4930..22f53d9 100644
--- a/drivers/clk/clk_rk3288.c
+++ b/drivers/clk/clk_rk3288.c
@@ -442,6 +442,18 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, 
uint clk_general_rate,
return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
 }
 
+static ulong rockchip_gmac_set_clk(struct rk3288_cru *cru,
+ uint clk_general_rate,
+ enum periph_id periph, uint freq)
+{
+   /* Assuming mac_clk is fed by an external clock */
+   rk_clrsetreg(&cru->cru_clksel_con[21],
+RMII_EXTCLK_MASK << RMII_EXTCLK_SHIFT,
+RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT);
+
+return 0;
+}
+
 static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint 
clk_general_rate,
  enum periph_id periph)
 {
@@ -514,6 +526,10 @@ ulong rk3288_set_periph_rate(struct udevice *dev, int 
periph, ulong rate)
ulong new_rate;
 
switch (periph) {
+   case PERIPH_ID_GMAC:
+   new_rate = rockchip_gmac_set_clk(priv->cru, clk_get_rate(dev),
+   periph, rate);
+   break;
case PERIPH_ID_EMMC:
case PERIPH_ID_SDCARD:
new_rate = rockchip_mmc_set_clk(priv->cru, clk_get_rate(dev),
-- 
2.5.3

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