Re: [U-Boot] [PATCH 02/12] arm: socfpga: Sync Cyclone V DK pinmux configuration

2015-01-17 Thread Dinh Nguyen 


On 12/31/14 1:14 PM, Marek Vasut wrote:
 Sync SoCFPGA Cyclone V development kit pinmux configuration with
 Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).
 
 Signed-off-by: Marek Vasut ma...@denx.de
 Cc: Chin Liang See cl...@opensource.altera.com
 Cc: Dinh Nguyen dingu...@opensource.altera.com
 Cc: Pavel Machek pa...@denx.de
 Cc: Stefan Roese s...@denx.de
 Cc: Vince Bridgers vbrid...@opensource.altera.com
 ---
  board/altera/socfpga/pinmux_config.c | 188 
 +--
  board/altera/socfpga/pinmux_config.h |  14 +--
  2 files changed, 101 insertions(+), 101 deletions(-)
 
 diff --git a/board/altera/socfpga/pinmux_config.c 
 b/board/altera/socfpga/pinmux_config.c
 index 8b09005..b124768 100644
 --- a/board/altera/socfpga/pinmux_config.c
 +++ b/board/altera/socfpga/pinmux_config.c
 @@ -4,100 +4,100 @@
  
  /* pin mux configuration data */

Acked-by: Dinh Nguyen dingu...@opensource.altera.com
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Re: [U-Boot] [PATCH 02/12] arm: socfpga: Sync Cyclone V DK pinmux configuration

2015-01-03 Thread Stefan Roese 

On 31.12.2014 20:14, Marek Vasut wrote:

Sync SoCFPGA Cyclone V development kit pinmux configuration with
Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).

Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@opensource.altera.com
Cc: Dinh Nguyen dingu...@opensource.altera.com
Cc: Pavel Machek pa...@denx.de
Cc: Stefan Roese s...@denx.de
Cc: Vince Bridgers vbrid...@opensource.altera.com


This is all for SPL only, right? Not sure if we should change these 
defines / values now even though its not really used in mainline. But it 
doesn't hurt. So:


Reviewed-by: Stefan Roese s...@denx.de

Thanks,
Stefan

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Re: [U-Boot] [PATCH 02/12] arm: socfpga: Sync Cyclone V DK pinmux configuration

2015-01-03 Thread Marek Vasut 
On Saturday, January 03, 2015 at 12:08:04 PM, Stefan Roese wrote:
 On 31.12.2014 20:14, Marek Vasut wrote:
  Sync SoCFPGA Cyclone V development kit pinmux configuration with
  Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).
  
  Signed-off-by: Marek Vasut ma...@denx.de
  Cc: Chin Liang See cl...@opensource.altera.com
  Cc: Dinh Nguyen dingu...@opensource.altera.com
  Cc: Pavel Machek pa...@denx.de
  Cc: Stefan Roese s...@denx.de
  Cc: Vince Bridgers vbrid...@opensource.altera.com
 
 This is all for SPL only, right?

Yes.

 Not sure if we should change these
 defines / values now even though its not really used in mainline. But it
 doesn't hurt. So:

It doesn't hurt keeping closer to RocketBoards for the time being I guess.

 Reviewed-by: Stefan Roese s...@denx.de

Thanks!

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 02/12] arm: socfpga: Sync Cyclone V DK pinmux configuration

2015-01-03 Thread Marek Vasut 
On Friday, January 02, 2015 at 06:13:43 AM, Pavel Machek wrote:
 On Wed 2014-12-31 20:14:50, Marek Vasut wrote:
  Sync SoCFPGA Cyclone V development kit pinmux configuration with
  Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).
  
  Signed-off-by: Marek Vasut ma...@denx.de
  Cc: Chin Liang See cl...@opensource.altera.com
  Cc: Dinh Nguyen dingu...@opensource.altera.com
  Cc: Pavel Machek pa...@denx.de
  Cc: Stefan Roese s...@denx.de
  Cc: Vince Bridgers vbrid...@opensource.altera.com
 
 Will this break the other socfpga targets? Because tables are
 completely different...

Mainline only supports socdk and socrates, which do work with this patch.
In case this did break some out-of-mainline boards, that cannot really be
helped at this point.

Still, this is only used in (already broken) SPL, so there's really nothing
much to be worried about there. The ultimate goal is to use pinmux from the
DT and zap this file.

Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 02/12] arm: socfpga: Sync Cyclone V DK pinmux configuration

2015-01-01 Thread Pavel Machek 
On Wed 2014-12-31 20:14:50, Marek Vasut wrote:
 Sync SoCFPGA Cyclone V development kit pinmux configuration with
 Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).
 
 Signed-off-by: Marek Vasut ma...@denx.de
 Cc: Chin Liang See cl...@opensource.altera.com
 Cc: Dinh Nguyen dingu...@opensource.altera.com
 Cc: Pavel Machek pa...@denx.de
 Cc: Stefan Roese s...@denx.de
 Cc: Vince Bridgers vbrid...@opensource.altera.com

Will this break the other socfpga targets? Because tables are
completely different...
Pavel

 ---
  board/altera/socfpga/pinmux_config.c | 188 
 +--
  board/altera/socfpga/pinmux_config.h |  14 +--
  2 files changed, 101 insertions(+), 101 deletions(-)
 
 diff --git a/board/altera/socfpga/pinmux_config.c 
 b/board/altera/socfpga/pinmux_config.c
 index 8b09005..b124768 100644
 --- a/board/altera/socfpga/pinmux_config.c
 +++ b/board/altera/socfpga/pinmux_config.c
 @@ -4,100 +4,100 @@
  
  /* pin mux configuration data */
  unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
 - 0, /* EMACIO0 - Unused */
 - 2, /* EMACIO1 - USB */
 - 2, /* EMACIO2 - USB */
 - 2, /* EMACIO3 - USB */
 - 2, /* EMACIO4 - USB */
 - 2, /* EMACIO5 - USB */
 - 2, /* EMACIO6 - USB */
 - 2, /* EMACIO7 - USB */
 - 2, /* EMACIO8 - USB */
 - 0, /* EMACIO9 - Unused */
 - 2, /* EMACIO10 - USB */
 - 2, /* EMACIO11 - USB */
 - 2, /* EMACIO12 - USB */
 - 2, /* EMACIO13 - USB */
 - 0, /* EMACIO14 - N/A */
 - 0, /* EMACIO15 - N/A */
 - 0, /* EMACIO16 - N/A */
 - 0, /* EMACIO17 - N/A */
 - 0, /* EMACIO18 - N/A */
 - 0, /* EMACIO19 - N/A */
 - 3, /* FLASHIO0 - SDMMC */
 - 3, /* FLASHIO1 - SDMMC */
 - 3, /* FLASHIO2 - SDMMC */
 - 3, /* FLASHIO3 - SDMMC */
 - 0, /* FLASHIO4 - SDMMC */
 - 0, /* FLASHIO5 - SDMMC */
 - 0, /* FLASHIO6 - SDMMC */
 - 0, /* FLASHIO7 - SDMMC */
 - 0, /* FLASHIO8 - SDMMC */
 - 3, /* FLASHIO9 - SDMMC */
 - 3, /* FLASHIO10 - SDMMC */
 - 3, /* FLASHIO11 - SDMMC */
 - 3, /* GENERALIO0 - TRACE */
 - 3, /* GENERALIO1 - TRACE */
 - 3, /* GENERALIO2 - TRACE */
 - 3, /* GENERALIO3 - TRACE  */
 - 3, /* GENERALIO4 - TRACE  */
 - 3, /* GENERALIO5 - TRACE  */
 - 3, /* GENERALIO6 - TRACE  */
 - 3, /* GENERALIO7 - TRACE  */
 - 3, /* GENERALIO8 - TRACE  */
 - 3, /* GENERALIO9 - SPIM0 */
 - 3, /* GENERALIO10 - SPIM0 */
 - 3, /* GENERALIO11 - SPIM0 */
 - 3, /* GENERALIO12 - SPIM0 */
 - 2, /* GENERALIO13 - CAN0 */
 - 2, /* GENERALIO14 - CAN0 */
 - 3, /* GENERALIO15 - I2C0 */
 - 3, /* GENERALIO16 - I2C0 */
 - 2, /* GENERALIO17 - UART0 */
 - 2, /* GENERALIO18 - UART0 */
 - 0, /* GENERALIO19 - N/A */
 - 0, /* GENERALIO20 - N/A */
 - 0, /* GENERALIO21 - N/A */
 - 0, /* GENERALIO22 - N/A */
 - 0, /* GENERALIO23 - N/A */
 - 0, /* GENERALIO24 - N/A */
 - 0, /* GENERALIO25 - N/A */
 - 0, /* GENERALIO26 - N/A */
 - 0, /* GENERALIO27 - N/A */
 - 0, /* GENERALIO28 - N/A */
 - 0, /* GENERALIO29 - N/A */
 - 0, /* GENERALIO30 - N/A */
 - 0, /* GENERALIO31 - N/A */
 - 2, /* MIXED1IO0 - EMAC */
 - 2, /* MIXED1IO1 - EMAC */
 - 2, /* MIXED1IO2 - EMAC */
 - 2, /* MIXED1IO3 - EMAC */
 - 2, /* MIXED1IO4 - EMAC */
 - 2, /* MIXED1IO5 - EMAC */
 - 2, /* MIXED1IO6 - EMAC */
 - 2, /* MIXED1IO7 - EMAC */
 - 2, /* MIXED1IO8 - EMAC */
 - 2, /* MIXED1IO9 - EMAC */
 - 2, /* MIXED1IO10 - EMAC */
 - 2, /* MIXED1IO11 - EMAC */
 - 2, /* MIXED1IO12 - EMAC */
 - 2, /* MIXED1IO13 - EMAC */
 - 0, /* MIXED1IO14 - Unused */
 - 3, /* MIXED1IO15 - QSPI */
 - 3, /* MIXED1IO16 - QSPI */
 - 3, /* MIXED1IO17 - QSPI */
 - 3, /* MIXED1IO18 - QSPI */
 - 3, /* MIXED1IO19 - QSPI */
 - 3, /* MIXED1IO20 - QSPI */
 - 0, /* MIXED1IO21 - GPIO */
 - 0, /* MIXED2IO0 - N/A */
 - 0, /* MIXED2IO1 - N/A */
 - 0, /* MIXED2IO2 - N/A */
 - 0, /* MIXED2IO3 - N/A */
 - 0, /* MIXED2IO4 - N/A */
 - 0, /* MIXED2IO5 - N/A */
 - 0, /* MIXED2IO6 - N/A */
 - 0, /* MIXED2IO7 - N/A */
 + 3, /* EMACIO0 */
 + 3, /* EMACIO1 */
 + 3, /* EMACIO2 */
 + 3, /* EMACIO3 */
 + 3, /* EMACIO4 */
 + 3, /* EMACIO5 */
 + 3, /* EMACIO6 */
 + 3, /* EMACIO7 */
 + 3, /* EMACIO8 */
 + 3, /* EMACIO9 */
 + 3, /* EMACIO10 */
 + 3, /* EMACIO11 */
 + 3, /* EMACIO12 */
 + 3, /* EMACIO13 */
 + 0, /* EMACIO14 */
 + 0, /* EMACIO15 */
 + 0, /* EMACIO16 */
 + 0, /* EMACIO17 */
 + 0, /* EMACIO18 */
 + 0, /* EMACIO19 */
 + 3, /* FLASHIO0 */
 + 0, /* FLASHIO1 */
 + 3, /* FLASHIO2 */
 + 3, /* FLASHIO3 */
 + 3, /* FLASHIO4 */
 + 3, /* FLASHIO5 */
 + 3, /* FLASHIO6 */
 + 3, /* FLASHIO7 */
 + 0, /* FLASHIO8 */
 + 3, /* FLASHIO9 */
 +

[U-Boot] [PATCH 02/12] arm: socfpga: Sync Cyclone V DK pinmux configuration

2014-12-31 Thread Marek Vasut 
Sync SoCFPGA Cyclone V development kit pinmux configuration with
Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR).

Signed-off-by: Marek Vasut ma...@denx.de
Cc: Chin Liang See cl...@opensource.altera.com
Cc: Dinh Nguyen dingu...@opensource.altera.com
Cc: Pavel Machek pa...@denx.de
Cc: Stefan Roese s...@denx.de
Cc: Vince Bridgers vbrid...@opensource.altera.com
---
 board/altera/socfpga/pinmux_config.c | 188 +--
 board/altera/socfpga/pinmux_config.h |  14 +--
 2 files changed, 101 insertions(+), 101 deletions(-)

diff --git a/board/altera/socfpga/pinmux_config.c 
b/board/altera/socfpga/pinmux_config.c
index 8b09005..b124768 100644
--- a/board/altera/socfpga/pinmux_config.c
+++ b/board/altera/socfpga/pinmux_config.c
@@ -4,100 +4,100 @@
 
 /* pin mux configuration data */
 unsigned long sys_mgr_init_table[CONFIG_HPS_PINMUX_NUM] = {
-   0, /* EMACIO0 - Unused */
-   2, /* EMACIO1 - USB */
-   2, /* EMACIO2 - USB */
-   2, /* EMACIO3 - USB */
-   2, /* EMACIO4 - USB */
-   2, /* EMACIO5 - USB */
-   2, /* EMACIO6 - USB */
-   2, /* EMACIO7 - USB */
-   2, /* EMACIO8 - USB */
-   0, /* EMACIO9 - Unused */
-   2, /* EMACIO10 - USB */
-   2, /* EMACIO11 - USB */
-   2, /* EMACIO12 - USB */
-   2, /* EMACIO13 - USB */
-   0, /* EMACIO14 - N/A */
-   0, /* EMACIO15 - N/A */
-   0, /* EMACIO16 - N/A */
-   0, /* EMACIO17 - N/A */
-   0, /* EMACIO18 - N/A */
-   0, /* EMACIO19 - N/A */
-   3, /* FLASHIO0 - SDMMC */
-   3, /* FLASHIO1 - SDMMC */
-   3, /* FLASHIO2 - SDMMC */
-   3, /* FLASHIO3 - SDMMC */
-   0, /* FLASHIO4 - SDMMC */
-   0, /* FLASHIO5 - SDMMC */
-   0, /* FLASHIO6 - SDMMC */
-   0, /* FLASHIO7 - SDMMC */
-   0, /* FLASHIO8 - SDMMC */
-   3, /* FLASHIO9 - SDMMC */
-   3, /* FLASHIO10 - SDMMC */
-   3, /* FLASHIO11 - SDMMC */
-   3, /* GENERALIO0 - TRACE */
-   3, /* GENERALIO1 - TRACE */
-   3, /* GENERALIO2 - TRACE */
-   3, /* GENERALIO3 - TRACE  */
-   3, /* GENERALIO4 - TRACE  */
-   3, /* GENERALIO5 - TRACE  */
-   3, /* GENERALIO6 - TRACE  */
-   3, /* GENERALIO7 - TRACE  */
-   3, /* GENERALIO8 - TRACE  */
-   3, /* GENERALIO9 - SPIM0 */
-   3, /* GENERALIO10 - SPIM0 */
-   3, /* GENERALIO11 - SPIM0 */
-   3, /* GENERALIO12 - SPIM0 */
-   2, /* GENERALIO13 - CAN0 */
-   2, /* GENERALIO14 - CAN0 */
-   3, /* GENERALIO15 - I2C0 */
-   3, /* GENERALIO16 - I2C0 */
-   2, /* GENERALIO17 - UART0 */
-   2, /* GENERALIO18 - UART0 */
-   0, /* GENERALIO19 - N/A */
-   0, /* GENERALIO20 - N/A */
-   0, /* GENERALIO21 - N/A */
-   0, /* GENERALIO22 - N/A */
-   0, /* GENERALIO23 - N/A */
-   0, /* GENERALIO24 - N/A */
-   0, /* GENERALIO25 - N/A */
-   0, /* GENERALIO26 - N/A */
-   0, /* GENERALIO27 - N/A */
-   0, /* GENERALIO28 - N/A */
-   0, /* GENERALIO29 - N/A */
-   0, /* GENERALIO30 - N/A */
-   0, /* GENERALIO31 - N/A */
-   2, /* MIXED1IO0 - EMAC */
-   2, /* MIXED1IO1 - EMAC */
-   2, /* MIXED1IO2 - EMAC */
-   2, /* MIXED1IO3 - EMAC */
-   2, /* MIXED1IO4 - EMAC */
-   2, /* MIXED1IO5 - EMAC */
-   2, /* MIXED1IO6 - EMAC */
-   2, /* MIXED1IO7 - EMAC */
-   2, /* MIXED1IO8 - EMAC */
-   2, /* MIXED1IO9 - EMAC */
-   2, /* MIXED1IO10 - EMAC */
-   2, /* MIXED1IO11 - EMAC */
-   2, /* MIXED1IO12 - EMAC */
-   2, /* MIXED1IO13 - EMAC */
-   0, /* MIXED1IO14 - Unused */
-   3, /* MIXED1IO15 - QSPI */
-   3, /* MIXED1IO16 - QSPI */
-   3, /* MIXED1IO17 - QSPI */
-   3, /* MIXED1IO18 - QSPI */
-   3, /* MIXED1IO19 - QSPI */
-   3, /* MIXED1IO20 - QSPI */
-   0, /* MIXED1IO21 - GPIO */
-   0, /* MIXED2IO0 - N/A */
-   0, /* MIXED2IO1 - N/A */
-   0, /* MIXED2IO2 - N/A */
-   0, /* MIXED2IO3 - N/A */
-   0, /* MIXED2IO4 - N/A */
-   0, /* MIXED2IO5 - N/A */
-   0, /* MIXED2IO6 - N/A */
-   0, /* MIXED2IO7 - N/A */
+   3, /* EMACIO0 */
+   3, /* EMACIO1 */
+   3, /* EMACIO2 */
+   3, /* EMACIO3 */
+   3, /* EMACIO4 */
+   3, /* EMACIO5 */
+   3, /* EMACIO6 */
+   3, /* EMACIO7 */
+   3, /* EMACIO8 */
+   3, /* EMACIO9 */
+   3, /* EMACIO10 */
+   3, /* EMACIO11 */
+   3, /* EMACIO12 */
+   3, /* EMACIO13 */
+   0, /* EMACIO14 */
+   0, /* EMACIO15 */
+   0, /* EMACIO16 */
+   0, /* EMACIO17 */
+   0, /* EMACIO18 */
+   0, /* EMACIO19 */
+   3, /* FLASHIO0 */
+   0, /* FLASHIO1 */
+   3, /* FLASHIO2 */
+   3, /* FLASHIO3 */
+   3, /* FLASHIO4 */
+   3, /* FLASHIO5 */
+   3, /* FLASHIO6 */
+   3, /* FLASHIO7 */
+   0, /* FLASHIO8 */
+   3, /* FLASHIO9 */
+   3, /* FLASHIO10 */
+   3, /* FLASHIO11 */
+   0, /* GENERALIO0 */
+   1, /* GENERALIO1 */
+