Re: [U-Boot] [PATCH 03/19] arm: socfpga: Add driver for flash to program FPGA

[Chee, Tien Fong]

On Rab, 2017-09-06 at 09:10 +0200, Marek Vasut wrote:
> On 09/06/2017 07:06 AM, Chee, Tien Fong wrote:
> [...]
> > 
> > > 
> > > > 
> > > > > 
> > > > > > 
> > > > > > The BSP tool is used to describe internal FPGA in SOCFPGA.
> > > > > > Other
> > > > > > external FPGAs other than SOCFPGA itself, it can be
> > > > > > programmed
> > > > > > through
> > > > > > U-boot.
> > > > > The BSP tool is broken if it generates broken DT, do I have
> > > > > to
> > > > > repeat
> > > > > myself ?
> > > > > 
> > > > BSP tool is only generate the RBF filename for FPGA inside
> > > > SOCFPGA.
> > > > Multiple external FPGA are configured through U-boot.
> > > What happens if you have FPGA connector over SPI ?
> > > 
> > I assume you are saying FPGA connected to EPCQ
> No, I mean FPGA connected over SPI bus.
> 
> > 
> > , and this is one of the
> > external FPGA configuration, like PCIE. For any external FPGA
> > configuration, FPGA itself/external HOST would get the FPGA data
> > from
> > storage such as EPCQ and configuring the FPGA without
> > HPS/Bootloader
> > intervine. SPL/U-boot would skip the FPGA configuration process
> > when
> > they see the mode is set to external FPGA configuration.
> > 
> > I know you want a DT to describe all FPGAs with FPGA node and their
> > own
> > data filename in every node. But, at this moment, all external
> > FPGAs
> > chip other than SOCFPGA itself are configured through U-boot(script 
> > &
> > env variable), or external FPGA configuration method.
> I want DT which describes hardware and is not misdesigned crap.
> Just because the BSP tool is broken does not mean I can allow
> upstream
> to accept that, no way.
> 
> > 
> > How about i just create a FPGA node for SOCFPGA, with FPGA data
> > filename within the node?
> Isn't that what the FPGA manager in mainline Linux does already ?
> 
Yeah, i will port from Linux DTS, and filenames added into the node.
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Re: [U-Boot] [PATCH 03/19] arm: socfpga: Add driver for flash to program FPGA

[Marek Vasut]

On 09/06/2017 07:06 AM, Chee, Tien Fong wrote:
[...]
> The BSP tool is used to describe internal FPGA in SOCFPGA.
> Other
> external FPGAs other than SOCFPGA itself, it can be programmed
> through
> U-boot.
 The BSP tool is broken if it generates broken DT, do I have to
 repeat
 myself ?

>>> BSP tool is only generate the RBF filename for FPGA inside SOCFPGA.
>>> Multiple external FPGA are configured through U-boot.
>> What happens if you have FPGA connector over SPI ?
>>
> I assume you are saying FPGA connected to EPCQ

No, I mean FPGA connected over SPI bus.

>, and this is one of the
> external FPGA configuration, like PCIE. For any external FPGA
> configuration, FPGA itself/external HOST would get the FPGA data from
> storage such as EPCQ and configuring the FPGA without HPS/Bootloader
> intervine. SPL/U-boot would skip the FPGA configuration process when
> they see the mode is set to external FPGA configuration.
> 
> I know you want a DT to describe all FPGAs with FPGA node and their own
> data filename in every node. But, at this moment, all external FPGAs
> chip other than SOCFPGA itself are configured through U-boot(script &
> env variable), or external FPGA configuration method.

I want DT which describes hardware and is not misdesigned crap.
Just because the BSP tool is broken does not mean I can allow upstream
to accept that, no way.

> How about i just create a FPGA node for SOCFPGA, with FPGA data
> filename within the node?

Isn't that what the FPGA manager in mainline Linux does already ?

-- 
Best regards,
Marek Vasut
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Re: [U-Boot] [PATCH 03/19] arm: socfpga: Add driver for flash to program FPGA

[Chee, Tien Fong]

On Sel, 2017-09-05 at 11:36 +0200, Marek Vasut wrote:
> On 09/05/2017 11:23 AM, Chee, Tien Fong wrote:
> > 
> > On Sel, 2017-09-05 at 11:04 +0200, Marek Vasut wrote:
> > > 
> > > On 09/05/2017 07:53 AM, Chee, Tien Fong wrote:
> > > > 
> > > > 
> > > > On Isn, 2017-09-04 at 11:39 +0200, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 09/04/2017 09:08 AM, Chee, Tien Fong wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > On Rab, 2017-08-30 at 10:52 +0200, Marek Vasut wrote:
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > On 08/30/2017 10:05 AM, Chee, Tien Fong wrote:
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > On Sel, 2017-08-29 at 13:55 +0200, Marek Vasut wrote:
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > 
> > > > > > > > > On 08/29/2017 12:45 PM, tien.fong.c...@intel.com
> > > > > > > > > wrote:
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > 
> > > > > > > > > > From: Tien Fong Chee 
> > > > > > > > > > 
> > > > > > > > > > This driver handles FPGA program operation from
> > > > > > > > > > flash
> > > > > > > > > > loading
> > > > > > > > > > RBF to memory and then to program FPGA.
> > > > > > > > > > 
> > > > > > > > > > Signed-off-by: Tien Fong Chee  > > > > > > > > > .com
> > > > > > > > > > > 
> > > > > > > > > > > 
> > > > > > > > > > ---
> > > > > > > > > >  .../include/mach/fpga_manager_arria10.h   
> > > > > > > > > >  |  
> > > > > > > > > >  27
> > > > > > > > > > ++
> > > > > > > > > >  drivers/fpga/socfpga_arria10.c
> > > > > > > > > >  |  
> > > > > > > > > > 386
> > > > > > > > > > +++-
> > > > > > > > > >  include/altera.h  
> > > > > > > > > >  |  
> > > > > > > > > >   6
> > > > > > > > > > +
> > > > > > > > > >  include/configs/socfpga_common.h  
> > > > > > > > > >  |  
> > > > > > > > > >   4
> > > > > > > > > > +
> > > > > > > > > >  4 files changed, 422 insertions(+), 1 deletions(-)
> > > > > > > > > > 
> > > > > > > > > > diff --git a/arch/arm/mach-
> > > > > > > > > > socfpga/include/mach/fpga_manager_arria10.h
> > > > > > > > > > b/arch/arm/mach-
> > > > > > > > > > socfpga/include/mach/fpga_manager_arria10.h
> > > > > > > > > > index 9cbf696..93a9122 100644
> > > > > > > > > > --- a/arch/arm/mach-
> > > > > > > > > > socfpga/include/mach/fpga_manager_arria10.h
> > > > > > > > > > +++ b/arch/arm/mach-
> > > > > > > > > > socfpga/include/mach/fpga_manager_arria10.h
> > > > > > > > > > @@ -8,6 +8,8 @@
> > > > > > > > > >  #ifndef _FPGA_MANAGER_ARRIA10_H_
> > > > > > > > > >  #define _FPGA_MANAGER_ARRIA10_H_
> > > > > > > > > >  
> > > > > > > > > > +#include 
> > > > > > > > > > +
> > > > > > > > > >  #define
> > > > > > > > > > ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK   
> > > > > > > > > > 
> > > > > > > > > > BIT(0)
> > > > > > > > > >  #define
> > > > > > > > > > ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK
> > > > > > > > > > 
> > > > > > > > > > BIT(1)
> > > > > > > > > >  #define
> > > > > > > > > > ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK    
> > > > > > > > > > 
> > > > > > > > > > BIT(2)
> > > > > > > > > > @@ -89,11 +91,36 @@ struct socfpga_fpga_manager {
> > > > > > > > > >     u32  imgcfg_fifo_status;
> > > > > > > > > >  };
> > > > > > > > > >  
> > > > > > > > > > +#if defined(CONFIG_CMD_FPGA_LOADFS)
> > > > > > > > > > +enum rbf_type {unknown, periph_section,
> > > > > > > > > > core_section};
> > > > > > > > > > +enum rbf_security {invalid, unencrypted,
> > > > > > > > > > encrypted};
> > > > > > > > > > +
> > > > > > > > > > +struct rbf_info {
> > > > > > > > > > +   enum rbf_type section;
> > > > > > > > > > +   enum rbf_security security;
> > > > > > > > > > +};
> > > > > > > > > > +
> > > > > > > > > > +struct flash_info {
> > > > > > > > > > +   char *interface;
> > > > > > > > > > +   char *dev_part;
> > > > > > > > > > +   char *filename;
> > > > > > > > > > +   int fstype;
> > > > > > > > > > +   u32 remaining;
> > > > > > > > > > +   u32 flash_offset;
> > > > > > > > > > +   struct rbf_info rbfinfo;
> > > > > > > > > > +   struct image_header header;
> > > > > > > > > > +};
> > > > > > > > > > +#endif
> > > > > > > > > > +
> > > > > > > > > >  /* Functions */
> > > > > > > > > >  int fpgamgr_program_init(u32 * rbf_data, size_t
> > > > > > > > > > rbf_size);
> > > > > > > > > >  int fpgamgr_program_finish(void);
> > > > > > > > > >  int is_fpgamgr_user_mode(void);
> > > > > > > > > >  int fpgamgr_wait_early_user_mode(void);
> > > > > > > > > > +#if defined(CONFIG_CMD_FPGA_LOADFS)
> > > > > > > > > > +const char *get_cff_filename(const void *fdt, int
> > > > > > > > > > *len,
> > > > > > > > > > u32
> > > > > > > > > > core);
> > > > > > > > > > +const char *get_cff_devpart(const void *fdt, int
> > > > > > > > > > *len);
> > > > > > > > 

Re: [U-Boot] [PATCH 03/19] arm: socfpga: Add driver for flash to program FPGA

[Marek Vasut]

On 09/05/2017 11:23 AM, Chee, Tien Fong wrote:
> On Sel, 2017-09-05 at 11:04 +0200, Marek Vasut wrote:
>> On 09/05/2017 07:53 AM, Chee, Tien Fong wrote:
>>>
>>> On Isn, 2017-09-04 at 11:39 +0200, Marek Vasut wrote:

 On 09/04/2017 09:08 AM, Chee, Tien Fong wrote:
>
>
> On Rab, 2017-08-30 at 10:52 +0200, Marek Vasut wrote:
>>
>>
>> On 08/30/2017 10:05 AM, Chee, Tien Fong wrote:
>>>
>>>
>>>
>>> On Sel, 2017-08-29 at 13:55 +0200, Marek Vasut wrote:



 On 08/29/2017 12:45 PM, tien.fong.c...@intel.com wrote:
>
>
>
>
> From: Tien Fong Chee 
>
> This driver handles FPGA program operation from flash
> loading
> RBF to memory and then to program FPGA.
>
> Signed-off-by: Tien Fong Chee >
> ---
>  .../include/mach/fpga_manager_arria10.h|  
>  27
> ++
>  drivers/fpga/socfpga_arria10.c |  
> 386
> +++-
>  include/altera.h   |  
>   6
> +
>  include/configs/socfpga_common.h   |  
>   4
> +
>  4 files changed, 422 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-
> socfpga/include/mach/fpga_manager_arria10.h
> b/arch/arm/mach-
> socfpga/include/mach/fpga_manager_arria10.h
> index 9cbf696..93a9122 100644
> --- a/arch/arm/mach-
> socfpga/include/mach/fpga_manager_arria10.h
> +++ b/arch/arm/mach-
> socfpga/include/mach/fpga_manager_arria10.h
> @@ -8,6 +8,8 @@
>  #ifndef _FPGA_MANAGER_ARRIA10_H_
>  #define _FPGA_MANAGER_ARRIA10_H_
>  
> +#include 
> +
>  #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK
>   
> BIT(0)
>  #define
> ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK
>   
> BIT(1)
>  #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK 
>   
> BIT(2)
> @@ -89,11 +91,36 @@ struct socfpga_fpga_manager {
>   u32  imgcfg_fifo_status;
>  };
>  
> +#if defined(CONFIG_CMD_FPGA_LOADFS)
> +enum rbf_type {unknown, periph_section, core_section};
> +enum rbf_security {invalid, unencrypted, encrypted};
> +
> +struct rbf_info {
> + enum rbf_type section;
> + enum rbf_security security;
> +};
> +
> +struct flash_info {
> + char *interface;
> + char *dev_part;
> + char *filename;
> + int fstype;
> + u32 remaining;
> + u32 flash_offset;
> + struct rbf_info rbfinfo;
> + struct image_header header;
> +};
> +#endif
> +
>  /* Functions */
>  int fpgamgr_program_init(u32 * rbf_data, size_t
> rbf_size);
>  int fpgamgr_program_finish(void);
>  int is_fpgamgr_user_mode(void);
>  int fpgamgr_wait_early_user_mode(void);
> +#if defined(CONFIG_CMD_FPGA_LOADFS)
> +const char *get_cff_filename(const void *fdt, int
> *len,
> u32
> core);
> +const char *get_cff_devpart(const void *fdt, int
> *len);
> +#endif
>  
>  #endif /* __ASSEMBLY__ */
>  
> diff --git a/drivers/fpga/socfpga_arria10.c
> b/drivers/fpga/socfpga_arria10.c
> index 5c1a68a..90c55e5 100644
> --- a/drivers/fpga/socfpga_arria10.c
> +++ b/drivers/fpga/socfpga_arria10.c
> @@ -13,6 +13,12 @@
>  #include 
>  #include 
>  #include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
>  #include 
>  #include 
>  
> @@ -22,6 +28,10 @@
>  #define COMPRESSION_OFFSET   229
>  #define FPGA_TIMEOUT_MSEC1000  /* timeout in
> ms */
>  #define FPGA_TIMEOUT_CNT 0x100
> +#define RBF_UNENCRYPTED  0xa65c
> +#define RBF_ENCRYPTED0xa65d
> +#define ARRIA10RBF_PERIPH0x0001
> +#define ARRIA10RBF_CORE  0x8001
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> @@ -118,7 +128,7 @@ static int
> wait_for_nconfig_pin_and_nstatus_pin(void)
>   return wait_for_bit(__func__,
>   _manager_base-
>>
>> imgcfg_stat,
>   mask,
> - false, FPGA_TIMEOUT_MSEC,
> false);
> + true, 

Re: [U-Boot] [PATCH 03/19] arm: socfpga: Add driver for flash to program FPGA

[Chee, Tien Fong]

On Sel, 2017-09-05 at 11:04 +0200, Marek Vasut wrote:
> On 09/05/2017 07:53 AM, Chee, Tien Fong wrote:
> > 
> > On Isn, 2017-09-04 at 11:39 +0200, Marek Vasut wrote:
> > > 
> > > On 09/04/2017 09:08 AM, Chee, Tien Fong wrote:
> > > > 
> > > > 
> > > > On Rab, 2017-08-30 at 10:52 +0200, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 08/30/2017 10:05 AM, Chee, Tien Fong wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > On Sel, 2017-08-29 at 13:55 +0200, Marek Vasut wrote:
> > > > > > > 
> > > > > > > 
> > > > > > > 
> > > > > > > On 08/29/2017 12:45 PM, tien.fong.c...@intel.com wrote:
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > 
> > > > > > > > From: Tien Fong Chee 
> > > > > > > > 
> > > > > > > > This driver handles FPGA program operation from flash
> > > > > > > > loading
> > > > > > > > RBF to memory and then to program FPGA.
> > > > > > > > 
> > > > > > > > Signed-off-by: Tien Fong Chee  > > > > > > > >
> > > > > > > > ---
> > > > > > > >  .../include/mach/fpga_manager_arria10.h|  
> > > > > > > >  27
> > > > > > > > ++
> > > > > > > >  drivers/fpga/socfpga_arria10.c |  
> > > > > > > > 386
> > > > > > > > +++-
> > > > > > > >  include/altera.h   |  
> > > > > > > >   6
> > > > > > > > +
> > > > > > > >  include/configs/socfpga_common.h   |  
> > > > > > > >   4
> > > > > > > > +
> > > > > > > >  4 files changed, 422 insertions(+), 1 deletions(-)
> > > > > > > > 
> > > > > > > > diff --git a/arch/arm/mach-
> > > > > > > > socfpga/include/mach/fpga_manager_arria10.h
> > > > > > > > b/arch/arm/mach-
> > > > > > > > socfpga/include/mach/fpga_manager_arria10.h
> > > > > > > > index 9cbf696..93a9122 100644
> > > > > > > > --- a/arch/arm/mach-
> > > > > > > > socfpga/include/mach/fpga_manager_arria10.h
> > > > > > > > +++ b/arch/arm/mach-
> > > > > > > > socfpga/include/mach/fpga_manager_arria10.h
> > > > > > > > @@ -8,6 +8,8 @@
> > > > > > > >  #ifndef _FPGA_MANAGER_ARRIA10_H_
> > > > > > > >  #define _FPGA_MANAGER_ARRIA10_H_
> > > > > > > >  
> > > > > > > > +#include 
> > > > > > > > +
> > > > > > > >  #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK  
> > > > > > > > 
> > > > > > > > BIT(0)
> > > > > > > >  #define
> > > > > > > > ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK
> > > > > > > > 
> > > > > > > > BIT(1)
> > > > > > > >  #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK   
> > > > > > > > 
> > > > > > > > BIT(2)
> > > > > > > > @@ -89,11 +91,36 @@ struct socfpga_fpga_manager {
> > > > > > > >     u32  imgcfg_fifo_status;
> > > > > > > >  };
> > > > > > > >  
> > > > > > > > +#if defined(CONFIG_CMD_FPGA_LOADFS)
> > > > > > > > +enum rbf_type {unknown, periph_section, core_section};
> > > > > > > > +enum rbf_security {invalid, unencrypted, encrypted};
> > > > > > > > +
> > > > > > > > +struct rbf_info {
> > > > > > > > +   enum rbf_type section;
> > > > > > > > +   enum rbf_security security;
> > > > > > > > +};
> > > > > > > > +
> > > > > > > > +struct flash_info {
> > > > > > > > +   char *interface;
> > > > > > > > +   char *dev_part;
> > > > > > > > +   char *filename;
> > > > > > > > +   int fstype;
> > > > > > > > +   u32 remaining;
> > > > > > > > +   u32 flash_offset;
> > > > > > > > +   struct rbf_info rbfinfo;
> > > > > > > > +   struct image_header header;
> > > > > > > > +};
> > > > > > > > +#endif
> > > > > > > > +
> > > > > > > >  /* Functions */
> > > > > > > >  int fpgamgr_program_init(u32 * rbf_data, size_t
> > > > > > > > rbf_size);
> > > > > > > >  int fpgamgr_program_finish(void);
> > > > > > > >  int is_fpgamgr_user_mode(void);
> > > > > > > >  int fpgamgr_wait_early_user_mode(void);
> > > > > > > > +#if defined(CONFIG_CMD_FPGA_LOADFS)
> > > > > > > > +const char *get_cff_filename(const void *fdt, int
> > > > > > > > *len,
> > > > > > > > u32
> > > > > > > > core);
> > > > > > > > +const char *get_cff_devpart(const void *fdt, int
> > > > > > > > *len);
> > > > > > > > +#endif
> > > > > > > >  
> > > > > > > >  #endif /* __ASSEMBLY__ */
> > > > > > > >  
> > > > > > > > diff --git a/drivers/fpga/socfpga_arria10.c
> > > > > > > > b/drivers/fpga/socfpga_arria10.c
> > > > > > > > index 5c1a68a..90c55e5 100644
> > > > > > > > --- a/drivers/fpga/socfpga_arria10.c
> > > > > > > > +++ b/drivers/fpga/socfpga_arria10.c
> > > > > > > > @@ -13,6 +13,12 @@
> > > > > > > >  #include 
> > > > > > > >  #include 
> > > > > > > >  #include 
> > > > > > > > +#include 
> > > > > > > > +#include 
> > > > > > > > +#include 
> > > > > > > > +#include 
> > > > > > > > +#include 
> > > > > > > > +#include 
> > > > > > > >  #include 
> > > > > > > >  #include 
> > > > > > > >  
> > > > > > > > @@ -22,6 +28,10 @@
> > > > > > > >  #define COMPRESSION_OFFSET 229
> > > > > > > >  #define FPGA_TIMEOUT_MSEC  1000  /* timeout in
> > > > 

Re: [U-Boot] [PATCH 03/19] arm: socfpga: Add driver for flash to program FPGA

[Marek Vasut]

On 09/05/2017 07:53 AM, Chee, Tien Fong wrote:
> On Isn, 2017-09-04 at 11:39 +0200, Marek Vasut wrote:
>> On 09/04/2017 09:08 AM, Chee, Tien Fong wrote:
>>>
>>> On Rab, 2017-08-30 at 10:52 +0200, Marek Vasut wrote:

 On 08/30/2017 10:05 AM, Chee, Tien Fong wrote:
>
>
> On Sel, 2017-08-29 at 13:55 +0200, Marek Vasut wrote:
>>
>>
>> On 08/29/2017 12:45 PM, tien.fong.c...@intel.com wrote:
>>>
>>>
>>>
>>> From: Tien Fong Chee 
>>>
>>> This driver handles FPGA program operation from flash
>>> loading
>>> RBF to memory and then to program FPGA.
>>>
>>> Signed-off-by: Tien Fong Chee 
>>> ---
>>>  .../include/mach/fpga_manager_arria10.h|   27
>>> ++
>>>  drivers/fpga/socfpga_arria10.c |  386
>>> +++-
>>>  include/altera.h   |6
>>> +
>>>  include/configs/socfpga_common.h   |4
>>> +
>>>  4 files changed, 422 insertions(+), 1 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-
>>> socfpga/include/mach/fpga_manager_arria10.h
>>> b/arch/arm/mach-
>>> socfpga/include/mach/fpga_manager_arria10.h
>>> index 9cbf696..93a9122 100644
>>> --- a/arch/arm/mach-
>>> socfpga/include/mach/fpga_manager_arria10.h
>>> +++ b/arch/arm/mach-
>>> socfpga/include/mach/fpga_manager_arria10.h
>>> @@ -8,6 +8,8 @@
>>>  #ifndef _FPGA_MANAGER_ARRIA10_H_
>>>  #define _FPGA_MANAGER_ARRIA10_H_
>>>  
>>> +#include 
>>> +
>>>  #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK  
>>> 
>>> BIT(0)
>>>  #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK
>>> 
>>> BIT(1)
>>>  #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK   
>>> 
>>> BIT(2)
>>> @@ -89,11 +91,36 @@ struct socfpga_fpga_manager {
>>> u32  imgcfg_fifo_status;
>>>  };
>>>  
>>> +#if defined(CONFIG_CMD_FPGA_LOADFS)
>>> +enum rbf_type {unknown, periph_section, core_section};
>>> +enum rbf_security {invalid, unencrypted, encrypted};
>>> +
>>> +struct rbf_info {
>>> +   enum rbf_type section;
>>> +   enum rbf_security security;
>>> +};
>>> +
>>> +struct flash_info {
>>> +   char *interface;
>>> +   char *dev_part;
>>> +   char *filename;
>>> +   int fstype;
>>> +   u32 remaining;
>>> +   u32 flash_offset;
>>> +   struct rbf_info rbfinfo;
>>> +   struct image_header header;
>>> +};
>>> +#endif
>>> +
>>>  /* Functions */
>>>  int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
>>>  int fpgamgr_program_finish(void);
>>>  int is_fpgamgr_user_mode(void);
>>>  int fpgamgr_wait_early_user_mode(void);
>>> +#if defined(CONFIG_CMD_FPGA_LOADFS)
>>> +const char *get_cff_filename(const void *fdt, int *len,
>>> u32
>>> core);
>>> +const char *get_cff_devpart(const void *fdt, int *len);
>>> +#endif
>>>  
>>>  #endif /* __ASSEMBLY__ */
>>>  
>>> diff --git a/drivers/fpga/socfpga_arria10.c
>>> b/drivers/fpga/socfpga_arria10.c
>>> index 5c1a68a..90c55e5 100644
>>> --- a/drivers/fpga/socfpga_arria10.c
>>> +++ b/drivers/fpga/socfpga_arria10.c
>>> @@ -13,6 +13,12 @@
>>>  #include 
>>>  #include 
>>>  #include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>>  #include 
>>>  #include 
>>>  
>>> @@ -22,6 +28,10 @@
>>>  #define COMPRESSION_OFFSET 229
>>>  #define FPGA_TIMEOUT_MSEC  1000  /* timeout in ms */
>>>  #define FPGA_TIMEOUT_CNT   0x100
>>> +#define RBF_UNENCRYPTED0xa65c
>>> +#define RBF_ENCRYPTED  0xa65d
>>> +#define ARRIA10RBF_PERIPH  0x0001
>>> +#define ARRIA10RBF_CORE0x8001
>>>  
>>>  DECLARE_GLOBAL_DATA_PTR;
>>>  
>>> @@ -118,7 +128,7 @@ static int
>>> wait_for_nconfig_pin_and_nstatus_pin(void)
>>> return wait_for_bit(__func__,
>>> _manager_base-
 imgcfg_stat,
>>> mask,
>>> -   false, FPGA_TIMEOUT_MSEC,
>>> false);
>>> +   true, FPGA_TIMEOUT_MSEC,
>>> false);
>>>  }
>>>  
>>>  static int wait_for_f2s_nstatus_pin(unsigned long value)
>>> @@ -453,6 +463,281 @@ int fpgamgr_program_finish(void)
>>> return 0;
>>>  }
>>>  
>>> +#if defined(CONFIG_CMD_FPGA_LOADFS)
>>> +const char *get_cff_filename(const void *fdt, int *len,
>>> u32
>>> core)
>>> +{
>>> +   const char *cff_filename = NULL;
>>> +   const char *cell;
>>> +   int nodeoffset;
>>> +   

Re: [U-Boot] [PATCH 03/19] arm: socfpga: Add driver for flash to program FPGA

[Chee, Tien Fong]

On Isn, 2017-09-04 at 11:39 +0200, Marek Vasut wrote:
> On 09/04/2017 09:08 AM, Chee, Tien Fong wrote:
> > 
> > On Rab, 2017-08-30 at 10:52 +0200, Marek Vasut wrote:
> > > 
> > > On 08/30/2017 10:05 AM, Chee, Tien Fong wrote:
> > > > 
> > > > 
> > > > On Sel, 2017-08-29 at 13:55 +0200, Marek Vasut wrote:
> > > > > 
> > > > > 
> > > > > On 08/29/2017 12:45 PM, tien.fong.c...@intel.com wrote:
> > > > > > 
> > > > > > 
> > > > > > 
> > > > > > From: Tien Fong Chee 
> > > > > > 
> > > > > > This driver handles FPGA program operation from flash
> > > > > > loading
> > > > > > RBF to memory and then to program FPGA.
> > > > > > 
> > > > > > Signed-off-by: Tien Fong Chee 
> > > > > > ---
> > > > > >  .../include/mach/fpga_manager_arria10.h|   27
> > > > > > ++
> > > > > >  drivers/fpga/socfpga_arria10.c |  386
> > > > > > +++-
> > > > > >  include/altera.h   |6
> > > > > > +
> > > > > >  include/configs/socfpga_common.h   |4
> > > > > > +
> > > > > >  4 files changed, 422 insertions(+), 1 deletions(-)
> > > > > > 
> > > > > > diff --git a/arch/arm/mach-
> > > > > > socfpga/include/mach/fpga_manager_arria10.h
> > > > > > b/arch/arm/mach-
> > > > > > socfpga/include/mach/fpga_manager_arria10.h
> > > > > > index 9cbf696..93a9122 100644
> > > > > > --- a/arch/arm/mach-
> > > > > > socfpga/include/mach/fpga_manager_arria10.h
> > > > > > +++ b/arch/arm/mach-
> > > > > > socfpga/include/mach/fpga_manager_arria10.h
> > > > > > @@ -8,6 +8,8 @@
> > > > > >  #ifndef _FPGA_MANAGER_ARRIA10_H_
> > > > > >  #define _FPGA_MANAGER_ARRIA10_H_
> > > > > >  
> > > > > > +#include 
> > > > > > +
> > > > > >  #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK  
> > > > > > 
> > > > > > BIT(0)
> > > > > >  #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK
> > > > > > 
> > > > > > BIT(1)
> > > > > >  #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK   
> > > > > > 
> > > > > > BIT(2)
> > > > > > @@ -89,11 +91,36 @@ struct socfpga_fpga_manager {
> > > > > >     u32  imgcfg_fifo_status;
> > > > > >  };
> > > > > >  
> > > > > > +#if defined(CONFIG_CMD_FPGA_LOADFS)
> > > > > > +enum rbf_type {unknown, periph_section, core_section};
> > > > > > +enum rbf_security {invalid, unencrypted, encrypted};
> > > > > > +
> > > > > > +struct rbf_info {
> > > > > > +   enum rbf_type section;
> > > > > > +   enum rbf_security security;
> > > > > > +};
> > > > > > +
> > > > > > +struct flash_info {
> > > > > > +   char *interface;
> > > > > > +   char *dev_part;
> > > > > > +   char *filename;
> > > > > > +   int fstype;
> > > > > > +   u32 remaining;
> > > > > > +   u32 flash_offset;
> > > > > > +   struct rbf_info rbfinfo;
> > > > > > +   struct image_header header;
> > > > > > +};
> > > > > > +#endif
> > > > > > +
> > > > > >  /* Functions */
> > > > > >  int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
> > > > > >  int fpgamgr_program_finish(void);
> > > > > >  int is_fpgamgr_user_mode(void);
> > > > > >  int fpgamgr_wait_early_user_mode(void);
> > > > > > +#if defined(CONFIG_CMD_FPGA_LOADFS)
> > > > > > +const char *get_cff_filename(const void *fdt, int *len,
> > > > > > u32
> > > > > > core);
> > > > > > +const char *get_cff_devpart(const void *fdt, int *len);
> > > > > > +#endif
> > > > > >  
> > > > > >  #endif /* __ASSEMBLY__ */
> > > > > >  
> > > > > > diff --git a/drivers/fpga/socfpga_arria10.c
> > > > > > b/drivers/fpga/socfpga_arria10.c
> > > > > > index 5c1a68a..90c55e5 100644
> > > > > > --- a/drivers/fpga/socfpga_arria10.c
> > > > > > +++ b/drivers/fpga/socfpga_arria10.c
> > > > > > @@ -13,6 +13,12 @@
> > > > > >  #include 
> > > > > >  #include 
> > > > > >  #include 
> > > > > > +#include 
> > > > > > +#include 
> > > > > > +#include 
> > > > > > +#include 
> > > > > > +#include 
> > > > > > +#include 
> > > > > >  #include 
> > > > > >  #include 
> > > > > >  
> > > > > > @@ -22,6 +28,10 @@
> > > > > >  #define COMPRESSION_OFFSET 229
> > > > > >  #define FPGA_TIMEOUT_MSEC  1000  /* timeout in ms */
> > > > > >  #define FPGA_TIMEOUT_CNT   0x100
> > > > > > +#define RBF_UNENCRYPTED0xa65c
> > > > > > +#define RBF_ENCRYPTED  0xa65d
> > > > > > +#define ARRIA10RBF_PERIPH  0x0001
> > > > > > +#define ARRIA10RBF_CORE0x8001
> > > > > >  
> > > > > >  DECLARE_GLOBAL_DATA_PTR;
> > > > > >  
> > > > > > @@ -118,7 +128,7 @@ static int
> > > > > > wait_for_nconfig_pin_and_nstatus_pin(void)
> > > > > >     return wait_for_bit(__func__,
> > > > > >     _manager_base-
> > > > > > >imgcfg_stat,
> > > > > >     mask,
> > > > > > -   false, FPGA_TIMEOUT_MSEC,
> > > > > > false);
> > > > > > +   true, FPGA_TIMEOUT_MSEC,
> > > > > > false);
> > > > > >  }
> > > > > >  
> > > > > >  static int wait_for_f2s_nstatus_pin(unsigned long value)
> 

Re: [U-Boot] [PATCH 03/19] arm: socfpga: Add driver for flash to program FPGA

[Marek Vasut]

On 09/04/2017 09:08 AM, Chee, Tien Fong wrote:
> On Rab, 2017-08-30 at 10:52 +0200, Marek Vasut wrote:
>> On 08/30/2017 10:05 AM, Chee, Tien Fong wrote:
>>>
>>> On Sel, 2017-08-29 at 13:55 +0200, Marek Vasut wrote:

 On 08/29/2017 12:45 PM, tien.fong.c...@intel.com wrote:
>
>
> From: Tien Fong Chee 
>
> This driver handles FPGA program operation from flash loading
> RBF to memory and then to program FPGA.
>
> Signed-off-by: Tien Fong Chee 
> ---
>  .../include/mach/fpga_manager_arria10.h|   27 ++
>  drivers/fpga/socfpga_arria10.c |  386
> +++-
>  include/altera.h   |6 +
>  include/configs/socfpga_common.h   |4 +
>  4 files changed, 422 insertions(+), 1 deletions(-)
>
> diff --git a/arch/arm/mach-
> socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-
> socfpga/include/mach/fpga_manager_arria10.h
> index 9cbf696..93a9122 100644
> --- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> @@ -8,6 +8,8 @@
>  #ifndef _FPGA_MANAGER_ARRIA10_H_
>  #define _FPGA_MANAGER_ARRIA10_H_
>  
> +#include 
> +
>  #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK
> BIT(0)
>  #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK   
> BIT(1)
>  #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK 
> BIT(2)
> @@ -89,11 +91,36 @@ struct socfpga_fpga_manager {
>   u32  imgcfg_fifo_status;
>  };
>  
> +#if defined(CONFIG_CMD_FPGA_LOADFS)
> +enum rbf_type {unknown, periph_section, core_section};
> +enum rbf_security {invalid, unencrypted, encrypted};
> +
> +struct rbf_info {
> + enum rbf_type section;
> + enum rbf_security security;
> +};
> +
> +struct flash_info {
> + char *interface;
> + char *dev_part;
> + char *filename;
> + int fstype;
> + u32 remaining;
> + u32 flash_offset;
> + struct rbf_info rbfinfo;
> + struct image_header header;
> +};
> +#endif
> +
>  /* Functions */
>  int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
>  int fpgamgr_program_finish(void);
>  int is_fpgamgr_user_mode(void);
>  int fpgamgr_wait_early_user_mode(void);
> +#if defined(CONFIG_CMD_FPGA_LOADFS)
> +const char *get_cff_filename(const void *fdt, int *len, u32
> core);
> +const char *get_cff_devpart(const void *fdt, int *len);
> +#endif
>  
>  #endif /* __ASSEMBLY__ */
>  
> diff --git a/drivers/fpga/socfpga_arria10.c
> b/drivers/fpga/socfpga_arria10.c
> index 5c1a68a..90c55e5 100644
> --- a/drivers/fpga/socfpga_arria10.c
> +++ b/drivers/fpga/socfpga_arria10.c
> @@ -13,6 +13,12 @@
>  #include 
>  #include 
>  #include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
>  #include 
>  #include 
>  
> @@ -22,6 +28,10 @@
>  #define COMPRESSION_OFFSET   229
>  #define FPGA_TIMEOUT_MSEC1000  /* timeout in ms */
>  #define FPGA_TIMEOUT_CNT 0x100
> +#define RBF_UNENCRYPTED  0xa65c
> +#define RBF_ENCRYPTED0xa65d
> +#define ARRIA10RBF_PERIPH0x0001
> +#define ARRIA10RBF_CORE  0x8001
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> @@ -118,7 +128,7 @@ static int
> wait_for_nconfig_pin_and_nstatus_pin(void)
>   return wait_for_bit(__func__,
>   _manager_base->imgcfg_stat,
>   mask,
> - false, FPGA_TIMEOUT_MSEC, false);
> + true, FPGA_TIMEOUT_MSEC, false);
>  }
>  
>  static int wait_for_f2s_nstatus_pin(unsigned long value)
> @@ -453,6 +463,281 @@ int fpgamgr_program_finish(void)
>   return 0;
>  }
>  
> +#if defined(CONFIG_CMD_FPGA_LOADFS)
> +const char *get_cff_filename(const void *fdt, int *len, u32
> core)
> +{
> + const char *cff_filename = NULL;
> + const char *cell;
> + int nodeoffset;
> + nodeoffset = fdt_subnode_offset(fdt, 0, "chosen");
> +
> + if (nodeoffset >= 0) {
> + if (core)
> + cell = fdt_getprop(fdt,
> + nodeoffset,
> + "cffcore-file",
> + len);
> + else
> + cell = fdt_getprop(fdt, nodeoffset,
> "cff-
> file", len);
 This should be a property of the FPGA , not the system . You can
 have
 multiple FPGAs and then this would become a problem.

>>> This setting is for the only one FPGA inside our SoCFPGA.
>> You just said it 

Re: [U-Boot] [PATCH 03/19] arm: socfpga: Add driver for flash to program FPGA

[Chee, Tien Fong]

On Rab, 2017-08-30 at 10:52 +0200, Marek Vasut wrote:
> On 08/30/2017 10:05 AM, Chee, Tien Fong wrote:
> > 
> > On Sel, 2017-08-29 at 13:55 +0200, Marek Vasut wrote:
> > > 
> > > On 08/29/2017 12:45 PM, tien.fong.c...@intel.com wrote:
> > > > 
> > > > 
> > > > From: Tien Fong Chee 
> > > > 
> > > > This driver handles FPGA program operation from flash loading
> > > > RBF to memory and then to program FPGA.
> > > > 
> > > > Signed-off-by: Tien Fong Chee 
> > > > ---
> > > >  .../include/mach/fpga_manager_arria10.h|   27 ++
> > > >  drivers/fpga/socfpga_arria10.c |  386
> > > > +++-
> > > >  include/altera.h   |6 +
> > > >  include/configs/socfpga_common.h   |4 +
> > > >  4 files changed, 422 insertions(+), 1 deletions(-)
> > > > 
> > > > diff --git a/arch/arm/mach-
> > > > socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-
> > > > socfpga/include/mach/fpga_manager_arria10.h
> > > > index 9cbf696..93a9122 100644
> > > > --- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> > > > +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> > > > @@ -8,6 +8,8 @@
> > > >  #ifndef _FPGA_MANAGER_ARRIA10_H_
> > > >  #define _FPGA_MANAGER_ARRIA10_H_
> > > >  
> > > > +#include 
> > > > +
> > > >  #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK  
> > > > BIT(0)
> > > >  #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK 
> > > > BIT(1)
> > > >  #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK   
> > > > BIT(2)
> > > > @@ -89,11 +91,36 @@ struct socfpga_fpga_manager {
> > > >     u32  imgcfg_fifo_status;
> > > >  };
> > > >  
> > > > +#if defined(CONFIG_CMD_FPGA_LOADFS)
> > > > +enum rbf_type {unknown, periph_section, core_section};
> > > > +enum rbf_security {invalid, unencrypted, encrypted};
> > > > +
> > > > +struct rbf_info {
> > > > +   enum rbf_type section;
> > > > +   enum rbf_security security;
> > > > +};
> > > > +
> > > > +struct flash_info {
> > > > +   char *interface;
> > > > +   char *dev_part;
> > > > +   char *filename;
> > > > +   int fstype;
> > > > +   u32 remaining;
> > > > +   u32 flash_offset;
> > > > +   struct rbf_info rbfinfo;
> > > > +   struct image_header header;
> > > > +};
> > > > +#endif
> > > > +
> > > >  /* Functions */
> > > >  int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
> > > >  int fpgamgr_program_finish(void);
> > > >  int is_fpgamgr_user_mode(void);
> > > >  int fpgamgr_wait_early_user_mode(void);
> > > > +#if defined(CONFIG_CMD_FPGA_LOADFS)
> > > > +const char *get_cff_filename(const void *fdt, int *len, u32
> > > > core);
> > > > +const char *get_cff_devpart(const void *fdt, int *len);
> > > > +#endif
> > > >  
> > > >  #endif /* __ASSEMBLY__ */
> > > >  
> > > > diff --git a/drivers/fpga/socfpga_arria10.c
> > > > b/drivers/fpga/socfpga_arria10.c
> > > > index 5c1a68a..90c55e5 100644
> > > > --- a/drivers/fpga/socfpga_arria10.c
> > > > +++ b/drivers/fpga/socfpga_arria10.c
> > > > @@ -13,6 +13,12 @@
> > > >  #include 
> > > >  #include 
> > > >  #include 
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > > +#include 
> > > >  #include 
> > > >  #include 
> > > >  
> > > > @@ -22,6 +28,10 @@
> > > >  #define COMPRESSION_OFFSET 229
> > > >  #define FPGA_TIMEOUT_MSEC  1000  /* timeout in ms */
> > > >  #define FPGA_TIMEOUT_CNT   0x100
> > > > +#define RBF_UNENCRYPTED0xa65c
> > > > +#define RBF_ENCRYPTED  0xa65d
> > > > +#define ARRIA10RBF_PERIPH  0x0001
> > > > +#define ARRIA10RBF_CORE0x8001
> > > >  
> > > >  DECLARE_GLOBAL_DATA_PTR;
> > > >  
> > > > @@ -118,7 +128,7 @@ static int
> > > > wait_for_nconfig_pin_and_nstatus_pin(void)
> > > >     return wait_for_bit(__func__,
> > > >     _manager_base->imgcfg_stat,
> > > >     mask,
> > > > -   false, FPGA_TIMEOUT_MSEC, false);
> > > > +   true, FPGA_TIMEOUT_MSEC, false);
> > > >  }
> > > >  
> > > >  static int wait_for_f2s_nstatus_pin(unsigned long value)
> > > > @@ -453,6 +463,281 @@ int fpgamgr_program_finish(void)
> > > >     return 0;
> > > >  }
> > > >  
> > > > +#if defined(CONFIG_CMD_FPGA_LOADFS)
> > > > +const char *get_cff_filename(const void *fdt, int *len, u32
> > > > core)
> > > > +{
> > > > +   const char *cff_filename = NULL;
> > > > +   const char *cell;
> > > > +   int nodeoffset;
> > > > +   nodeoffset = fdt_subnode_offset(fdt, 0, "chosen");
> > > > +
> > > > +   if (nodeoffset >= 0) {
> > > > +   if (core)
> > > > +   cell = fdt_getprop(fdt,
> > > > +   nodeoffset,
> > > > +   "cffcore-file",
> > > > +

Re: [U-Boot] [PATCH 03/19] arm: socfpga: Add driver for flash to program FPGA

[Marek Vasut]

On 08/30/2017 10:05 AM, Chee, Tien Fong wrote:
> On Sel, 2017-08-29 at 13:55 +0200, Marek Vasut wrote:
>> On 08/29/2017 12:45 PM, tien.fong.c...@intel.com wrote:
>>>
>>> From: Tien Fong Chee 
>>>
>>> This driver handles FPGA program operation from flash loading
>>> RBF to memory and then to program FPGA.
>>>
>>> Signed-off-by: Tien Fong Chee 
>>> ---
>>>  .../include/mach/fpga_manager_arria10.h|   27 ++
>>>  drivers/fpga/socfpga_arria10.c |  386
>>> +++-
>>>  include/altera.h   |6 +
>>>  include/configs/socfpga_common.h   |4 +
>>>  4 files changed, 422 insertions(+), 1 deletions(-)
>>>
>>> diff --git a/arch/arm/mach-
>>> socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-
>>> socfpga/include/mach/fpga_manager_arria10.h
>>> index 9cbf696..93a9122 100644
>>> --- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
>>> +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
>>> @@ -8,6 +8,8 @@
>>>  #ifndef _FPGA_MANAGER_ARRIA10_H_
>>>  #define _FPGA_MANAGER_ARRIA10_H_
>>>  
>>> +#include 
>>> +
>>>  #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK  
>>> BIT(0)
>>>  #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK 
>>> BIT(1)
>>>  #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK   
>>> BIT(2)
>>> @@ -89,11 +91,36 @@ struct socfpga_fpga_manager {
>>> u32  imgcfg_fifo_status;
>>>  };
>>>  
>>> +#if defined(CONFIG_CMD_FPGA_LOADFS)
>>> +enum rbf_type {unknown, periph_section, core_section};
>>> +enum rbf_security {invalid, unencrypted, encrypted};
>>> +
>>> +struct rbf_info {
>>> +   enum rbf_type section;
>>> +   enum rbf_security security;
>>> +};
>>> +
>>> +struct flash_info {
>>> +   char *interface;
>>> +   char *dev_part;
>>> +   char *filename;
>>> +   int fstype;
>>> +   u32 remaining;
>>> +   u32 flash_offset;
>>> +   struct rbf_info rbfinfo;
>>> +   struct image_header header;
>>> +};
>>> +#endif
>>> +
>>>  /* Functions */
>>>  int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
>>>  int fpgamgr_program_finish(void);
>>>  int is_fpgamgr_user_mode(void);
>>>  int fpgamgr_wait_early_user_mode(void);
>>> +#if defined(CONFIG_CMD_FPGA_LOADFS)
>>> +const char *get_cff_filename(const void *fdt, int *len, u32 core);
>>> +const char *get_cff_devpart(const void *fdt, int *len);
>>> +#endif
>>>  
>>>  #endif /* __ASSEMBLY__ */
>>>  
>>> diff --git a/drivers/fpga/socfpga_arria10.c
>>> b/drivers/fpga/socfpga_arria10.c
>>> index 5c1a68a..90c55e5 100644
>>> --- a/drivers/fpga/socfpga_arria10.c
>>> +++ b/drivers/fpga/socfpga_arria10.c
>>> @@ -13,6 +13,12 @@
>>>  #include 
>>>  #include 
>>>  #include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>> +#include 
>>>  #include 
>>>  #include 
>>>  
>>> @@ -22,6 +28,10 @@
>>>  #define COMPRESSION_OFFSET 229
>>>  #define FPGA_TIMEOUT_MSEC  1000  /* timeout in ms */
>>>  #define FPGA_TIMEOUT_CNT   0x100
>>> +#define RBF_UNENCRYPTED0xa65c
>>> +#define RBF_ENCRYPTED  0xa65d
>>> +#define ARRIA10RBF_PERIPH  0x0001
>>> +#define ARRIA10RBF_CORE0x8001
>>>  
>>>  DECLARE_GLOBAL_DATA_PTR;
>>>  
>>> @@ -118,7 +128,7 @@ static int
>>> wait_for_nconfig_pin_and_nstatus_pin(void)
>>> return wait_for_bit(__func__,
>>> _manager_base->imgcfg_stat,
>>> mask,
>>> -   false, FPGA_TIMEOUT_MSEC, false);
>>> +   true, FPGA_TIMEOUT_MSEC, false);
>>>  }
>>>  
>>>  static int wait_for_f2s_nstatus_pin(unsigned long value)
>>> @@ -453,6 +463,281 @@ int fpgamgr_program_finish(void)
>>> return 0;
>>>  }
>>>  
>>> +#if defined(CONFIG_CMD_FPGA_LOADFS)
>>> +const char *get_cff_filename(const void *fdt, int *len, u32 core)
>>> +{
>>> +   const char *cff_filename = NULL;
>>> +   const char *cell;
>>> +   int nodeoffset;
>>> +   nodeoffset = fdt_subnode_offset(fdt, 0, "chosen");
>>> +
>>> +   if (nodeoffset >= 0) {
>>> +   if (core)
>>> +   cell = fdt_getprop(fdt,
>>> +   nodeoffset,
>>> +   "cffcore-file",
>>> +   len);
>>> +   else
>>> +   cell = fdt_getprop(fdt, nodeoffset, "cff-
>>> file", len);
>> This should be a property of the FPGA , not the system . You can have
>> multiple FPGAs and then this would become a problem.
>>
> This setting is for the only one FPGA inside our SoCFPGA.

You just said it yourself, it is for the only FPGA in your SOCFPGA ,
thus it is a property of the FPGA , not a chosen .

> For external
> multiple FPGAs programming, user is adviced to store the FPGA filename
> in environment variable and programming FPGA with fpga loadfs command.
> 
> Please note that, peripheral rbf and partition are required in SPL to
> set up DDR before booting to U-boot.

Re: [U-Boot] [PATCH 03/19] arm: socfpga: Add driver for flash to program FPGA

[Chee, Tien Fong]

On Sel, 2017-08-29 at 13:55 +0200, Marek Vasut wrote:
> On 08/29/2017 12:45 PM, tien.fong.c...@intel.com wrote:
> > 
> > From: Tien Fong Chee 
> > 
> > This driver handles FPGA program operation from flash loading
> > RBF to memory and then to program FPGA.
> > 
> > Signed-off-by: Tien Fong Chee 
> > ---
> >  .../include/mach/fpga_manager_arria10.h|   27 ++
> >  drivers/fpga/socfpga_arria10.c |  386
> > +++-
> >  include/altera.h   |6 +
> >  include/configs/socfpga_common.h   |4 +
> >  4 files changed, 422 insertions(+), 1 deletions(-)
> > 
> > diff --git a/arch/arm/mach-
> > socfpga/include/mach/fpga_manager_arria10.h b/arch/arm/mach-
> > socfpga/include/mach/fpga_manager_arria10.h
> > index 9cbf696..93a9122 100644
> > --- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> > +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> > @@ -8,6 +8,8 @@
> >  #ifndef _FPGA_MANAGER_ARRIA10_H_
> >  #define _FPGA_MANAGER_ARRIA10_H_
> >  
> > +#include 
> > +
> >  #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK  
> > BIT(0)
> >  #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK 
> > BIT(1)
> >  #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK   
> > BIT(2)
> > @@ -89,11 +91,36 @@ struct socfpga_fpga_manager {
> >     u32  imgcfg_fifo_status;
> >  };
> >  
> > +#if defined(CONFIG_CMD_FPGA_LOADFS)
> > +enum rbf_type {unknown, periph_section, core_section};
> > +enum rbf_security {invalid, unencrypted, encrypted};
> > +
> > +struct rbf_info {
> > +   enum rbf_type section;
> > +   enum rbf_security security;
> > +};
> > +
> > +struct flash_info {
> > +   char *interface;
> > +   char *dev_part;
> > +   char *filename;
> > +   int fstype;
> > +   u32 remaining;
> > +   u32 flash_offset;
> > +   struct rbf_info rbfinfo;
> > +   struct image_header header;
> > +};
> > +#endif
> > +
> >  /* Functions */
> >  int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
> >  int fpgamgr_program_finish(void);
> >  int is_fpgamgr_user_mode(void);
> >  int fpgamgr_wait_early_user_mode(void);
> > +#if defined(CONFIG_CMD_FPGA_LOADFS)
> > +const char *get_cff_filename(const void *fdt, int *len, u32 core);
> > +const char *get_cff_devpart(const void *fdt, int *len);
> > +#endif
> >  
> >  #endif /* __ASSEMBLY__ */
> >  
> > diff --git a/drivers/fpga/socfpga_arria10.c
> > b/drivers/fpga/socfpga_arria10.c
> > index 5c1a68a..90c55e5 100644
> > --- a/drivers/fpga/socfpga_arria10.c
> > +++ b/drivers/fpga/socfpga_arria10.c
> > @@ -13,6 +13,12 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> >  #include 
> >  #include 
> >  
> > @@ -22,6 +28,10 @@
> >  #define COMPRESSION_OFFSET 229
> >  #define FPGA_TIMEOUT_MSEC  1000  /* timeout in ms */
> >  #define FPGA_TIMEOUT_CNT   0x100
> > +#define RBF_UNENCRYPTED0xa65c
> > +#define RBF_ENCRYPTED  0xa65d
> > +#define ARRIA10RBF_PERIPH  0x0001
> > +#define ARRIA10RBF_CORE0x8001
> >  
> >  DECLARE_GLOBAL_DATA_PTR;
> >  
> > @@ -118,7 +128,7 @@ static int
> > wait_for_nconfig_pin_and_nstatus_pin(void)
> >     return wait_for_bit(__func__,
> >     _manager_base->imgcfg_stat,
> >     mask,
> > -   false, FPGA_TIMEOUT_MSEC, false);
> > +   true, FPGA_TIMEOUT_MSEC, false);
> >  }
> >  
> >  static int wait_for_f2s_nstatus_pin(unsigned long value)
> > @@ -453,6 +463,281 @@ int fpgamgr_program_finish(void)
> >     return 0;
> >  }
> >  
> > +#if defined(CONFIG_CMD_FPGA_LOADFS)
> > +const char *get_cff_filename(const void *fdt, int *len, u32 core)
> > +{
> > +   const char *cff_filename = NULL;
> > +   const char *cell;
> > +   int nodeoffset;
> > +   nodeoffset = fdt_subnode_offset(fdt, 0, "chosen");
> > +
> > +   if (nodeoffset >= 0) {
> > +   if (core)
> > +   cell = fdt_getprop(fdt,
> > +   nodeoffset,
> > +   "cffcore-file",
> > +   len);
> > +   else
> > +   cell = fdt_getprop(fdt, nodeoffset, "cff-
> > file", len);
> This should be a property of the FPGA , not the system . You can have
> multiple FPGAs and then this would become a problem.
> 
This setting is for the only one FPGA inside our SoCFPGA. For external
multiple FPGAs programming, user is adviced to store the FPGA filename
in environment variable and programming FPGA with fpga loadfs command.

Please note that, peripheral rbf and partition are required in SPL to
set up DDR before booting to U-boot.

> > 
> > +
> > +   if (cell)
> > +   cff_filename = cell;
> > +   }
> > +
> > +   return cff_filename;
> > +}
> > +
> > +const char *get_cff_devpart(const 

Re: [U-Boot] [PATCH 03/19] arm: socfpga: Add driver for flash to program FPGA

[Marek Vasut]

On 08/29/2017 12:45 PM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee 
> 
> This driver handles FPGA program operation from flash loading
> RBF to memory and then to program FPGA.
> 
> Signed-off-by: Tien Fong Chee 
> ---
>  .../include/mach/fpga_manager_arria10.h|   27 ++
>  drivers/fpga/socfpga_arria10.c |  386 
> +++-
>  include/altera.h   |6 +
>  include/configs/socfpga_common.h   |4 +
>  4 files changed, 422 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h 
> b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> index 9cbf696..93a9122 100644
> --- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> @@ -8,6 +8,8 @@
>  #ifndef _FPGA_MANAGER_ARRIA10_H_
>  #define _FPGA_MANAGER_ARRIA10_H_
>  
> +#include 
> +
>  #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSKBIT(0)
>  #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK   BIT(1)
>  #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK BIT(2)
> @@ -89,11 +91,36 @@ struct socfpga_fpga_manager {
>   u32  imgcfg_fifo_status;
>  };
>  
> +#if defined(CONFIG_CMD_FPGA_LOADFS)
> +enum rbf_type {unknown, periph_section, core_section};
> +enum rbf_security {invalid, unencrypted, encrypted};
> +
> +struct rbf_info {
> + enum rbf_type section;
> + enum rbf_security security;
> +};
> +
> +struct flash_info {
> + char *interface;
> + char *dev_part;
> + char *filename;
> + int fstype;
> + u32 remaining;
> + u32 flash_offset;
> + struct rbf_info rbfinfo;
> + struct image_header header;
> +};
> +#endif
> +
>  /* Functions */
>  int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
>  int fpgamgr_program_finish(void);
>  int is_fpgamgr_user_mode(void);
>  int fpgamgr_wait_early_user_mode(void);
> +#if defined(CONFIG_CMD_FPGA_LOADFS)
> +const char *get_cff_filename(const void *fdt, int *len, u32 core);
> +const char *get_cff_devpart(const void *fdt, int *len);
> +#endif
>  
>  #endif /* __ASSEMBLY__ */
>  
> diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
> index 5c1a68a..90c55e5 100644
> --- a/drivers/fpga/socfpga_arria10.c
> +++ b/drivers/fpga/socfpga_arria10.c
> @@ -13,6 +13,12 @@
>  #include 
>  #include 
>  #include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
>  #include 
>  #include 
>  
> @@ -22,6 +28,10 @@
>  #define COMPRESSION_OFFSET   229
>  #define FPGA_TIMEOUT_MSEC1000  /* timeout in ms */
>  #define FPGA_TIMEOUT_CNT 0x100
> +#define RBF_UNENCRYPTED  0xa65c
> +#define RBF_ENCRYPTED0xa65d
> +#define ARRIA10RBF_PERIPH0x0001
> +#define ARRIA10RBF_CORE  0x8001
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> @@ -118,7 +128,7 @@ static int wait_for_nconfig_pin_and_nstatus_pin(void)
>   return wait_for_bit(__func__,
>   _manager_base->imgcfg_stat,
>   mask,
> - false, FPGA_TIMEOUT_MSEC, false);
> + true, FPGA_TIMEOUT_MSEC, false);
>  }
>  
>  static int wait_for_f2s_nstatus_pin(unsigned long value)
> @@ -453,6 +463,281 @@ int fpgamgr_program_finish(void)
>   return 0;
>  }
>  
> +#if defined(CONFIG_CMD_FPGA_LOADFS)
> +const char *get_cff_filename(const void *fdt, int *len, u32 core)
> +{
> + const char *cff_filename = NULL;
> + const char *cell;
> + int nodeoffset;
> + nodeoffset = fdt_subnode_offset(fdt, 0, "chosen");
> +
> + if (nodeoffset >= 0) {
> + if (core)
> + cell = fdt_getprop(fdt,
> + nodeoffset,
> + "cffcore-file",
> + len);
> + else
> + cell = fdt_getprop(fdt, nodeoffset, "cff-file", len);

This should be a property of the FPGA , not the system . You can have
multiple FPGAs and then this would become a problem.

> +
> + if (cell)
> + cff_filename = cell;
> + }
> +
> + return cff_filename;
> +}
> +
> +const char *get_cff_devpart(const void *fdt, int *len)
> +{
> + const char *cff_devpart = NULL;
> + const char *cell;
> + int nodeoffset;
> + nodeoffset = fdt_subnode_offset(fdt, 0, "chosen");
> +
> + cell = fdt_getprop(fdt, nodeoffset, "cff_devpart", len);

Indent ? What is this new undocumented DT node about ?

> + if (cell)
> + cff_devpart = cell;
> +
> + return cff_devpart;
> +}
> +
> +void get_rbf_image_info(struct rbf_info *rbf, u16 *buffer)
> +{
> + /*
> +   Magic ID starting at:
> +-> 1st dword in periph.rbf
> +-> 2nd dword in core.rbf

[U-Boot] [PATCH 03/19] arm: socfpga: Add driver for flash to program FPGA

[tien . fong . chee]

From: Tien Fong Chee 

This driver handles FPGA program operation from flash loading
RBF to memory and then to program FPGA.

Signed-off-by: Tien Fong Chee 
---
 .../include/mach/fpga_manager_arria10.h|   27 ++
 drivers/fpga/socfpga_arria10.c |  386 +++-
 include/altera.h   |6 +
 include/configs/socfpga_common.h   |4 +
 4 files changed, 422 insertions(+), 1 deletions(-)

diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h 
b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
index 9cbf696..93a9122 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
@@ -8,6 +8,8 @@
 #ifndef _FPGA_MANAGER_ARRIA10_H_
 #define _FPGA_MANAGER_ARRIA10_H_
 
+#include 
+
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK  BIT(0)
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1)
 #define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK   BIT(2)
@@ -89,11 +91,36 @@ struct socfpga_fpga_manager {
u32  imgcfg_fifo_status;
 };
 
+#if defined(CONFIG_CMD_FPGA_LOADFS)
+enum rbf_type {unknown, periph_section, core_section};
+enum rbf_security {invalid, unencrypted, encrypted};
+
+struct rbf_info {
+   enum rbf_type section;
+   enum rbf_security security;
+};
+
+struct flash_info {
+   char *interface;
+   char *dev_part;
+   char *filename;
+   int fstype;
+   u32 remaining;
+   u32 flash_offset;
+   struct rbf_info rbfinfo;
+   struct image_header header;
+};
+#endif
+
 /* Functions */
 int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size);
 int fpgamgr_program_finish(void);
 int is_fpgamgr_user_mode(void);
 int fpgamgr_wait_early_user_mode(void);
+#if defined(CONFIG_CMD_FPGA_LOADFS)
+const char *get_cff_filename(const void *fdt, int *len, u32 core);
+const char *get_cff_devpart(const void *fdt, int *len);
+#endif
 
 #endif /* __ASSEMBLY__ */
 
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 5c1a68a..90c55e5 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -13,6 +13,12 @@
 #include 
 #include 
 #include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
 #include 
 #include 
 
@@ -22,6 +28,10 @@
 #define COMPRESSION_OFFSET 229
 #define FPGA_TIMEOUT_MSEC  1000  /* timeout in ms */
 #define FPGA_TIMEOUT_CNT   0x100
+#define RBF_UNENCRYPTED0xa65c
+#define RBF_ENCRYPTED  0xa65d
+#define ARRIA10RBF_PERIPH  0x0001
+#define ARRIA10RBF_CORE0x8001
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -118,7 +128,7 @@ static int wait_for_nconfig_pin_and_nstatus_pin(void)
return wait_for_bit(__func__,
_manager_base->imgcfg_stat,
mask,
-   false, FPGA_TIMEOUT_MSEC, false);
+   true, FPGA_TIMEOUT_MSEC, false);
 }
 
 static int wait_for_f2s_nstatus_pin(unsigned long value)
@@ -453,6 +463,281 @@ int fpgamgr_program_finish(void)
return 0;
 }
 
+#if defined(CONFIG_CMD_FPGA_LOADFS)
+const char *get_cff_filename(const void *fdt, int *len, u32 core)
+{
+   const char *cff_filename = NULL;
+   const char *cell;
+   int nodeoffset;
+   nodeoffset = fdt_subnode_offset(fdt, 0, "chosen");
+
+   if (nodeoffset >= 0) {
+   if (core)
+   cell = fdt_getprop(fdt,
+   nodeoffset,
+   "cffcore-file",
+   len);
+   else
+   cell = fdt_getprop(fdt, nodeoffset, "cff-file", len);
+
+   if (cell)
+   cff_filename = cell;
+   }
+
+   return cff_filename;
+}
+
+const char *get_cff_devpart(const void *fdt, int *len)
+{
+   const char *cff_devpart = NULL;
+   const char *cell;
+   int nodeoffset;
+   nodeoffset = fdt_subnode_offset(fdt, 0, "chosen");
+
+   cell = fdt_getprop(fdt, nodeoffset, "cff_devpart", len);
+
+   if (cell)
+   cff_devpart = cell;
+
+   return cff_devpart;
+}
+
+void get_rbf_image_info(struct rbf_info *rbf, u16 *buffer)
+{
+   /*
+ Magic ID starting at:
+  -> 1st dword in periph.rbf
+  -> 2nd dword in core.rbf
+   */
+   u32 word_reading_max = 2;
+   u32 i;
+
+   for(i = 0; i < word_reading_max; i++)
+   {
+   if(RBF_UNENCRYPTED == *(buffer + i)) /* PERIPH RBF */
+   rbf->security = unencrypted;
+   else if (RBF_ENCRYPTED == *(buffer + i))
+   rbf->security = encrypted;
+   else if (RBF_UNENCRYPTED == *(buffer + i + 1)) /* CORE RBF */
+