Re: [U-Boot] [PATCH 04/10] sunxi: s/sun8i/sun8i_a23/

2015-04-16 Thread Hans de Goede 

Hi,

On 15-04-15 21:49, Ian Campbell wrote:

On Tue, 2015-04-14 at 18:06 +0200, Hans de Goede wrote:

This is a preparation patch for adding A33 support, which will have a mach
name of sun8i-a33.


And, presumably, differs substantially from sun8i-a23, to the extent it
should likely have been a new sunNi but we are stuck with what AW did,
sigh, oh well.


Actually other then having a different DRAM controller / MBUS setup,
the differences are very minor (what I know sofar is a few slightly
different bits in the otg controller/phy, and the SID is back inside
the SoC).


Signed-off-by: Hans de Goede hdego...@redhat.com


Acked-by: Ian Campbell ian.campb...@citrix.com




Regards,

Hans
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

Re: [U-Boot] [PATCH 04/10] sunxi: s/sun8i/sun8i_a23/

2015-04-15 Thread Ian Campbell 
On Tue, 2015-04-14 at 18:06 +0200, Hans de Goede wrote:
 This is a preparation patch for adding A33 support, which will have a mach
 name of sun8i-a33.

And, presumably, differs substantially from sun8i-a23, to the extent it
should likely have been a new sunNi but we are stuck with what AW did,
sigh, oh well.

 Signed-off-by: Hans de Goede hdego...@redhat.com

Acked-by: Ian Campbell ian.campb...@citrix.com


___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

[U-Boot] [PATCH 04/10] sunxi: s/sun8i/sun8i_a23/

2015-04-14 Thread Hans de Goede 
This is a preparation patch for adding A33 support, which will have a mach
name of sun8i-a33.

Signed-off-by: Hans de Goede hdego...@redhat.com
---
 arch/arm/cpu/armv7/sunxi/Makefile |  8 
 arch/arm/cpu/armv7/sunxi/board.c  |  8 
 arch/arm/cpu/armv7/sunxi/cpu_info.c   |  2 +-
 .../cpu/armv7/sunxi/{dram_sun8i.c = dram_sun8i_a23.c}|  0
 arch/arm/cpu/armv7/sunxi/rsb.c|  2 +-
 arch/arm/include/asm/arch-sunxi/clock.h   |  3 ++-
 arch/arm/include/asm/arch-sunxi/clock_sun6i.h |  6 +++---
 arch/arm/include/asm/arch-sunxi/dram.h|  4 ++--
 .../asm/arch-sunxi/{dram_sun8i.h = dram_sun8i_a23.h} |  0
 board/sunxi/Kconfig   | 15 ---
 board/sunxi/board.c   |  4 ++--
 configs/Ippo_q8h_v1_2_defconfig   |  2 +-
 configs/Ippo_q8h_v5_defconfig |  2 +-
 drivers/power/Kconfig |  4 ++--
 include/configs/sunxi-common.h|  2 +-
 15 files changed, 32 insertions(+), 30 deletions(-)
 rename arch/arm/cpu/armv7/sunxi/{dram_sun8i.c = dram_sun8i_a23.c} (100%)
 rename arch/arm/include/asm/arch-sunxi/{dram_sun8i.h = dram_sun8i_a23.h} 
(100%)

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile 
b/arch/arm/cpu/armv7/sunxi/Makefile
index 4bb12ad..b2e5e5d 100644
--- a/arch/arm/cpu/armv7/sunxi/Makefile
+++ b/arch/arm/cpu/armv7/sunxi/Makefile
@@ -15,16 +15,16 @@ obj-y   += dram_helpers.o
 obj-y  += pinmux.o
 obj-y  += usbc.o
 obj-$(CONFIG_MACH_SUN6I)   += prcm.o
-obj-$(CONFIG_MACH_SUN8I)   += prcm.o
+obj-$(CONFIG_MACH_SUN8I_A23)   += prcm.o
 obj-$(CONFIG_MACH_SUN9I)   += prcm.o
 obj-$(CONFIG_MACH_SUN6I)   += p2wi.o
-obj-$(CONFIG_MACH_SUN8I)   += rsb.o
+obj-$(CONFIG_MACH_SUN8I_A23)   += rsb.o
 obj-$(CONFIG_MACH_SUN9I)   += rsb.o
 obj-$(CONFIG_MACH_SUN4I)   += clock_sun4i.o
 obj-$(CONFIG_MACH_SUN5I)   += clock_sun4i.o
 obj-$(CONFIG_MACH_SUN6I)   += clock_sun6i.o
 obj-$(CONFIG_MACH_SUN7I)   += clock_sun4i.o
-obj-$(CONFIG_MACH_SUN8I)   += clock_sun6i.o
+obj-$(CONFIG_MACH_SUN8I_A23)   += clock_sun6i.o
 obj-$(CONFIG_MACH_SUN9I)   += clock_sun9i.o
 
 ifndef CONFIG_SPL_BUILD
@@ -38,6 +38,6 @@ obj-$(CONFIG_MACH_SUN4I)  += dram_sun4i.o
 obj-$(CONFIG_MACH_SUN5I)   += dram_sun4i.o
 obj-$(CONFIG_MACH_SUN6I)   += dram_sun6i.o
 obj-$(CONFIG_MACH_SUN7I)   += dram_sun4i.o
-obj-$(CONFIG_MACH_SUN8I)   += dram_sun8i.o
+obj-$(CONFIG_MACH_SUN8I_A23)   += dram_sun8i_a23.o
 obj-y  += fel_utils.o
 endif
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c
index 30d5974..7ce79af 100644
--- a/arch/arm/cpu/armv7/sunxi/board.c
+++ b/arch/arm/cpu/armv7/sunxi/board.c
@@ -46,7 +46,7 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
 #endif
-#if defined(CONFIG_MACH_SUN8I)
+#if defined(CONFIG_MACH_SUN8I_A23)
sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0_TX);
sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0_RX);
 #else
@@ -70,7 +70,7 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 5  defined(CONFIG_MACH_SUN8I)
+#elif CONFIG_CONS_INDEX == 5  defined(CONFIG_MACH_SUN8I_A23)
sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
@@ -89,14 +89,14 @@ void spl_board_load_image(void)
 
 void s_init(void)
 {
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I
+#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_A23
/* Magic (undocmented) value taken from boot0, without this DRAM
 * access gets messed up (seems cache related) */
setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
 #endif
 #if defined CONFIG_MACH_SUN6I || \
 defined CONFIG_MACH_SUN7I || \
-defined CONFIG_MACH_SUN8I
+defined CONFIG_MACH_SUN8I_A23
/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
asm volatile(
mrc p15, 0, r0, c1, c0, 1\n
diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c 
b/arch/arm/cpu/armv7/sunxi/cpu_info.c
index c3ec20d..6143038 100644
--- a/arch/arm/cpu/armv7/sunxi/cpu_info.c
+++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c
@@ -64,7 +64,7 @@ int print_cpuinfo(void)
}
 #elif defined CONFIG_MACH_SUN7I
puts(CPU:   Allwinner A20 (SUN7I)\n);
-#elif defined CONFIG_MACH_SUN8I
+#elif defined CONFIG_MACH_SUN8I_A23
puts(CPU:   Allwinner A23 (SUN8I)\n);
 #else
 #warning Please update cpu_info.c