This is a port of Linux driver for SDHC host controller hardware
found on Freescale's MX2 and MX3 processors. Uses new generic MMC
framework (CONFIG_GENERIC_MMC) and it looks like there are some
problems with a framework (at least on LE cpus). Some of these
problems are addressed in the following patches.
Signed-off-by: Ilya Yanok ya...@emcraft.com
---
cpu/arm926ejs/mx27/generic.c | 16 ++
drivers/mmc/Makefile |1 +
drivers/mmc/mxcmmc.c | 520
include/asm-arm/arch-mx27/mxcmmc.h | 25 ++
4 files changed, 562 insertions(+), 0 deletions(-)
create mode 100644 drivers/mmc/mxcmmc.c
create mode 100644 include/asm-arm/arch-mx27/mxcmmc.h
diff --git a/cpu/arm926ejs/mx27/generic.c b/cpu/arm926ejs/mx27/generic.c
index fdbc8b7..a0be35b 100644
--- a/cpu/arm926ejs/mx27/generic.c
+++ b/cpu/arm926ejs/mx27/generic.c
@@ -21,6 +21,9 @@
#include common.h
#include div64.h
#include asm/arch/imx-regs.h
+#ifdef CONFIG_MXC_MMC
+#include asm/arch/mxcmmc.h
+#endif
/*
* get the system pll clock in Hz
*
@@ -143,6 +146,19 @@ int print_cpuinfo (void)
}
#endif
+/*
+ * Initializes on-chip MMC controllers.
+ * to override, implement board_mmc_init()
+ */
+int cpu_mmc_init(bd_t *bis)
+{
+#ifdef CONFIG_MXC_MMC
+ return mxc_mmc_init(bis);
+#else
+ return 0;
+#endif
+}
+
void imx_gpio_mode(int gpio_mode)
{
unsigned int pin = gpio_mode GPIO_PIN_MASK;
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 1b0af12..6fa04b8 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -30,6 +30,7 @@ COBJS-$(CONFIG_ATMEL_MCI) += atmel_mci.o
COBJS-$(CONFIG_BFIN_SDH) += bfin_sdh.o
COBJS-$(CONFIG_OMAP3_MMC) += omap3_mmc.o
COBJS-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
+COBJS-$(CONFIG_MXC_MMC) += mxcmmc.o
COBJS-$(CONFIG_PXA_MMC) += pxa_mmc.o
COBJS := $(COBJS-y)
diff --git a/drivers/mmc/mxcmmc.c b/drivers/mmc/mxcmmc.c
new file mode 100644
index 000..9635d6e
--- /dev/null
+++ b/drivers/mmc/mxcmmc.c
@@ -0,0 +1,520 @@
+/*
+ * This is a driver for the SDHC controller found in Freescale MX2/MX3
+ * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
+ * Unlike the hardware found on MX1, this hardware just works and does
+ * not need all the quirks found in imxmmc.c, hence the seperate driver.
+ *
+ * Copyright (C) 2009 Ilya Yanok, ya...@emcraft.com
+ * Copyright (C) 2008 Sascha Hauer, Pengutronix s.ha...@pengutronix.de
+ * Copyright (C) 2006 Pavel Pisa, PiKRON pp...@pikron.com
+ *
+ * derived from pxamci.c by Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include config.h
+#include common.h
+#include command.h
+#include mmc.h
+#include part.h
+#include malloc.h
+#include mmc.h
+#include asm/errno.h
+#include asm/io.h
+#ifdef CONFIG_MX27
+#include asm/arch/clock.h
+#endif
+
+#define DRIVER_NAME mxc-mmc
+
+#define MMC_REG_STR_STP_CLK0x00
+#define MMC_REG_STATUS 0x04
+#define MMC_REG_CLK_RATE 0x08
+#define MMC_REG_CMD_DAT_CONT 0x0C
+#define MMC_REG_RES_TO 0x10
+#define MMC_REG_READ_TO0x14
+#define MMC_REG_BLK_LEN0x18
+#define MMC_REG_NOB0x1C
+#define MMC_REG_REV_NO 0x20
+#define MMC_REG_INT_CNTR 0x24
+#define MMC_REG_CMD0x28
+#define MMC_REG_ARG0x2C
+#define MMC_REG_RES_FIFO 0x34
+#define MMC_REG_BUFFER_ACCESS 0x38
+
+#define STR_STP_CLK_RESET (1 3)
+#define STR_STP_CLK_START_CLK (1 1)
+#define STR_STP_CLK_STOP_CLK(1 0)
+
+#define STATUS_CARD_INSERTION (1 31)
+#define STATUS_CARD_REMOVAL(1 30)
+#define STATUS_YBUF_EMPTY (1 29)
+#define STATUS_XBUF_EMPTY (1 28)
+#define STATUS_YBUF_FULL (1 27)
+#define STATUS_XBUF_FULL (1 26)
+#define STATUS_BUF_UND_RUN (1 25)
+#define STATUS_BUF_OVFL(1 24)
+#define STATUS_SDIO_INT_ACTIVE (1 14)
+#define STATUS_END_CMD_RESP(1 13)
+#define STATUS_WRITE_OP_DONE (1 12)
+#define STATUS_DATA_TRANS_DONE (1 11)
+#define STATUS_READ_OP_DONE(1 11)
+#define STATUS_WR_CRC_ERROR_CODE_MASK (3 10)
+#define STATUS_CARD_BUS_CLK_RUN(1 8)
+#define STATUS_BUF_READ_RDY(1 7)
+#define STATUS_BUF_WRITE_RDY (1 6)
+#define STATUS_RESP_CRC_ERR(1 5)
+#define STATUS_CRC_READ_ERR(1 3)
+#define STATUS_CRC_WRITE_ERR (1 2)
+#define STATUS_TIME_OUT_RESP (1 1)
+#define STATUS_TIME_OUT_READ (1 0)
+#define STATUS_ERR_MASK0x2f
+
+#define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 12)
