Re: [U-Boot] [PATCH 05/20] arm: dts: MediaTek: add MT7623 Bananapi R2 board support
On Tue, 2018-10-02 at 15:10 +0200, Matthias Brugger wrote: > > On 02/10/2018 08:13, Ryder Lee wrote: > > This patch adds support for MT7623 development board - Bananapi R2 from > > BIPAI KEJI. Detailed hardware information for BPI-R2 which could be > > found on http://wiki.banana-pi.org/Banana_Pi_BPI-R2. > > > > Signed-off-by: Ryder Lee > > --- > > arch/arm/dts/Makefile | 1 + > > arch/arm/dts/mt7623.dtsi | 258 ++ > > arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 207 ++ > > include/dt-bindings/clock/mt7623-clk.h| 429 > > ++ > > include/dt-bindings/power/mt7623-power.h | 19 ++ > > include/dt-bindings/reset/mt7623-resets.h | 85 ++ > > 6 files changed, 999 insertions(+) > > create mode 100644 arch/arm/dts/mt7623.dtsi > > create mode 100644 arch/arm/dts/mt7623n-bananapi-bpi-r2.dts > > create mode 100644 include/dt-bindings/clock/mt7623-clk.h > > create mode 100644 include/dt-bindings/power/mt7623-power.h > > create mode 100644 include/dt-bindings/reset/mt7623-resets.h > > > [...] > > +/* INFRACFG */ > > + > > +#define CLK_INFRA_DBG 0 > > +#define CLK_INFRA_SMI 1 > > +#define CLK_INFRA_QAXI_CM4 2 > > +#define CLK_INFRA_AUD_SPLIN_B 3 > > +#define CLK_INFRA_AUDIO4 > > +#define CLK_INFRA_EFUSE5 > > +#define CLK_INFRA_L2C_SRAM 6 > > +#define CLK_INFRA_M4U 7 > > +#define CLK_INFRA_CONNMCU 8 > > +#define CLK_INFRA_TRNG 9 > > +#define CLK_INFRA_RAMBUFIF 10 > > +#define CLK_INFRA_CPUM 11 > > +#define CLK_INFRA_KP 12 > > +#define CLK_INFRA_CEC 13 > > +#define CLK_INFRA_IRRX 14 > > +#define CLK_INFRA_PMICSPI 15 > > +#define CLK_INFRA_PMICWRAP 16 > > +#define CLK_INFRA_DDCCI17 > > +#define CLK_INFRA_CPUSEL18 > > Tabs instead of spaces please :) Sure, I will fix it. Thanks for catching that. > Regards, > Matthias ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 05/20] arm: dts: MediaTek: add MT7623 Bananapi R2 board support
On 02/10/2018 08:13, Ryder Lee wrote: > This patch adds support for MT7623 development board - Bananapi R2 from > BIPAI KEJI. Detailed hardware information for BPI-R2 which could be > found on http://wiki.banana-pi.org/Banana_Pi_BPI-R2. > > Signed-off-by: Ryder Lee > --- > arch/arm/dts/Makefile | 1 + > arch/arm/dts/mt7623.dtsi | 258 ++ > arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 207 ++ > include/dt-bindings/clock/mt7623-clk.h| 429 > ++ > include/dt-bindings/power/mt7623-power.h | 19 ++ > include/dt-bindings/reset/mt7623-resets.h | 85 ++ > 6 files changed, 999 insertions(+) > create mode 100644 arch/arm/dts/mt7623.dtsi > create mode 100644 arch/arm/dts/mt7623n-bananapi-bpi-r2.dts > create mode 100644 include/dt-bindings/clock/mt7623-clk.h > create mode 100644 include/dt-bindings/power/mt7623-power.h > create mode 100644 include/dt-bindings/reset/mt7623-resets.h > [...] > +/* INFRACFG */ > + > +#define CLK_INFRA_DBG0 > +#define CLK_INFRA_SMI1 > +#define CLK_INFRA_QAXI_CM4 2 > +#define CLK_INFRA_AUD_SPLIN_B3 > +#define CLK_INFRA_AUDIO 4 > +#define CLK_INFRA_EFUSE 5 > +#define CLK_INFRA_L2C_SRAM 6 > +#define CLK_INFRA_M4U7 > +#define CLK_INFRA_CONNMCU8 > +#define CLK_INFRA_TRNG 9 > +#define CLK_INFRA_RAMBUFIF 10 > +#define CLK_INFRA_CPUM 11 > +#define CLK_INFRA_KP 12 > +#define CLK_INFRA_CEC13 > +#define CLK_INFRA_IRRX 14 > +#define CLK_INFRA_PMICSPI15 > +#define CLK_INFRA_PMICWRAP 16 > +#define CLK_INFRA_DDCCI 17 > +#define CLK_INFRA_CPUSEL18 Tabs instead of spaces please :) Regards, Matthias ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 05/20] arm: dts: MediaTek: add MT7623 Bananapi R2 board support
This patch adds support for MT7623 development board - Bananapi R2 from
BIPAI KEJI. Detailed hardware information for BPI-R2 which could be
found on http://wiki.banana-pi.org/Banana_Pi_BPI-R2.
Signed-off-by: Ryder Lee
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/mt7623.dtsi | 258 ++
arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 207 ++
include/dt-bindings/clock/mt7623-clk.h| 429 ++
include/dt-bindings/power/mt7623-power.h | 19 ++
include/dt-bindings/reset/mt7623-resets.h | 85 ++
6 files changed, 999 insertions(+)
create mode 100644 arch/arm/dts/mt7623.dtsi
create mode 100644 arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
create mode 100644 include/dt-bindings/clock/mt7623-clk.h
create mode 100644 include/dt-bindings/power/mt7623-power.h
create mode 100644 include/dt-bindings/reset/mt7623-resets.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9f88146..942ae4d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -555,6 +555,7 @@ dtb-$(CONFIG_TARGET_STM32MP1) += \
dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += \
+ mt7623n-bananapi-bpi-r2.dtb \
mt7629-rfb.dtb
targets += $(dtb-y)
diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi
new file mode 100644
index 000..8bb6394
--- /dev/null
+++ b/arch/arm/dts/mt7623.dtsi
@@ -0,0 +1,258 @@
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Ryder Lee
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "mediatek,mt7623";
+ interrupt-parent = <>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ enable-method = "mediatek,mt6589-smp";
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ clocks = < CLK_INFRA_CPUSEL>,
+< CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ clock-frequency = <13>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x1>;
+ clocks = < CLK_INFRA_CPUSEL>,
+< CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ clock-frequency = <13>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x2>;
+ clocks = < CLK_INFRA_CPUSEL>,
+< CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ clock-frequency = <13>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x3>;
+ clocks = < CLK_INFRA_CPUSEL>,
+< CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ clock-frequency = <13>;
+ };
+ };
+
+ system_clk: dummy13m {
+ compatible = "fixed-clock";
+ clock-frequency = <1300>;
+ #clock-cells = <0>;
+ };
+
+ rtc32k: oscillator-1 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32000>;
+ clock-output-names = "rtc32k";
+ };
+
+ clk26m: oscillator-0 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <2600>;
+ clock-output-names = "clk26m";
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupt-parent = <>;
+ interrupts = ,
+,
+,
+;
+ clock-frequency = <1300>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ topckgen: clock-controller@1000 {
+ compatible = "mediatek,mt7623-topckgen";
+ reg = <0x1000 0x1000>;
+ #clock-cells = <1>;
+ u-boot,dm-pre-reloc;
+ };
+
+ infracfg: syscon@10001000 {
+ compatible = "mediatek,mt7623-infracfg", "syscon";
+ reg = <0x10001000 0x1000>;
+ #clock-cells = <1>;
+
