Signed-off-by: Marek Vasut <marek.va...@gmail.com>
Cc: Ben Warren <biggerbadder...@gmail.com>
Cc: Stefano Babic <sba...@denx.de>
Cc: Wolfgang Denk <w...@denx.de>
Cc: Detlev Zundel <d...@denx.de>
---
arch/arm/cpu/arm926ejs/mx28/mx28.c | 31 +++++++++++++++++++++++++++++++
1 files changed, 31 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/mx28/mx28.c
b/arch/arm/cpu/arm926ejs/mx28/mx28.c
index e3df76b..dca54d2 100644
--- a/arch/arm/cpu/arm926ejs/mx28/mx28.c
+++ b/arch/arm/cpu/arm926ejs/mx28/mx28.c
@@ -129,3 +129,34 @@ int print_cpuinfo(void)
return 0;
}
#endif
+
+/*
+ * Initializes on-chip ethernet controllers.
+ */
+#ifdef CONFIG_CMD_NET
+int cpu_eth_init(bd_t *bis)
+{
+ struct mx28_clkctrl_regs *clkctrl_regs =
+ (struct mx28_clkctrl_regs *)MXS_CLKCTRL_BASE;
+
+ /* Turn on ENET clocks */
+ clrbits_le32(&clkctrl_regs->hw_clkctrl_enet,
+ CLKCTRL_ENET_SLEEP | CLKCTRL_ENET_DISABLE);
+
+ /* Set up ENET PLL for 50 MHz */
+ /* Power on ENET PLL */
+ writel(CLKCTRL_PLL2CTRL0_POWER,
+ &clkctrl_regs->hw_clkctrl_pll2ctrl0_set);
+
+ udelay(10);
+
+ /* Gate on ENET PLL */
+ writel(CLKCTRL_PLL2CTRL0_CLKGATE,
+ &clkctrl_regs->hw_clkctrl_pll2ctrl0_clr);
+
+ /* Enable pad output */
+ setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN);
+
+ return 0;
+}
+#endif
--
1.7.5.4
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