Re: [U-Boot] [PATCH 08/10] arm: socfpga: arria10: Added drivers for Arria10 clock manager

[Chee, Tien Fong]

On Sel, 2016-12-06 at 16:10 +0800, Chee Tien Fong wrote:
> From: Tien Fong Chee 
> 
> The drivers is restructured such common functions, gen5 functions,
> and arria10 functions are moved to clock_manager.c, cock_manager_gen5
> and clock_manager_arria10 respectively.
> 
> Signed-off-by: Tien Fong Chee 
> Cc: Marek Vasut 
> Cc: Dinh Nguyen 
> Cc: Chin Liang See 
> Cc: Tien Fong 
> ---
>  arch/arm/mach-socfpga/Makefile |6 +-
>  arch/arm/mach-socfpga/clock_manager.c  |  754 +++---
> --
>  arch/arm/mach-socfpga/clock_manager_arria10.c  |  954
> 
>  arch/arm/mach-socfpga/clock_manager_gen5.c |  342 +++
>  arch/arm/mach-socfpga/include/mach/clock_manager.h |  360 ++--
>  5 files changed, 1910 insertions(+), 506 deletions(-)
>  create mode 100644 arch/arm/mach-socfpga/clock_manager_arria10.c
>  create mode 100644 arch/arm/mach-socfpga/clock_manager_gen5.c
> 
> diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-
> socfpga/Makefile
> index f8b529e..71cf31c 100644
> --- a/arch/arm/mach-socfpga/Makefile
> +++ b/arch/arm/mach-socfpga/Makefile
> @@ -9,9 +9,11 @@
>  
Any comments on this patch before i start the version 2?

>  obj-y+= misc.o timer.o reset_manager.o system_manager.o
> clock_manager.o \
>      fpga_manager.o board.o
> -obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
> misc_arria10.o
> +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o
> misc_arria10.o \
> + clock_manager_arria10.o
>  obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o
> wrap_pll_config.o \
> - reset_manager_gen5.o misc_gen5.o
> + reset_manager_gen5.o misc_gen5.o \
> + clock_manager_gen5.o
>  
>  ifdef CONFIG_SPL_BUILD
>  obj-y += spl.o
> diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-
> socfpga/clock_manager.c
> index aa71636..fe82c39 100644
> --- a/arch/arm/mach-socfpga/clock_manager.c
> +++ b/arch/arm/mach-socfpga/clock_manager.c
> @@ -1,422 +1,293 @@
>  /*
> - *  Copyright (C) 2013 Altera Corporation 
> + *  Copyright (C) 2013-2016 Intel Corporation 
>   *
> - * SPDX-License-Identifier:  GPL-2.0+
> + * SPDX-License-Identifier:  GPL-2.0
>   */
>  
>  #include 
>  #include 
>  #include 
> +#include 
>  
>  DECLARE_GLOBAL_DATA_PTR;
>  
> +/* Function prototypes */
> +/* Common prototypes */
> +unsigned int cm_get_l4_sp_clk_hz(void);
> +unsigned int cm_get_qspi_controller_clk_hz(void);
> +unsigned int cm_get_mmc_controller_clk_hz(void);
> +unsigned int cm_get_spi_controller_clk_hz(void);
> +static void cm_print_clock_quick_summary(void);
> +int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const
> argv[]);
> +void cm_wait_for_lock(uint32_t mask);
> +void cm_wait_for_fsm(void);
> +unsigned int cm_get_main_vco_clk_hz(void);
> +unsigned int cm_get_per_vco_clk_hz(void);
> +unsigned long cm_get_mpu_clk_hz(void);
> +
>  static const struct socfpga_clock_manager *clock_manager_base =
>   (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
>  
> -static void cm_wait_for_lock(uint32_t mask)
> +/* Common functions */
> +int set_cpu_clk_info(void)
>  {
> - register uint32_t inter_val;
> - uint32_t retry = 0;
> - do {
> - inter_val = readl(_manager_base->inter) &
> mask;
> - if (inter_val == mask)
> - retry++;
> - else
> - retry = 0;
> - if (retry >= 10)
> - break;
> - } while (1);
> -}
> + /* Calculate the clock frequencies required for drivers */
> + cm_get_l4_sp_clk_hz();
> + cm_get_mmc_controller_clk_hz();
>  
> -/* function to poll in the fsm busy bit */
> -static void cm_wait_for_fsm(void)
> -{
> - while (readl(_manager_base->stat) & CLKMGR_STAT_BUSY)
> - ;
> -}
> + gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 100;
> + gd->bd->bi_dsp_freq = 0;
>  
> -/*
> - * function to write the bypass register which requires a poll of
> the
> - * busy bit
> - */
> -static void cm_write_bypass(uint32_t val)
> -{
> - writel(val, _manager_base->bypass);
> - cm_wait_for_fsm();
> -}
> +#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
> + gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 100;
> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
> + gd->bd->bi_ddr_freq = 0;
> +#endif
>  
> -/* function to write the ctrl register which requires a poll of the
> busy bit */
> -static void cm_write_ctrl(uint32_t val)
> -{
> - writel(val, _manager_base->ctrl);
> - cm_wait_for_fsm();
> + return 0;
>  }
>  
> -/* function to write a clock register that has phase information */
> -static void cm_write_with_phase(uint32_t value,
> - uint32_t reg_address, 

[U-Boot] [PATCH 08/10] arm: socfpga: arria10: Added drivers for Arria10 clock manager

[Chee Tien Fong]

From: Tien Fong Chee 

The drivers is restructured such common functions, gen5 functions,
and arria10 functions are moved to clock_manager.c, cock_manager_gen5
and clock_manager_arria10 respectively.

Signed-off-by: Tien Fong Chee 
Cc: Marek Vasut 
Cc: Dinh Nguyen 
Cc: Chin Liang See 
Cc: Tien Fong 
---
 arch/arm/mach-socfpga/Makefile |6 +-
 arch/arm/mach-socfpga/clock_manager.c  |  754 +++-
 arch/arm/mach-socfpga/clock_manager_arria10.c  |  954 
 arch/arm/mach-socfpga/clock_manager_gen5.c |  342 +++
 arch/arm/mach-socfpga/include/mach/clock_manager.h |  360 ++--
 5 files changed, 1910 insertions(+), 506 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/clock_manager_arria10.c
 create mode 100644 arch/arm/mach-socfpga/clock_manager_gen5.c

diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index f8b529e..71cf31c 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -9,9 +9,11 @@
 
 obj-y  += misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
   fpga_manager.o board.o
-obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o misc_arria10.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += reset_manager_arria10.o misc_arria10.o 
\
+   clock_manager_arria10.o
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \
-   reset_manager_gen5.o misc_gen5.o
+   reset_manager_gen5.o misc_gen5.o \
+   clock_manager_gen5.o
 
 ifdef CONFIG_SPL_BUILD
 obj-y += spl.o
diff --git a/arch/arm/mach-socfpga/clock_manager.c 
b/arch/arm/mach-socfpga/clock_manager.c
index aa71636..fe82c39 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -1,422 +1,293 @@
 /*
- *  Copyright (C) 2013 Altera Corporation 
+ *  Copyright (C) 2013-2016 Intel Corporation 
  *
- * SPDX-License-Identifier:GPL-2.0+
+ * SPDX-License-Identifier:GPL-2.0
  */
 
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
+/* Function prototypes */
+/* Common prototypes */
+unsigned int cm_get_l4_sp_clk_hz(void);
+unsigned int cm_get_qspi_controller_clk_hz(void);
+unsigned int cm_get_mmc_controller_clk_hz(void);
+unsigned int cm_get_spi_controller_clk_hz(void);
+static void cm_print_clock_quick_summary(void);
+int do_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+void cm_wait_for_lock(uint32_t mask);
+void cm_wait_for_fsm(void);
+unsigned int cm_get_main_vco_clk_hz(void);
+unsigned int cm_get_per_vco_clk_hz(void);
+unsigned long cm_get_mpu_clk_hz(void);
+
 static const struct socfpga_clock_manager *clock_manager_base =
(struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
 
-static void cm_wait_for_lock(uint32_t mask)
+/* Common functions */
+int set_cpu_clk_info(void)
 {
-   register uint32_t inter_val;
-   uint32_t retry = 0;
-   do {
-   inter_val = readl(_manager_base->inter) & mask;
-   if (inter_val == mask)
-   retry++;
-   else
-   retry = 0;
-   if (retry >= 10)
-   break;
-   } while (1);
-}
+   /* Calculate the clock frequencies required for drivers */
+   cm_get_l4_sp_clk_hz();
+   cm_get_mmc_controller_clk_hz();
 
-/* function to poll in the fsm busy bit */
-static void cm_wait_for_fsm(void)
-{
-   while (readl(_manager_base->stat) & CLKMGR_STAT_BUSY)
-   ;
-}
+   gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 100;
+   gd->bd->bi_dsp_freq = 0;
 
-/*
- * function to write the bypass register which requires a poll of the
- * busy bit
- */
-static void cm_write_bypass(uint32_t val)
-{
-   writel(val, _manager_base->bypass);
-   cm_wait_for_fsm();
-}
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+   gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 100;
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+   gd->bd->bi_ddr_freq = 0;
+#endif
 
-/* function to write the ctrl register which requires a poll of the busy bit */
-static void cm_write_ctrl(uint32_t val)
-{
-   writel(val, _manager_base->ctrl);
-   cm_wait_for_fsm();
+   return 0;
 }
 
-/* function to write a clock register that has phase information */
-static void cm_write_with_phase(uint32_t value,
-   uint32_t reg_address, uint32_t mask)
+unsigned int cm_get_spi_controller_clk_hz(void)
 {
-   /* poll until phase is zero */
-   while (readl(reg_address) & mask)
-   ;
+   uint32_t clock = 0;
 
-   writel(value, reg_address);
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
+   uint32_t reg;
+   clock = cm_get_per_vco_clk_hz();
 
-