Re: [U-Boot] [PATCH 08/14] mmc: Add JZ47xx SD/MMC controller driver

2016-11-28 Thread Marek Vasut 
On 11/28/2016 03:58 AM, Jaehoon Chung wrote:
> Hi Marek,
> 
> On 11/26/2016 07:32 AM, Marek Vasut wrote:
>> From: Paul Burton 
>>
>> Add driver for the JZ47xx MSC controller.
> 
> There are some checkpatch error and warings. Could you fix them?

Yeah

> And i don't know what means MSC?

Me neither, probably MMC SD Controller .

>> Signed-off-by: Marek Vasut 
>> Cc: Daniel Schwierzeck 
>> Cc: Paul Burton 
>> ---
>>  drivers/mmc/Kconfig  |   6 +
>>  drivers/mmc/Makefile |   1 +
>>  drivers/mmc/jz_mmc.c | 443 
>> +++
>>  3 files changed, 450 insertions(+)
>>  create mode 100644 drivers/mmc/jz_mmc.c
>>
>> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
>> index aca438b8..761b886 100644
>> --- a/drivers/mmc/Kconfig
>> +++ b/drivers/mmc/Kconfig
>> @@ -102,6 +102,12 @@ config MMC_UNIPHIER
>>  help
>>This selects support for the SD/MMC Host Controller on UniPhier SoCs.
>>  
>> +config JZ47XX_MMC
>> +bool "Ingenic JZ47xx SD/MMC Host Controller support"
>> +depends on ARCH_JZ47XX
>> +help
>> +  This selects support for the SD Card Controller on Ingenic JZ47xx 
>> SoCs.
>> +
>>  config SANDBOX_MMC
>>  bool "Sandbox MMC support"
>>  depends on MMC && SANDBOX
>> diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
>> index d850758..5f7cca3 100644
>> --- a/drivers/mmc/Makefile
>> +++ b/drivers/mmc/Makefile
>> @@ -57,6 +57,7 @@ obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
>>  obj-$(CONFIG_MMC_UNIPHIER) += uniphier-sd.o
>>  obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o
>>  obj-$(CONFIG_ROCKCHIP_SDHCI) += rockchip_sdhci.o
>> +obj-$(CONFIG_JZ47XX_MMC) += jz_mmc.o
>>  
>>  ifdef CONFIG_SPL_BUILD
>>  obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o
>> diff --git a/drivers/mmc/jz_mmc.c b/drivers/mmc/jz_mmc.c
>> new file mode 100644
>> index 000..213fe63
>> --- /dev/null
>> +++ b/drivers/mmc/jz_mmc.c
>> @@ -0,0 +1,443 @@
>> +/*
>> + * Ingenic JZ MMC driver
>> + *
>> + * Copyright (c) 2013 Imagination Technologies
>> + * Author: Paul Burton 
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +/* Registers */
>> +#define MSC_STRPCL  0x000
>> +#define MSC_STAT0x004
>> +#define MSC_CLKRT   0x008
>> +#define MSC_CMDAT   0x00c
>> +#define MSC_RESTO   0x010
>> +#define MSC_RDTO0x014
>> +#define MSC_BLKLEN  0x018
>> +#define MSC_NOB 0x01c
>> +#define MSC_SNOB0x020
>> +#define MSC_IMASK   0x024
>> +#define MSC_IREG0x028
>> +#define MSC_CMD 0x02c
>> +#define MSC_ARG 0x030
>> +#define MSC_RES 0x034
>> +#define MSC_RXFIFO  0x038
>> +#define MSC_TXFIFO  0x03c
>> +#define MSC_LPM 0x040
>> +#define MSC_DMAC0x044
>> +#define MSC_DMANDA  0x048
>> +#define MSC_DMADA   0x04c
>> +#define MSC_DMALEN  0x050
>> +#define MSC_DMACMD  0x054
>> +#define MSC_CTRL2   0x058
>> +#define MSC_RTCNT   0x05c
>> +#define MSC_DBG 0x0fc
>> +
>> +/* MSC Clock and Control Register (MSC_STRPCL) */
>> +
>> +#define MSC_STRPCL_EXIT_MULTIPLEBIT(7)
>> +#define MSC_STRPCL_EXIT_TRANSFERBIT(6)
>> +#define MSC_STRPCL_START_READWAIT   BIT(5)
>> +#define MSC_STRPCL_STOP_READWAITBIT(4)
>> +#define MSC_STRPCL_RESETBIT(3)
>> +#define MSC_STRPCL_START_OP BIT(2)
>> +#define MSC_STRPCL_CLOCK_CONTROL_STOP   BIT(0)
>> +#define MSC_STRPCL_CLOCK_CONTROL_START  BIT(1)
>> +
>> +/* MSC Status Register (MSC_STAT) */
>> +
>> +#define MSC_STAT_AUTO_CMD_DONE  BIT(31)
>> +#define MSC_STAT_IS_RESETTING   BIT(15)
>> +#define MSC_STAT_SDIO_INT_ACTIVEBIT(14)
>> +#define MSC_STAT_PRG_DONE   BIT(13)
>> +#define MSC_STAT_DATA_TRAN_DONE BIT(12)
>> +#define MSC_STAT_END_CMD_RESBIT(11)
>> +#define MSC_STAT_DATA_FIFO_AFULLBIT(10)
>> +#define MSC_STAT_IS_READWAITBIT(9)
>> +#define MSC_STAT_CLK_EN BIT(8)
>> +#define MSC_STAT_DATA_FIFO_FULL BIT(7)
>> +#define MSC_STAT_DATA_FIFO_EMPTYBIT(6)
>> +#define MSC_STAT_CRC_RES_ERRBIT(5)
>> +#define MSC_STAT_CRC_READ_ERROR BIT(4)
>> +#define MSC_STAT_CRC_WRITE_ERRORBIT(2)
>> +#define MSC_STAT_CRC_WRITE_ERROR_NOSTS  BIT(4)
>> +#define MSC_STAT_TIME_OUT_RES   BIT(1)
>> +#define MSC_STAT_TIME_OUT_READ  BIT(0)
>> +
>> +/* MSC Bus Clock Control Register (MSC_CLKRT) */
>>

Re: [U-Boot] [PATCH 08/14] mmc: Add JZ47xx SD/MMC controller driver

2016-11-27 Thread Jaehoon Chung 
Hi Marek,

On 11/26/2016 07:32 AM, Marek Vasut wrote:
> From: Paul Burton 
> 
> Add driver for the JZ47xx MSC controller.

There are some checkpatch error and warings. Could you fix them?

And i don't know what means MSC?

> 
> Signed-off-by: Marek Vasut 
> Cc: Daniel Schwierzeck 
> Cc: Paul Burton 
> ---
>  drivers/mmc/Kconfig  |   6 +
>  drivers/mmc/Makefile |   1 +
>  drivers/mmc/jz_mmc.c | 443 
> +++
>  3 files changed, 450 insertions(+)
>  create mode 100644 drivers/mmc/jz_mmc.c
> 
> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
> index aca438b8..761b886 100644
> --- a/drivers/mmc/Kconfig
> +++ b/drivers/mmc/Kconfig
> @@ -102,6 +102,12 @@ config MMC_UNIPHIER
>   help
> This selects support for the SD/MMC Host Controller on UniPhier SoCs.
>  
> +config JZ47XX_MMC
> + bool "Ingenic JZ47xx SD/MMC Host Controller support"
> + depends on ARCH_JZ47XX
> + help
> +   This selects support for the SD Card Controller on Ingenic JZ47xx 
> SoCs.
> +
>  config SANDBOX_MMC
>   bool "Sandbox MMC support"
>   depends on MMC && SANDBOX
> diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
> index d850758..5f7cca3 100644
> --- a/drivers/mmc/Makefile
> +++ b/drivers/mmc/Makefile
> @@ -57,6 +57,7 @@ obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
>  obj-$(CONFIG_MMC_UNIPHIER) += uniphier-sd.o
>  obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o
>  obj-$(CONFIG_ROCKCHIP_SDHCI) += rockchip_sdhci.o
> +obj-$(CONFIG_JZ47XX_MMC) += jz_mmc.o
>  
>  ifdef CONFIG_SPL_BUILD
>  obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o
> diff --git a/drivers/mmc/jz_mmc.c b/drivers/mmc/jz_mmc.c
> new file mode 100644
> index 000..213fe63
> --- /dev/null
> +++ b/drivers/mmc/jz_mmc.c
> @@ -0,0 +1,443 @@
> +/*
> + * Ingenic JZ MMC driver
> + *
> + * Copyright (c) 2013 Imagination Technologies
> + * Author: Paul Burton 
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +/* Registers */
> +#define MSC_STRPCL   0x000
> +#define MSC_STAT 0x004
> +#define MSC_CLKRT0x008
> +#define MSC_CMDAT0x00c
> +#define MSC_RESTO0x010
> +#define MSC_RDTO 0x014
> +#define MSC_BLKLEN   0x018
> +#define MSC_NOB  0x01c
> +#define MSC_SNOB 0x020
> +#define MSC_IMASK0x024
> +#define MSC_IREG 0x028
> +#define MSC_CMD  0x02c
> +#define MSC_ARG  0x030
> +#define MSC_RES  0x034
> +#define MSC_RXFIFO   0x038
> +#define MSC_TXFIFO   0x03c
> +#define MSC_LPM  0x040
> +#define MSC_DMAC 0x044
> +#define MSC_DMANDA   0x048
> +#define MSC_DMADA0x04c
> +#define MSC_DMALEN   0x050
> +#define MSC_DMACMD   0x054
> +#define MSC_CTRL20x058
> +#define MSC_RTCNT0x05c
> +#define MSC_DBG  0x0fc
> +
> +/* MSC Clock and Control Register (MSC_STRPCL) */
> +
> +#define MSC_STRPCL_EXIT_MULTIPLE BIT(7)
> +#define MSC_STRPCL_EXIT_TRANSFER BIT(6)
> +#define MSC_STRPCL_START_READWAITBIT(5)
> +#define MSC_STRPCL_STOP_READWAIT BIT(4)
> +#define MSC_STRPCL_RESET BIT(3)
> +#define MSC_STRPCL_START_OP  BIT(2)
> +#define MSC_STRPCL_CLOCK_CONTROL_STOPBIT(0)
> +#define MSC_STRPCL_CLOCK_CONTROL_START   BIT(1)
> +
> +/* MSC Status Register (MSC_STAT) */
> +
> +#define MSC_STAT_AUTO_CMD_DONE   BIT(31)
> +#define MSC_STAT_IS_RESETTINGBIT(15)
> +#define MSC_STAT_SDIO_INT_ACTIVE BIT(14)
> +#define MSC_STAT_PRG_DONEBIT(13)
> +#define MSC_STAT_DATA_TRAN_DONE  BIT(12)
> +#define MSC_STAT_END_CMD_RES BIT(11)
> +#define MSC_STAT_DATA_FIFO_AFULL BIT(10)
> +#define MSC_STAT_IS_READWAIT BIT(9)
> +#define MSC_STAT_CLK_EN  BIT(8)
> +#define MSC_STAT_DATA_FIFO_FULL  BIT(7)
> +#define MSC_STAT_DATA_FIFO_EMPTY BIT(6)
> +#define MSC_STAT_CRC_RES_ERR BIT(5)
> +#define MSC_STAT_CRC_READ_ERROR  BIT(4)
> +#define MSC_STAT_CRC_WRITE_ERROR BIT(2)
> +#define MSC_STAT_CRC_WRITE_ERROR_NOSTS   BIT(4)
> +#define MSC_STAT_TIME_OUT_RESBIT(1)
> +#define MSC_STAT_TIME_OUT_READ   BIT(0)
> +
> +/* MSC Bus Clock Control Register (MSC_CLKRT) */
> +#define MSC_CLKRT_CLK_RATE_MASK  0x7
> +
> +/* MSC Command Sequence Control Register (MSC_CMDAT) */
> +
> +#define MSC_CMDAT_IO_ABORT   BIT(11)
> +#define

[U-Boot] [PATCH 08/14] mmc: Add JZ47xx SD/MMC controller driver

2016-11-25 Thread Marek Vasut 
From: Paul Burton 

Add driver for the JZ47xx MSC controller.

Signed-off-by: Marek Vasut 
Cc: Daniel Schwierzeck 
Cc: Paul Burton 
---
 drivers/mmc/Kconfig  |   6 +
 drivers/mmc/Makefile |   1 +
 drivers/mmc/jz_mmc.c | 443 +++
 3 files changed, 450 insertions(+)
 create mode 100644 drivers/mmc/jz_mmc.c

diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index aca438b8..761b886 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -102,6 +102,12 @@ config MMC_UNIPHIER
help
  This selects support for the SD/MMC Host Controller on UniPhier SoCs.
 
+config JZ47XX_MMC
+   bool "Ingenic JZ47xx SD/MMC Host Controller support"
+   depends on ARCH_JZ47XX
+   help
+ This selects support for the SD Card Controller on Ingenic JZ47xx 
SoCs.
+
 config SANDBOX_MMC
bool "Sandbox MMC support"
depends on MMC && SANDBOX
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index d850758..5f7cca3 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -57,6 +57,7 @@ obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o
 obj-$(CONFIG_MMC_UNIPHIER) += uniphier-sd.o
 obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o
 obj-$(CONFIG_ROCKCHIP_SDHCI) += rockchip_sdhci.o
+obj-$(CONFIG_JZ47XX_MMC) += jz_mmc.o
 
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_SPL_MMC_BOOT) += fsl_esdhc_spl.o
diff --git a/drivers/mmc/jz_mmc.c b/drivers/mmc/jz_mmc.c
new file mode 100644
index 000..213fe63
--- /dev/null
+++ b/drivers/mmc/jz_mmc.c
@@ -0,0 +1,443 @@
+/*
+ * Ingenic JZ MMC driver
+ *
+ * Copyright (c) 2013 Imagination Technologies
+ * Author: Paul Burton 
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* Registers */
+#define MSC_STRPCL 0x000
+#define MSC_STAT   0x004
+#define MSC_CLKRT  0x008
+#define MSC_CMDAT  0x00c
+#define MSC_RESTO  0x010
+#define MSC_RDTO   0x014
+#define MSC_BLKLEN 0x018
+#define MSC_NOB0x01c
+#define MSC_SNOB   0x020
+#define MSC_IMASK  0x024
+#define MSC_IREG   0x028
+#define MSC_CMD0x02c
+#define MSC_ARG0x030
+#define MSC_RES0x034
+#define MSC_RXFIFO 0x038
+#define MSC_TXFIFO 0x03c
+#define MSC_LPM0x040
+#define MSC_DMAC   0x044
+#define MSC_DMANDA 0x048
+#define MSC_DMADA  0x04c
+#define MSC_DMALEN 0x050
+#define MSC_DMACMD 0x054
+#define MSC_CTRL2  0x058
+#define MSC_RTCNT  0x05c
+#define MSC_DBG0x0fc
+
+/* MSC Clock and Control Register (MSC_STRPCL) */
+
+#define MSC_STRPCL_EXIT_MULTIPLE   BIT(7)
+#define MSC_STRPCL_EXIT_TRANSFER   BIT(6)
+#define MSC_STRPCL_START_READWAIT  BIT(5)
+#define MSC_STRPCL_STOP_READWAIT   BIT(4)
+#define MSC_STRPCL_RESET   BIT(3)
+#define MSC_STRPCL_START_OPBIT(2)
+#define MSC_STRPCL_CLOCK_CONTROL_STOP  BIT(0)
+#define MSC_STRPCL_CLOCK_CONTROL_START BIT(1)
+
+/* MSC Status Register (MSC_STAT) */
+
+#define MSC_STAT_AUTO_CMD_DONE BIT(31)
+#define MSC_STAT_IS_RESETTING  BIT(15)
+#define MSC_STAT_SDIO_INT_ACTIVE   BIT(14)
+#define MSC_STAT_PRG_DONE  BIT(13)
+#define MSC_STAT_DATA_TRAN_DONEBIT(12)
+#define MSC_STAT_END_CMD_RES   BIT(11)
+#define MSC_STAT_DATA_FIFO_AFULL   BIT(10)
+#define MSC_STAT_IS_READWAIT   BIT(9)
+#define MSC_STAT_CLK_ENBIT(8)
+#define MSC_STAT_DATA_FIFO_FULLBIT(7)
+#define MSC_STAT_DATA_FIFO_EMPTY   BIT(6)
+#define MSC_STAT_CRC_RES_ERR   BIT(5)
+#define MSC_STAT_CRC_READ_ERRORBIT(4)
+#define MSC_STAT_CRC_WRITE_ERROR   BIT(2)
+#define MSC_STAT_CRC_WRITE_ERROR_NOSTS BIT(4)
+#define MSC_STAT_TIME_OUT_RES  BIT(1)
+#define MSC_STAT_TIME_OUT_READ BIT(0)
+
+/* MSC Bus Clock Control Register (MSC_CLKRT) */
+#define MSC_CLKRT_CLK_RATE_MASK0x7
+
+/* MSC Command Sequence Control Register (MSC_CMDAT) */
+
+#define MSC_CMDAT_IO_ABORT BIT(11)
+#define MSC_CMDAT_BUS_WIDTH_1BIT   (0x0 << 9)
+#define MSC_CMDAT_BUS_WIDTH_4BIT   (0x2 << 9)
+#define MSC_CMDAT_DMA_EN   BIT(8)
+#define MSC_CMDAT_INIT BIT(7)
+#define MSC_CMDAT_BUSY BIT(6)
+#define MSC_CMDAT_STREAM_BLOCK BIT(5)
+#define MSC_CMDAT_WRITEBIT(4)
+#define MSC_CMDAT_DATA_EN